From: Chunyan Zhang <zhang.lyra@gmail.com>
To: Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Orson Zhai <orsonzhai@gmail.com>,
Baolin Wang <baolin.wang7@gmail.com>,
Chunyan Zhang <zhang.lyra@gmail.com>,
Xiaolong Zhang <xiaolong.zhang@unisoc.com>,
Chunyan Zhang <chunyan.zhang@unisoc.com>
Subject: [PATCH v3 1/7] clk: sprd: add gate for pll clocks
Date: Fri, 10 Jan 2020 14:09:12 +0800 [thread overview]
Message-ID: <20200110060918.18416-2-zhang.lyra@gmail.com> (raw)
In-Reply-To: <20200110060918.18416-1-zhang.lyra@gmail.com>
From: Xiaolong Zhang <xiaolong.zhang@unisoc.com>
Some sprd's gate clocks are used to the switch of pll, which
need to wait a certain time for stable after being enabled.
Signed-off-by: Xiaolong Zhang <xiaolong.zhang@unisoc.com>
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
---
drivers/clk/sprd/gate.c | 17 +++++++++++++++++
drivers/clk/sprd/gate.h | 21 +++++++++++++++++++--
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sprd/gate.c b/drivers/clk/sprd/gate.c
index f59d1936b412..574cfc116bbc 100644
--- a/drivers/clk/sprd/gate.c
+++ b/drivers/clk/sprd/gate.c
@@ -79,6 +79,17 @@ static int sprd_sc_gate_enable(struct clk_hw *hw)
return 0;
}
+
+static int sprd_pll_sc_gate_prepare(struct clk_hw *hw)
+{
+ struct sprd_gate *sg = hw_to_sprd_gate(hw);
+
+ clk_sc_gate_toggle(sg, true);
+ udelay(sg->udelay);
+
+ return 0;
+}
+
static int sprd_gate_is_enabled(struct clk_hw *hw)
{
struct sprd_gate *sg = hw_to_sprd_gate(hw);
@@ -109,3 +120,9 @@ const struct clk_ops sprd_sc_gate_ops = {
};
EXPORT_SYMBOL_GPL(sprd_sc_gate_ops);
+const struct clk_ops sprd_pll_sc_gate_ops = {
+ .unprepare = sprd_sc_gate_disable,
+ .prepare = sprd_pll_sc_gate_prepare,
+ .is_enabled = sprd_gate_is_enabled,
+};
+EXPORT_SYMBOL_GPL(sprd_pll_sc_gate_ops);
diff --git a/drivers/clk/sprd/gate.h b/drivers/clk/sprd/gate.h
index dc352ea55e1f..d380d77b8dce 100644
--- a/drivers/clk/sprd/gate.h
+++ b/drivers/clk/sprd/gate.h
@@ -14,16 +14,19 @@ struct sprd_gate {
u32 enable_mask;
u16 flags;
u16 sc_offset;
+ u16 udelay;
struct sprd_clk_common common;
};
-#define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
- _enable_mask, _flags, _gate_flags, _ops) \
+#define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
+ _sc_offset, _enable_mask, _flags, \
+ _gate_flags, _udelay, _ops) \
struct sprd_gate _struct = { \
.enable_mask = _enable_mask, \
.sc_offset = _sc_offset, \
.flags = _gate_flags, \
+ .udelay = _udelay, \
.common = { \
.regmap = NULL, \
.reg = _reg, \
@@ -34,6 +37,12 @@ struct sprd_gate {
} \
}
+#define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
+ _enable_mask, _flags, _gate_flags, _ops) \
+ SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
+ _sc_offset, _enable_mask, _flags, \
+ _gate_flags, 0, _ops)
+
#define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \
_enable_mask, _flags, _gate_flags) \
SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0, \
@@ -46,6 +55,13 @@ struct sprd_gate {
_enable_mask, _flags, _gate_flags, \
&sprd_sc_gate_ops)
+#define SPRD_PLL_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \
+ _enable_mask, _flags, _gate_flags, _udelay) \
+ SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
+ _sc_offset, _enable_mask, _flags, \
+ _gate_flags, _udelay, \
+ &sprd_pll_sc_gate_ops)
+
static inline struct sprd_gate *hw_to_sprd_gate(const struct clk_hw *hw)
{
struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
@@ -55,5 +71,6 @@ static inline struct sprd_gate *hw_to_sprd_gate(const struct clk_hw *hw)
extern const struct clk_ops sprd_gate_ops;
extern const struct clk_ops sprd_sc_gate_ops;
+extern const struct clk_ops sprd_pll_sc_gate_ops;
#endif /* _SPRD_GATE_H_ */
--
2.20.1
next prev parent reply other threads:[~2020-01-10 6:10 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-10 6:09 [PATCH v3 0/7] Add clocks for Unisoc's SC9863A Chunyan Zhang
2020-01-10 6:09 ` Chunyan Zhang [this message]
2020-01-10 6:09 ` [PATCH v3 2/7] dt-bindings: clk: sprd: rename the common file name sprd.txt to SoC specific Chunyan Zhang
2020-01-10 6:09 ` [PATCH v3 3/7] dt-bindings: clk: sprd: add bindings for sc9863a clock controller Chunyan Zhang
2020-01-10 6:09 ` [PATCH v3 4/7] clk: sprd: Add dt-bindings include file for SC9863A Chunyan Zhang
2020-01-10 6:09 ` [PATCH v3 5/7] clk: sprd: Add macros for referencing parents without strings Chunyan Zhang
2020-01-10 6:09 ` [PATCH v3 6/7] clk: sprd: support to get regmap from parent node Chunyan Zhang
2020-01-10 6:09 ` [PATCH v3 7/7] clk: sprd: add clocks support for SC9863A Chunyan Zhang
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