From: Thierry Reding <thierry.reding@gmail.com>
To: Dmitry Osipenko <digetx@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH RESEND for 5.6 v1 1/3] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation
Date: Fri, 10 Jan 2020 15:52:16 +0100 [thread overview]
Message-ID: <20200110145216.GI2233456@ulmo> (raw)
In-Reply-To: <20191218184407.25790-1-digetx@gmail.com>
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On Wed, Dec 18, 2019 at 09:44:05PM +0300, Dmitry Osipenko wrote:
> UART clock is divided using divisor values from DLM/DLL registers when
> enable-bit is unset in clk register and clk's divider configuration isn't
> taken onto account in this case. This doesn't cause any problems, but
> let's add a check for the divider's enable-bit state, for consistency.
>
> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
> drivers/clk/tegra/clk-divider.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
All three patches applied to for-5.6/clk, thanks.
Thierry
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prev parent reply other threads:[~2020-01-10 14:52 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-18 18:44 [PATCH RESEND for 5.6 v1 1/3] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation Dmitry Osipenko
2019-12-18 18:44 ` [PATCH RESEND for 5.6 v1 2/3] clk: tegra20/30: Don't pre-initialize displays parent clock Dmitry Osipenko
2020-01-07 23:21 ` Dmitry Osipenko
2019-12-18 18:44 ` [PATCH RESEND for 5.6 v1 3/3] clk: tegra20/30: Explicitly set parent clock for Video Decoder Dmitry Osipenko
2020-01-10 14:52 ` Thierry Reding [this message]
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