From: Shawn Guo <shawnguo@kernel.org>
To: Peng Fan <peng.fan@nxp.com>, Leonard Crestez <leonard.crestez@nxp.com>
Cc: "sboyd@kernel.org" <sboyd@kernel.org>,
"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
"festevam@gmail.com" <festevam@gmail.com>,
Abel Vesa <abel.vesa@nxp.com>,
"kernel@pengutronix.de" <kernel@pengutronix.de>,
dl-linux-imx <linux-imx@nxp.com>,
Aisheng Dong <aisheng.dong@nxp.com>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Anson Huang <anson.huang@nxp.com>, Jacky Bai <ping.bai@nxp.com>
Subject: Re: [PATCH 1/3] clk: imx: pll14xx: avoid modify dram pll
Date: Sun, 12 Jan 2020 10:32:49 +0800 [thread overview]
Message-ID: <20200112023248.GY4456@T480> (raw)
In-Reply-To: <1577696903-27870-2-git-send-email-peng.fan@nxp.com>
On Mon, Dec 30, 2019 at 09:13:00AM +0000, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> The dram pll is only expected to be modified in firmware,
> so we should only support read clk frequency in Linux Kernel.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
@Leonard, do you agree?
Shawn
> ---
> drivers/clk/imx/clk-pll14xx.c | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
> index 5b0519a81a7a..9288b21d4d59 100644
> --- a/drivers/clk/imx/clk-pll14xx.c
> +++ b/drivers/clk/imx/clk-pll14xx.c
> @@ -69,8 +69,6 @@ struct imx_pll14xx_clk imx_1443x_pll = {
>
> struct imx_pll14xx_clk imx_1443x_dram_pll = {
> .type = PLL_1443X,
> - .rate_table = imx_pll1443x_tbl,
> - .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
> .flags = CLK_GET_RATE_NOCACHE,
> };
>
> @@ -376,6 +374,10 @@ static const struct clk_ops clk_pll1443x_ops = {
> .set_rate = clk_pll1443x_set_rate,
> };
>
> +static const struct clk_ops clk_pll1443x_min_ops = {
> + .recalc_rate = clk_pll1443x_recalc_rate,
> +};
> +
> struct clk_hw *imx_clk_hw_pll14xx(const char *name, const char *parent_name,
> void __iomem *base,
> const struct imx_pll14xx_clk *pll_clk)
> @@ -403,7 +405,10 @@ struct clk_hw *imx_clk_hw_pll14xx(const char *name, const char *parent_name,
> init.ops = &clk_pll1416x_ops;
> break;
> case PLL_1443X:
> - init.ops = &clk_pll1443x_ops;
> + if (!pll_clk->rate_table)
> + init.ops = &clk_pll1443x_min_ops;
> + else
> + init.ops = &clk_pll1443x_ops;
> break;
> default:
> pr_err("%s: Unknown pll type for pll clk %s\n",
> --
> 2.16.4
>
next prev parent reply other threads:[~2020-01-12 2:33 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-30 9:12 [PATCH 0/3] clk: imx: avoid modify dram pll and improve for pll14xx Peng Fan
2019-12-30 9:13 ` [PATCH 1/3] clk: imx: pll14xx: avoid modify dram pll Peng Fan
2020-01-12 2:32 ` Shawn Guo [this message]
2020-01-14 0:11 ` Leonard Crestez
2019-12-30 9:13 ` [PATCH 2/3] clk: imx: pll14xx: introduce imx_clk_hw_pll14xx_flags Peng Fan
2019-12-30 9:13 ` [PATCH 3/3] clk: imx: imx8m: use imx_clk_hw_pll14xx_flags for dram pll Peng Fan
2020-01-12 2:40 ` Shawn Guo
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