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From: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Joel Stanley <joel@jms.id.au>,
	Andrew Jeffery <andrew@aj.id.au>
Cc: linux-clk@vger.kernel.org, linux-aspeed@lists.ozlabs.org,
	Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Subject: [PATCH] clk: ast2600: enable BCLK for PCI/PCIe bus always
Date: Mon, 13 Jan 2020 13:34:53 -0800
Message-ID: <20200113213453.27108-1-jae.hyun.yoo@linux.intel.com> (raw)

BCLK for PCI/PCIe bus should be enabled always with having the
CLK_IS_CRITICAL flag otherwise it will be disabled at kernel late
initcall phase as an unused clock, and eventually it causes
unexpected behavior on BMC features that are connected to the host
through PCI/PCIe bus.

Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
---
 drivers/clk/clk-ast2600.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
index 392d01705b97..42bfdc16bf7a 100644
--- a/drivers/clk/clk-ast2600.c
+++ b/drivers/clk/clk-ast2600.c
@@ -64,7 +64,7 @@ static const struct aspeed_gate_data aspeed_g6_gates[] = {
 	[ASPEED_CLK_GATE_GCLK]		= {  2,  7, "gclk-gate",	NULL,	 0 },	/* 2D engine */
 	/* vclk parent - dclk/d1clk/hclk/mclk */
 	[ASPEED_CLK_GATE_VCLK]		= {  3,  6, "vclk-gate",	NULL,	 0 },	/* Video Capture */
-	[ASPEED_CLK_GATE_BCLK]		= {  4,  8, "bclk-gate",	"bclk",	 0 }, /* PCIe/PCI */
+	[ASPEED_CLK_GATE_BCLK]		= {  4,  8, "bclk-gate",	"bclk",	 CLK_IS_CRITICAL }, /* PCIe/PCI */
 	/* From dpll */
 	[ASPEED_CLK_GATE_DCLK]		= {  5, -1, "dclk-gate",	NULL,	 CLK_IS_CRITICAL }, /* DAC */
 	[ASPEED_CLK_GATE_REF0CLK]	= {  6, -1, "ref0clk-gate",	"clkin", CLK_IS_CRITICAL },
-- 
2.17.1


             reply index

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-13 21:34 Jae Hyun Yoo [this message]
2020-01-14  6:15 ` Joel Stanley
2020-01-14 19:53   ` Jae Hyun Yoo
2020-01-15  5:43     ` Joel Stanley
2020-01-15 20:21       ` Jae Hyun Yoo

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