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From: Dinh Nguyen <dinguyen@kernel.org>
To: sboyd@kernel.org
Cc: dinguyen@kernel.org, mturquette@baylibre.com, linux-clk@vger.kernel.org
Subject: [PATCH 1/2] clk: stratix10: use do_div() for 64-bit calculation
Date: Tue, 14 Jan 2020 10:07:25 -0600
Message-ID: <20200114160726.19771-1-dinguyen@kernel.org> (raw)

do_div() macro to perform u64 division and guards against overflow if
the result is too large for the unsigned long return type.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
 drivers/clk/socfpga/clk-pll-s10.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
index 4705eb544f01..8d7b1d0c4664 100644
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -39,7 +39,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
 	/* read VCO1 reg for numerator and denominator */
 	reg = readl(socfpgaclk->hw.reg);
 	refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
-	vco_freq = (unsigned long long)parent_rate / refdiv;
+
+	vco_freq = parent_rate;
+	do_div(vco_freq, refdiv);
 
 	/* Read mdiv and fdiv from the fdbck register */
 	reg = readl(socfpgaclk->hw.reg + 0x4);
-- 
2.17.1


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Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-14 16:07 Dinh Nguyen [this message]
2020-01-14 16:07 ` [PATCH 2/2] clk: socfpga: stratix10: simplify paramter passing Dinh Nguyen
2020-02-04 15:29   ` Dinh Nguyen
2020-02-12 23:42     ` Stephen Boyd
2020-02-13 15:04       ` Dinh Nguyen
2020-02-12 23:42   ` Stephen Boyd
2020-02-12 23:42 ` [PATCH 1/2] clk: stratix10: use do_div() for 64-bit calculation Stephen Boyd

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