[PATCHv1 0/2] Add FSYS2 power domain for MMC driver

[PATCHv1 0/2] Add FSYS2 power domain for MMC driver

[Anand Moon]

This patches add the power domain for MMC driver,
but somehow the suspend/resume feature is broken
so any input on how to fix this.

Also on similar lines I tried to add power domain
FSYS for usb3 and usb2 nodes but this time
it failed to load the kernel, so how can I reslove
this issue.

-Anand

Anand Moon (2):
  ARM: dts: exynos: Add FSYS2 power domain to Exynos542x
  clk: samsung: exynos542x: Move FSYS2 subsystem clocks to its sub-CMU

 arch/arm/boot/dts/exynos5420.dtsi    | 10 ++++++++++
 drivers/clk/samsung/clk-exynos5420.c | 24 +++++++++++++++++++++---
 2 files changed, 31 insertions(+), 3 deletions(-)

-- 
2.25.0

[PATCHv1 1/2] ARM: dts: exynos: Add FSYS2 power domain to Exynos542x

[Anand Moon]

Add a power domain FSYS2 for MMC device present in Exynos542x/5800 SoCs.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index b672080e7469..2ba8a57303cd 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -210,6 +210,7 @@ mmc_0: mmc@12200000 {
 			clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 			clock-names = "biu", "ciu";
 			fifo-depth = <0x40>;
+			power-domains = <&fsys2_pd>;
 			status = "disabled";
 		};
 
@@ -222,6 +223,7 @@ mmc_1: mmc@12210000 {
 			clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 			clock-names = "biu", "ciu";
 			fifo-depth = <0x40>;
+			power-domains = <&fsys2_pd>;
 			status = "disabled";
 		};
 
@@ -234,6 +236,7 @@ mmc_2: mmc@12220000 {
 			clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 			clock-names = "biu", "ciu";
 			fifo-depth = <0x40>;
+			power-domains = <&fsys2_pd>;
 			status = "disabled";
 		};
 
@@ -396,6 +399,13 @@ msc_pd: power-domain@10044120 {
 			label = "MSC";
 		};
 
+		fsys2_pd: power-domain@10044160 {
+			compatible = "samsung,exynos4210-pd";
+			reg = <0x10044160 0x20>;
+			#power-domain-cells = <0>;
+			label = "FSYS2";
+		};
+
 		pinctrl_0: pinctrl@13400000 {
 			compatible = "samsung,exynos5420-pinctrl";
 			reg = <0x13400000 0x1000>;
-- 
2.25.0

[PATCHv1 2/2] clk: samsung: exynos542x: Move FSYS2 subsystem clocks to its sub-CMU

[Anand Moon]

Move FSYS2 clk setting to sub-CMU block to support power domain on/off
sequences for mmc driver.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
Note: This patch might be missing some more setting
as suspend/resume feature is broken.
I could not resolve this issue at my end, any input or
suggetion to improve this code.
---
 drivers/clk/samsung/clk-exynos5420.c | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index c9e5a1fb6653..3597e8d62445 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1035,9 +1035,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
 	GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
 	GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
 	GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
-	GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
-	GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
-	GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
 	GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
 			GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
@@ -1258,6 +1255,17 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
 	{ DIV2_RATIO0, 0, 0x30 },	/* DIV dout_gscl_blk_300 */
 };
 
+static const struct samsung_gate_clock exynos5x_fsys2_gate_clks[] __initconst = {
+	GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
+	GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
+	GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
+};
+
+static struct exynos5_subcmu_reg_dump exynos5x_fsys2_suspend_regs[] = {
+	{ GATE_IP_FSYS, 0xff, 0xff },   /* FSYS gates */
+	{ SRC_TOP3, 0, BIT(12) },       /* MUX_ACLK_200_FSYS2_SEL */
+};
+
 static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = {
 	GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9,
 	     CLK_SET_RATE_PARENT, 0),
@@ -1376,12 +1384,21 @@ static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
 	.pd_name	= "MAU",
 };
 
+static const struct exynos5_subcmu_info exynos5x_fsys2_subcmu = {
+	.gate_clks	= exynos5x_fsys2_gate_clks,
+	.nr_gate_clks	= ARRAY_SIZE(exynos5x_fsys2_gate_clks),
+	.suspend_regs	= exynos5x_fsys2_suspend_regs,
+	.nr_suspend_regs = ARRAY_SIZE(exynos5x_fsys2_suspend_regs),
+	.pd_name	= "FSYS2",
+};
+
 static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
 	&exynos5x_disp_subcmu,
 	&exynos5x_gsc_subcmu,
 	&exynos5x_g3d_subcmu,
 	&exynos5x_mfc_subcmu,
 	&exynos5x_mscl_subcmu,
+	&exynos5x_fsys2_subcmu,
 };
 
 static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
@@ -1391,6 +1408,7 @@ static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
 	&exynos5x_mfc_subcmu,
 	&exynos5x_mscl_subcmu,
 	&exynos5800_mau_subcmu,
+	&exynos5x_fsys2_subcmu,
 };
 
 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
-- 
2.25.0

Re: [PATCHv1 0/2] Add FSYS2 power domain for MMC driver

[Krzysztof Kozlowski]

On Wed, Feb 12, 2020 at 12:02:35PM +0000, Anand Moon wrote:
> This patches add the power domain for MMC driver,
> but somehow the suspend/resume feature is broken
> so any input on how to fix this.

I think S2R was working on XU3-family after Marek's fixes, so you mean
that these patches break it?

Best regards,
Krzysztof


> 
> Also on similar lines I tried to add power domain
> FSYS for usb3 and usb2 nodes but this time
> it failed to load the kernel, so how can I reslove
> this issue.
> 
> -Anand
> 
> Anand Moon (2):
>   ARM: dts: exynos: Add FSYS2 power domain to Exynos542x
>   clk: samsung: exynos542x: Move FSYS2 subsystem clocks to its sub-CMU
> 
>  arch/arm/boot/dts/exynos5420.dtsi    | 10 ++++++++++
>  drivers/clk/samsung/clk-exynos5420.c | 24 +++++++++++++++++++++---
>  2 files changed, 31 insertions(+), 3 deletions(-)
> 
> -- 
> 2.25.0
> 

Re: [PATCHv1 0/2] Add FSYS2 power domain for MMC driver

[Anand Moon]

hi Krzysztof,

On Thu, 13 Feb 2020 at 15:47, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On Wed, Feb 12, 2020 at 12:02:35PM +0000, Anand Moon wrote:
> > This patches add the power domain for MMC driver,
> > but somehow the suspend/resume feature is broken
> > so any input on how to fix this.
>
> I think S2R was working on XU3-family after Marek's fixes, so you mean
> that these patches break it?
>
Yes I my testing mmc driver failed to come up after suspend.

But I see below in power domain, Just to confirm.
#  cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
domain                          status          slaves
    /device                                             runtime status
----------------------------------------------------------------------
CAM                             off-0
FSYS2                           on
    /devices/platform/soc/10010000.clock-controller/exynos5-subcmu.6.auto
 active
    /devices/platform/soc/12200000.mmc                  active
    /devices/platform/soc/12220000.mmc                  active

# powerdebug -d
FSYS2:
current_state: on
active_time: 29016991 ms
total_idle_time: 4037 ms
Idle States:
             State            Time
             S0               4037
Devices:
         /devices/platform/soc/10010000.clock-controller/exynos5-subcmu.6.auto
         /devices/platform/soc/12200000.mmc
         /devices/platform/soc/12220000.mmc

> Best regards,
> Krzysztof
>
>

-Anand

> >
> > Also on similar lines I tried to add power domain
> > FSYS for usb3 and usb2 nodes but this time
> > it failed to load the kernel, so how can I reslove
> > this issue.
> >
> > -Anand
> >
> > Anand Moon (2):
> >   ARM: dts: exynos: Add FSYS2 power domain to Exynos542x
> >   clk: samsung: exynos542x: Move FSYS2 subsystem clocks to its sub-CMU
> >
> >  arch/arm/boot/dts/exynos5420.dtsi    | 10 ++++++++++
> >  drivers/clk/samsung/clk-exynos5420.c | 24 +++++++++++++++++++++---
> >  2 files changed, 31 insertions(+), 3 deletions(-)
> >
> > --
> > 2.25.0
> >

Re: [PATCHv1 0/2] Add FSYS2 power domain for MMC driver

[Krzysztof Kozlowski]

On Thu, Feb 13, 2020 at 06:58:51PM +0530, Anand Moon wrote:
> hi Krzysztof,
> 
> On Thu, 13 Feb 2020 at 15:47, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >
> > On Wed, Feb 12, 2020 at 12:02:35PM +0000, Anand Moon wrote:
> > > This patches add the power domain for MMC driver,
> > > but somehow the suspend/resume feature is broken
> > > so any input on how to fix this.
> >
> > I think S2R was working on XU3-family after Marek's fixes, so you mean
> > that these patches break it?
> >
> Yes I my testing mmc driver failed to come up after suspend.

Patches breaking systems should be clearly marked as work in progress,
e.g.  by using RFC instead of PATCH in the title.

This patchset cannot be applied.

You probably have to figure out some missing dependencies, e.g. in
clocks/power domains/pinctrl.

Best regards,
Krzysztof

Re: [PATCHv1 0/2] Add FSYS2 power domain for MMC driver

[Anand Moon]

Hi Krzysztof,

On Thu, 13 Feb 2020 at 21:13, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On Thu, Feb 13, 2020 at 06:58:51PM +0530, Anand Moon wrote:
> > hi Krzysztof,
> >
> > On Thu, 13 Feb 2020 at 15:47, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> > >
> > > On Wed, Feb 12, 2020 at 12:02:35PM +0000, Anand Moon wrote:
> > > > This patches add the power domain for MMC driver,
> > > > but somehow the suspend/resume feature is broken
> > > > so any input on how to fix this.
> > >
> > > I think S2R was working on XU3-family after Marek's fixes, so you mean
> > > that these patches break it?
> > >
> > Yes I my testing mmc driver failed to come up after suspend.
>
> Patches breaking systems should be clearly marked as work in progress,
> e.g.  by using RFC instead of PATCH in the title.
>
> This patchset cannot be applied.
>
Ok

> You probably have to figure out some missing dependencies, e.g. in
> clocks/power domains/pinctrl.
>
I have tried to add some more missing code, but this FSYS2 power domain
power off during suspend and their is no resume after this. Do know why.

[root@alarm ~]# echo N | sudo tee /sys/module/printk/parameters/console_suspend
N
[root@alarm ~]# echo 1 > /sys/power/pm_debug_messages
[root@alarm ~]# time rtcwake -s 60 -m mem
rtcwake: assuming RTC uses UTC ...
rtcwake: wakeup from "mem" using /dev/rtc0 at Mon Feb 24 05:18:02 2020
[   81.955425] PM: suspend entry (deep)
[   81.961793] Filesystems sync: 0.003 seconds
[   81.978051] Freezing user space processes ... (elapsed 0.009 seconds) done.
[   81.993635] OOM killer disabled.
[   81.996531] Freezing remaining freezable tasks ... (elapsed 0.002
seconds) done.
[   82.229718] wake enabled for irq 160
[   82.445441] wake enabled for irq 164
[   82.461752] samsung-pinctrl 13400000.pinctrl: Setting external
wakeup interrupt mask: 0xffffffe7
[   82.481095] Disabling non-boot CPUs ...

My observation, all the device get suspended and USB device come alive
after resume.
since mmc device is in sill in suspended state it dose not resume.

So can we stop the FSYS2 power domain to getting disabled during suspend.
Or is their any other thing I am missing.
How to enable more debug print for power management ?
How can I debug future ?

-Anand