On Tue, Mar 10, 2020 at 07:43:12PM +0300, Dmitry Osipenko wrote: > 10.03.2020 18:20, Thierry Reding пишет: > > From: Joseph Lo > > > > This is the initial patch for Tegra210 EMC frequency scaling. It has the > > code to program various aspects of the EMC that are standardized, but it > > does not yet include the specific programming sequence needed for clock > > scaling. > > > > The driver is designed to support LPDDR4 SDRAM. Devices that use LPDDR4 > > need to perform training of the RAM before it can be used. Firmware will > > perform this training during early boot and pass a table of supported > > frequencies to the kernel via device tree. > > > > For the frequencies above 800 MHz, periodic retraining is needed to > > compensate for changes in timing. This periodic training will have to be > > performed until the frequency drops back to or below 800 MHz. > > > > This driver provides helpers used during this runtime retraining that > > will be used by the sequence specific code in a follow-up patch. > > > > Based on work by Peter De Schrijver . > > > > Signed-off-by: Joseph Lo > > Signed-off-by: Thierry Reding > > --- > > Changes in v5: > > - major rework and cleanup > > > > drivers/memory/tegra/tegra210-emc.c | 1952 +++++++++++++++++++++------ > > drivers/memory/tegra/tegra210-emc.h | 893 +++++++++++- > > 2 files changed, 2390 insertions(+), 455 deletions(-) > > > > diff --git a/drivers/memory/tegra/tegra210-emc.c b/drivers/memory/tegra/tegra210-emc.c > > index 80ea14d1e6ce..4ea8fb70a4fd 100644 > > --- a/drivers/memory/tegra/tegra210-emc.c > > +++ b/drivers/memory/tegra/tegra210-emc.c > > @@ -1,6 +1,6 @@ > > // SPDX-License-Identifier: GPL-2.0 > > /* > > - * Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved. > > + * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved. > > */ > > Would be nice to avoid all the unnecessary changes, like the one above > and then all the code's removals/reshuffling. > > Such that a new patch was a clean addition to a previous patch, instead > of a re-write. I think this is the result of me messing up a rebase. The EMC driver changes added in the clock driver patch should've been in this patch, which would've made this a clean addition. I'll reshuffle the code for the next revision. Thanks for pointing that out. Thierry