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Wed, 27 May 2020 19:18:27 -0700 (PDT) Received: from xps15 ([64.188.179.252]) by smtp.gmail.com with ESMTPSA id s71sm2536741ilc.32.2020.05.27.19.18.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2020 19:18:27 -0700 (PDT) Received: (nullmailer pid 3229541 invoked by uid 1000); Thu, 28 May 2020 02:18:26 -0000 Date: Wed, 27 May 2020 20:18:26 -0600 From: Rob Herring To: Lars Povlsen List-Id: Cc: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , Michael Turquette , devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandre Belloni Subject: Re: [PATCH 10/14] dt-bindings: clock: sparx5: Add Sparx5 SoC DPLL clock Message-ID: <20200528021826.GA3221035@bogus> References: <20200513125532.24585-1-lars.povlsen@microchip.com> <20200513125532.24585-11-lars.povlsen@microchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200513125532.24585-11-lars.povlsen@microchip.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On Wed, May 13, 2020 at 02:55:28PM +0200, Lars Povlsen wrote: > This add the DT bindings documentation for the Sparx5 SoC DPLL clock > > Reviewed-by: Alexandre Belloni > Signed-off-by: Lars Povlsen > --- > .../bindings/clock/microchip,sparx5-dpll.yaml | 46 +++++++++++++++++++ > 1 file changed, 46 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml > > diff --git a/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml > new file mode 100644 > index 0000000000000..594007d8fc59a > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml > @@ -0,0 +1,46 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip Sparx5 DPLL Clock > + > +maintainers: > + - Lars Povlsen > + > +description: | > + The Sparx5 DPLL clock controller generates and supplies clock to > + various peripherals within the SoC. > + > + This binding uses common clock bindings > + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt > + > +properties: > + compatible: > + const: microchip,sparx5-dpll > + > + reg: > + items: > + - description: dpll registers For a single entry, just: maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + # Clock provider for eMMC: > + - | > + clks: clks@61110000c { clock-controller@1110000c { > + compatible = "microchip,sparx5-dpll"; > + #clock-cells = <1>; > + reg = <0x1110000c 0x24>; Looks like this is a sub-block in some other h/w block. What's the parent device? That should be described and this should be part of it either as a single node or a child node. Without a complete view of what this block has I can't provide any guidance. Rob