From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEC37C433DF for ; Mon, 15 Jun 2020 13:33:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CD2092071A for ; Mon, 15 Jun 2020 13:33:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="PeG9ybGM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730518AbgFONdO (ORCPT ); Mon, 15 Jun 2020 09:33:14 -0400 Received: from esa1.microchip.iphmx.com ([68.232.147.91]:62186 "EHLO esa1.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729875AbgFONdF (ORCPT ); Mon, 15 Jun 2020 09:33:05 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1592227985; x=1623763985; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HrI/NoAQfZ2v5GhtxSsX0gula1thXocA0/KftR1JTdE=; b=PeG9ybGMVX//OtWaLoga6oDwVJ5xB+euaM/c3GfhypkflcyRbkQweR/j 1yjv/slLqD+LkPreiB1Qd+zP+PrbJELmVOL+jUvRdOw+8W3HM1lyYRc0r nE3Mho32xMcblw1IDQKkSN38IH8UblNSYKLqf5uZIHWX4qDjsg+1ee05h PHDGg5oOlwGx/vh+dfp60neIuYiplIQSn31FsgNQfDpBY0miYRpS6LrAS jCXRwdLBYO68AMFkvXhuOmqhXjBOf1GhbQY6LG6NHod4c5FOmwli7BNyi OFEJAXQeCnkA30MMAQ8JwfCecVxUE2eS+bMwh1OyQwcXszLvms17dnyv0 A==; IronPort-SDR: bKtjbPcRRjnKVFZ0EQtzwttXV4ry9JL+rkMnv+6qCqTJwotoGraDPUseAE2zM2mjbYCUk/OnY3 Qe7U4w2bS/MKnF1NU2PeRaoPgmkZhZsaa1LfS+24WRpgWDt+RT9lYiCLVlMN/jyfgOs7pPgT9C 9ZNXvHPWRJyUDxItvOCv8q3Obv9AwPYle2a+NyK7cbWyKS5pA993/CV0BZbyZ9AGvKz5TKI4ER QLe3zYHm3dg9QL6tT2QD5s8MagxASaIGR/R5cV0wwDH1SHu+DC6lXZ+2QgIAIgqu8bD6FG1uu5 xRo= X-IronPort-AV: E=Sophos;i="5.73,514,1583218800"; d="scan'208";a="83619432" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 15 Jun 2020 06:33:04 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 15 Jun 2020 06:33:04 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Mon, 15 Jun 2020 06:33:01 -0700 From: Lars Povlsen List-Id: To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH v3 02/10] arm64: sparx5: Add support for Microchip 2xA53 SoC Date: Mon, 15 Jun 2020 15:32:34 +0200 Message-ID: <20200615133242.24911-3-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200615133242.24911-1-lars.povlsen@microchip.com> References: <20200615133242.24911-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This adds support for the Microchip Sparx5 ARMv8-based SoC family of TSN-capable gigabit switches. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- MAINTAINERS | 8 ++++++++ arch/arm64/Kconfig.platforms | 14 ++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 68f21d46614c4..13553b77ed4f7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2111,6 +2111,14 @@ X: drivers/net/wireless/atmel/ N: at91 N: atmel +ARM/Microchip Sparx5 SoC support +M: Lars Povlsen +M: Steen Hegelund +M: Microchip Linux Driver Support +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +N: sparx5 + ARM/MIOA701 MACHINE SUPPORT M: Robert Jarzmik L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 8dd05b2a925c5..8939e4e6e34c2 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -89,6 +89,20 @@ config ARCH_EXYNOS help This enables support for ARMv8 based Samsung Exynos SoC family. +config ARCH_SPARX5 + bool "ARMv8 based Microchip Sparx5 SoC family" + select PINCTRL + select DW_APB_TIMER_OF + help + This enables support for the Microchip Sparx5 ARMv8-based + SoC family of TSN-capable gigabit switches. + + The SparX-5 Ethernet switch family provides a rich set of + switching features such as advanced TCAM-based VLAN and QoS + processing enabling delivery of differentiated services, and + security through TCAM-based frame processing using versatile + content aware processor (VCAP). + config ARCH_K3 bool "Texas Instruments Inc. K3 multicore SoC architecture" select PM_GENERIC_DOMAINS if PM -- 2.27.0