* [PATCH 0/2] clk: meson: g12a: Add the NNA source clocks
@ 2020-06-10 8:30 Neil Armstrong
2020-06-10 8:30 ` [PATCH 1/2] dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs Neil Armstrong
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Neil Armstrong @ 2020-06-10 8:30 UTC (permalink / raw)
To: jbrunet
Cc: linux-clk, linux-amlogic, linux-arm-kernel, linux-kernel, Neil Armstrong
This patchset adds the Neural Network Accelerator source clocks present
on the Amlogic SM1 SoCs family.
Dmitry Shmidt (2):
dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs
clk: meson: g12a: Add support for NNA CLK source clocks
drivers/clk/meson/g12a.c | 119 ++++++++++++++++++++++++++
drivers/clk/meson/g12a.h | 7 +-
include/dt-bindings/clock/g12a-clkc.h | 2 +
3 files changed, 127 insertions(+), 1 deletion(-)
--
2.22.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs
2020-06-10 8:30 [PATCH 0/2] clk: meson: g12a: Add the NNA source clocks Neil Armstrong
@ 2020-06-10 8:30 ` Neil Armstrong
2020-06-17 22:18 ` Rob Herring
2020-06-10 8:30 ` [PATCH 2/2] clk: meson: g12a: Add support for NNA CLK source clocks Neil Armstrong
2020-06-24 10:11 ` [PATCH 0/2] clk: meson: g12a: Add the NNA " Jerome Brunet
2 siblings, 1 reply; 5+ messages in thread
From: Neil Armstrong @ 2020-06-10 8:30 UTC (permalink / raw)
To: jbrunet, devicetree
Cc: linux-clk, linux-amlogic, linux-arm-kernel, linux-kernel,
Dmitry Shmidt, Neil Armstrong
From: Dmitry Shmidt <dimitrysh@google.com>
This adds the Neural Network Accelerator IP source clocks.
Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
include/dt-bindings/clock/g12a-clkc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
index b0d65d73db96..40d49940d8a8 100644
--- a/include/dt-bindings/clock/g12a-clkc.h
+++ b/include/dt-bindings/clock/g12a-clkc.h
@@ -145,5 +145,7 @@
#define CLKID_CPU3_CLK 255
#define CLKID_SPICC0_SCLK 258
#define CLKID_SPICC1_SCLK 261
+#define CLKID_NNA_AXI_CLK 264
+#define CLKID_NNA_CORE_CLK 267
#endif /* __G12A_CLKC_H */
--
2.22.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] clk: meson: g12a: Add support for NNA CLK source clocks
2020-06-10 8:30 [PATCH 0/2] clk: meson: g12a: Add the NNA source clocks Neil Armstrong
2020-06-10 8:30 ` [PATCH 1/2] dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs Neil Armstrong
@ 2020-06-10 8:30 ` Neil Armstrong
2020-06-24 10:11 ` [PATCH 0/2] clk: meson: g12a: Add the NNA " Jerome Brunet
2 siblings, 0 replies; 5+ messages in thread
From: Neil Armstrong @ 2020-06-10 8:30 UTC (permalink / raw)
To: jbrunet
Cc: linux-clk, linux-amlogic, linux-arm-kernel, linux-kernel,
Dmitry Shmidt, Neil Armstrong
From: Dmitry Shmidt <dimitrysh@google.com>
This adds the Neural Network Accelerator source clocks hierarchy, it's
2 simple composite clocks to feed the AXI interface and the Core of
the Neural Network Accelerator IP.
This IP is only present on the Amlogic SM1 SoCs family.
Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/clk/meson/g12a.c | 119 +++++++++++++++++++++++++++++++++++++++
drivers/clk/meson/g12a.h | 7 ++-
2 files changed, 125 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 30c15766ebb1..9803d44bb157 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -3981,6 +3981,113 @@ static struct clk_regmap g12a_spicc1_sclk = {
},
};
+/* Neural Network Accelerator source clock */
+
+static const struct clk_parent_data nna_clk_parent_data[] = {
+ { .fw_name = "xtal", },
+ { .hw = &g12a_gp0_pll.hw, },
+ { .hw = &g12a_hifi_pll.hw, },
+ { .hw = &g12a_fclk_div2p5.hw, },
+ { .hw = &g12a_fclk_div3.hw, },
+ { .hw = &g12a_fclk_div4.hw, },
+ { .hw = &g12a_fclk_div5.hw, },
+ { .hw = &g12a_fclk_div7.hw },
+};
+
+static struct clk_regmap sm1_nna_axi_clk_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_NNA_CLK_CNTL,
+ .mask = 7,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "nna_axi_clk_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = nna_clk_parent_data,
+ .num_parents = ARRAY_SIZE(nna_clk_parent_data),
+ },
+};
+
+static struct clk_regmap sm1_nna_axi_clk_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_NNA_CLK_CNTL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "nna_axi_clk_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sm1_nna_axi_clk_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap sm1_nna_axi_clk = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_NNA_CLK_CNTL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "nna_axi_clk",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sm1_nna_axi_clk_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap sm1_nna_core_clk_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_NNA_CLK_CNTL,
+ .mask = 7,
+ .shift = 25,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "nna_core_clk_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = nna_clk_parent_data,
+ .num_parents = ARRAY_SIZE(nna_clk_parent_data),
+ },
+};
+
+static struct clk_regmap sm1_nna_core_clk_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_NNA_CLK_CNTL,
+ .shift = 16,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "nna_core_clk_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sm1_nna_core_clk_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap sm1_nna_core_clk = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_NNA_CLK_CNTL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "nna_core_clk",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sm1_nna_core_clk_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
#define MESON_GATE(_name, _reg, _bit) \
MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
@@ -4779,6 +4886,12 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
[CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
[CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
[CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
+ [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
+ [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
+ [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
+ [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
+ [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
+ [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -5020,6 +5133,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
&g12a_spicc1_sclk_sel,
&g12a_spicc1_sclk_div,
&g12a_spicc1_sclk,
+ &sm1_nna_axi_clk_sel,
+ &sm1_nna_axi_clk_div,
+ &sm1_nna_axi_clk,
+ &sm1_nna_core_clk_sel,
+ &sm1_nna_core_clk_div,
+ &sm1_nna_core_clk,
};
static const struct reg_sequence g12a_init_regs[] = {
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index a8852556836e..69b6a69549c7 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -70,6 +70,7 @@
#define HHI_MALI_CLK_CNTL 0x1b0
#define HHI_VPU_CLKC_CNTL 0x1b4
#define HHI_VPU_CLK_CNTL 0x1bC
+#define HHI_NNA_CLK_CNTL 0x1C8
#define HHI_HDMI_CLK_CNTL 0x1CC
#define HHI_VDEC_CLK_CNTL 0x1E0
#define HHI_VDEC2_CLK_CNTL 0x1E4
@@ -259,8 +260,12 @@
#define CLKID_SPICC0_SCLK_DIV 257
#define CLKID_SPICC1_SCLK_SEL 259
#define CLKID_SPICC1_SCLK_DIV 260
+#define CLKID_NNA_AXI_CLK_SEL 262
+#define CLKID_NNA_AXI_CLK_DIV 263
+#define CLKID_NNA_CORE_CLK_SEL 265
+#define CLKID_NNA_CORE_CLK_DIV 266
-#define NR_CLKS 262
+#define NR_CLKS 268
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/g12a-clkc.h>
--
2.22.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs
2020-06-10 8:30 ` [PATCH 1/2] dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs Neil Armstrong
@ 2020-06-17 22:18 ` Rob Herring
0 siblings, 0 replies; 5+ messages in thread
From: Rob Herring @ 2020-06-17 22:18 UTC (permalink / raw)
To: Neil Armstrong
Cc: devicetree, linux-kernel, linux-amlogic, Dmitry Shmidt, jbrunet,
linux-clk, linux-arm-kernel
On Wed, 10 Jun 2020 10:30:11 +0200, Neil Armstrong wrote:
> From: Dmitry Shmidt <dimitrysh@google.com>
>
> This adds the Neural Network Accelerator IP source clocks.
>
> Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> include/dt-bindings/clock/g12a-clkc.h | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 0/2] clk: meson: g12a: Add the NNA source clocks
2020-06-10 8:30 [PATCH 0/2] clk: meson: g12a: Add the NNA source clocks Neil Armstrong
2020-06-10 8:30 ` [PATCH 1/2] dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs Neil Armstrong
2020-06-10 8:30 ` [PATCH 2/2] clk: meson: g12a: Add support for NNA CLK source clocks Neil Armstrong
@ 2020-06-24 10:11 ` Jerome Brunet
2 siblings, 0 replies; 5+ messages in thread
From: Jerome Brunet @ 2020-06-24 10:11 UTC (permalink / raw)
To: Neil Armstrong; +Cc: linux-clk, linux-amlogic, linux-arm-kernel, linux-kernel
On Wed 10 Jun 2020 at 10:30, Neil Armstrong <narmstrong@baylibre.com> wrote:
> This patchset adds the Neural Network Accelerator source clocks present
> on the Amlogic SM1 SoCs family.
>
> Dmitry Shmidt (2):
> dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs
> clk: meson: g12a: Add support for NNA CLK source clocks
>
> drivers/clk/meson/g12a.c | 119 ++++++++++++++++++++++++++
> drivers/clk/meson/g12a.h | 7 +-
> include/dt-bindings/clock/g12a-clkc.h | 2 +
> 3 files changed, 127 insertions(+), 1 deletion(-)
Applied, Thx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-06-24 10:11 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2020-06-10 8:30 [PATCH 0/2] clk: meson: g12a: Add the NNA source clocks Neil Armstrong
2020-06-10 8:30 ` [PATCH 1/2] dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs Neil Armstrong
2020-06-17 22:18 ` Rob Herring
2020-06-10 8:30 ` [PATCH 2/2] clk: meson: g12a: Add support for NNA CLK source clocks Neil Armstrong
2020-06-24 10:11 ` [PATCH 0/2] clk: meson: g12a: Add the NNA " Jerome Brunet
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