From: Konrad Dybcio <konradybcio@gmail.com>
To: skrzynka@konradybcio.pl
Cc: Konrad Dybcio <konradybcio@gmail.com>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>,
Kees Cook <keescook@chromium.org>,
Anton Vorontsov <anton@enomsg.org>,
Colin Cross <ccross@android.com>, Tony Luck <tony.luck@intel.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 16/21] arm64: dts: qcom: msm8994: Add I2C, SPI and BLSP DMA nodes
Date: Sat, 20 Jun 2020 16:46:32 +0200 [thread overview]
Message-ID: <20200620144639.335093-17-konradybcio@gmail.com> (raw)
In-Reply-To: <20200620144639.335093-1-konradybcio@gmail.com>
Add support for I2C and SPI buses to enable peripherals
such as touchscreens or sensors. Also add DMA nodes and
configuration
Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
---
arch/arm64/boot/dts/qcom/msm8994.dtsi | 137 +++++++++++++++++++++++++-
1 file changed, 136 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
index 20e859eb1318..7a7b22e2d5cc 100644
--- a/arch/arm64/boot/dts/qcom/msm8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
@@ -233,14 +233,40 @@ msmgpio: pinctrl@fd510000 {
#interrupt-cells = <2>;
};
+ blsp1_dma: dma@f9904000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0xf9904000 0x19000>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ num-channels = <18>;
+ qcom,num-ees = <4>;
+ };
+
+ blsp2_dma: dma@f9944000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0xf9944000 0x19000>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ num-channels = <18>;
+ qcom,num-ees = <4>;
+ };
+
blsp1_uart2: serial@f991e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991e000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
+ status = "disabled";
};
blsp2_uart2: serial@f995e000 {
@@ -250,6 +276,115 @@ blsp2_uart2: serial@f995e000 {
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
+ dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ blsp_i2c1: i2c@f9923000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9923000 0x500>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_default>;
+ pinctrl-1 = <&i2c1_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_i2c2: i2c@f9924000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9924000 0x500>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <355000>;
+ dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_default>;
+ pinctrl-1 = <&i2c2_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ /* I2C3 doesn't exist */
+
+ blsp_i2c4: i2c@f9926000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9926000 0x500>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <355000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c4_default>;
+ pinctrl-1 = <&i2c4_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_i2c5: i2c@f9967000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9967000 0x500>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <355000>;
+ dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_default>;
+ pinctrl-1 = <&i2c5_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_i2c6: i2c@f9928000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0xf9928000 0x500>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <355000>;
+ dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c6_default>;
+ pinctrl-1 = <&i2c6_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_spi0: spi@f9923000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0xf9923000 0x500>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ spi-max-frequency = <19200000>;
+ dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_spi0_default>;
+ pinctrl-1 = <&blsp1_spi0_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
};
spmi_bus: qcom,spmi@fc4c0000 {
--
2.27.0
next prev parent reply other threads:[~2020-06-20 14:48 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-20 14:46 [PATCH 00/21] MSM8994 peripheral enablement, DTS updates Konrad Dybcio
2020-06-20 14:46 ` [PATCH 01/21] clk: qcom: smd: Add support for MSM8992/4 rpm clocks Konrad Dybcio
2020-06-23 19:11 ` Stephen Boyd
2020-06-20 14:46 ` [PATCH 02/21] arm64: dts: qcom: msm8994: Add SPMI PMIC arbiter device Konrad Dybcio
2020-06-20 14:46 ` [PATCH 03/21] arm64: dts: qcom: msm8994: Add a proper CPU map Konrad Dybcio
2020-06-20 14:46 ` [PATCH 04/21] arm64: dts: qcom: msm8994: Wrap clock nodes into clocks {} Konrad Dybcio
2020-06-20 14:46 ` [PATCH 05/21] arm64: dts: qcom: msm8994: Rename the smem node and remove its unit address Konrad Dybcio
2020-06-20 14:46 ` [PATCH 06/21] arm64: dts: qcom: msm8994: Rename clock_gcc label to gcc Konrad Dybcio
2020-06-20 14:46 ` [PATCH 07/21] arm64: dts: qcom: msm8994: Add apcs node Konrad Dybcio
2020-06-20 14:46 ` [PATCH 08/21] arm64: dts: qcom: msm8994: Add pmu node Konrad Dybcio
2020-06-20 14:46 ` [PATCH 09/21] arm64: dts: qcom: msm8994: Add PSCI node Konrad Dybcio
2020-06-20 14:46 ` [PATCH 10/21] arm64: dts: qcom: msm8994: Add support for SMD RPM Konrad Dybcio
2020-06-20 14:46 ` [PATCH 11/21] arm64: dts: qcom: msm8994: Add SDHCI1 node Konrad Dybcio
2020-06-20 14:46 ` [PATCH 12/21] arm64: dts: qcom: msm8994: Remove qcom,msm-id and qcom-pmic-id properties Konrad Dybcio
2020-06-20 14:46 ` [PATCH 13/21] arm64: dts: qcom: msm8994: Make comments C style Konrad Dybcio
2020-06-20 14:46 ` [PATCH 14/21] arm64: dts: qcom: msm8994: Add SCM node Konrad Dybcio
2020-06-20 14:46 ` [PATCH 15/21] arm64: dts: qcom: msm8994: Add BLSP2 UART2 node Konrad Dybcio
2020-06-20 14:46 ` Konrad Dybcio [this message]
2020-06-20 14:46 ` [PATCH 17/21] arm64: dts: qcom: Update msm8994 pin configuration Konrad Dybcio
2020-06-20 14:46 ` [PATCH 18/21] regulator: qcom_smd: Fix pmi8994 label Konrad Dybcio
2020-06-21 6:05 ` Bjorn Andersson
2020-06-20 14:46 ` [PATCH 19/21] arm64: dts: qcom: angler: Add qcom,msm-id and pmic-id Konrad Dybcio
2020-06-20 14:46 ` [PATCH 20/21] arm64: dts: qcom: Add support for Sony Xperia Z5 (SoMC Sumire-RoW) Konrad Dybcio
2020-06-20 14:46 ` [PATCH 21/21] arm64: dts: qcom: Move msm8994-smd-rpm contents to lg-bullhead Konrad Dybcio
2020-06-23 12:39 ` [PATCH 00/21] MSM8994 peripheral enablement, DTS updates Mark Brown
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