* [PATCH 0/2] clk: meson8b: add two missing gate clocks
@ 2020-06-29 20:39 Martin Blumenstingl
2020-06-29 20:39 ` [PATCH 1/2] clk: meson: meson8b: add the vclk_en gate clock Martin Blumenstingl
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Martin Blumenstingl @ 2020-06-29 20:39 UTC (permalink / raw)
To: jbrunet, linux-amlogic
Cc: narmstrong, linux-clk, linux-arm-kernel, linux-kernel,
Martin Blumenstingl
While trying to figure out how to set up the video clocks on the 32-bit
SoCs I found that the current clock tree is missing two gates. This adds
the missing gates based on evidence found in the public S805 datasheet,
the GXBB clock driver and 3.10 vendor kernel.
I didn't add any Fixes tag because this clock tree is still read-only
and the HDMI PLL (the top-most clock in this tree) needs more work as
well.
Martin Blumenstingl (2):
clk: meson: meson8b: add the vclk_en gate clock
clk: meson: meson8b: add the vclk2_en gate clock
drivers/clk/meson/meson8b.c | 60 ++++++++++++++++++++++++++++++-------
drivers/clk/meson/meson8b.h | 4 ++-
2 files changed, 53 insertions(+), 11 deletions(-)
--
2.27.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] clk: meson: meson8b: add the vclk_en gate clock
2020-06-29 20:39 [PATCH 0/2] clk: meson8b: add two missing gate clocks Martin Blumenstingl
@ 2020-06-29 20:39 ` Martin Blumenstingl
2020-06-29 20:39 ` [PATCH 2/2] clk: meson: meson8b: add the vclk2_en " Martin Blumenstingl
2020-07-09 17:16 ` [PATCH 0/2] clk: meson8b: add two missing gate clocks Jerome Brunet
2 siblings, 0 replies; 4+ messages in thread
From: Martin Blumenstingl @ 2020-06-29 20:39 UTC (permalink / raw)
To: jbrunet, linux-amlogic
Cc: narmstrong, linux-clk, linux-arm-kernel, linux-kernel,
Martin Blumenstingl
HHI_VID_CLK_CNTL[19] is documented as CLK_EN0. This description is the
same in the public S912 datasheet and the GXBB driver calls this gate
"vclk". Add this gate clock to the Meson8/Meson8b/Meson8m2 clock
controller because it's needed to make the video output work.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/clk/meson/meson8b.c | 30 +++++++++++++++++++++++++-----
drivers/clk/meson/meson8b.h | 3 ++-
2 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 3d826711c820..d5b90d61a530 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -1204,6 +1204,22 @@ static struct clk_regmap meson8b_vclk_in_en = {
},
};
+static struct clk_regmap meson8b_vclk_en = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_VID_CLK_CNTL,
+ .bit_idx = 19,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "vclk_en",
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &meson8b_vclk_in_en.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
static struct clk_regmap meson8b_vclk_div1_gate = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VID_CLK_CNTL,
@@ -1213,7 +1229,7 @@ static struct clk_regmap meson8b_vclk_div1_gate = {
.name = "vclk_div1_en",
.ops = &clk_regmap_gate_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
- &meson8b_vclk_in_en.hw
+ &meson8b_vclk_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1227,7 +1243,7 @@ static struct clk_fixed_factor meson8b_vclk_div2_div = {
.name = "vclk_div2",
.ops = &clk_fixed_factor_ops,
.parent_hws = (const struct clk_hw *[]) {
- &meson8b_vclk_in_en.hw
+ &meson8b_vclk_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1257,7 +1273,7 @@ static struct clk_fixed_factor meson8b_vclk_div4_div = {
.name = "vclk_div4",
.ops = &clk_fixed_factor_ops,
.parent_hws = (const struct clk_hw *[]) {
- &meson8b_vclk_in_en.hw
+ &meson8b_vclk_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1287,7 +1303,7 @@ static struct clk_fixed_factor meson8b_vclk_div6_div = {
.name = "vclk_div6",
.ops = &clk_fixed_factor_ops,
.parent_hws = (const struct clk_hw *[]) {
- &meson8b_vclk_in_en.hw
+ &meson8b_vclk_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1317,7 +1333,7 @@ static struct clk_fixed_factor meson8b_vclk_div12_div = {
.name = "vclk_div12",
.ops = &clk_fixed_factor_ops,
.parent_hws = (const struct clk_hw *[]) {
- &meson8b_vclk_in_en.hw
+ &meson8b_vclk_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2820,6 +2836,7 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
[CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
[CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
[CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
+ [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
[CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
@@ -3025,6 +3042,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
[CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
[CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
[CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
+ [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
[CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
@@ -3241,6 +3259,7 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
[CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
[CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
[CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
+ [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
[CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
@@ -3443,6 +3462,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
&meson8b_vid_pll_final_div,
&meson8b_vclk_in_sel,
&meson8b_vclk_in_en,
+ &meson8b_vclk_en,
&meson8b_vclk_div1_gate,
&meson8b_vclk_div2_div_gate,
&meson8b_vclk_div4_div_gate,
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index cd38ae2a9cb5..c8ab2a632295 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -180,8 +180,9 @@
#define CLKID_CTS_AMCLK_DIV 208
#define CLKID_CTS_MCLK_I958_SEL 210
#define CLKID_CTS_MCLK_I958_DIV 211
+#define CLKID_VCLK_EN 214
-#define CLK_NR_CLKS 214
+#define CLK_NR_CLKS 215
/*
* include the CLKID and RESETID that have
--
2.27.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] clk: meson: meson8b: add the vclk2_en gate clock
2020-06-29 20:39 [PATCH 0/2] clk: meson8b: add two missing gate clocks Martin Blumenstingl
2020-06-29 20:39 ` [PATCH 1/2] clk: meson: meson8b: add the vclk_en gate clock Martin Blumenstingl
@ 2020-06-29 20:39 ` Martin Blumenstingl
2020-07-09 17:16 ` [PATCH 0/2] clk: meson8b: add two missing gate clocks Jerome Brunet
2 siblings, 0 replies; 4+ messages in thread
From: Martin Blumenstingl @ 2020-06-29 20:39 UTC (permalink / raw)
To: jbrunet, linux-amlogic
Cc: narmstrong, linux-clk, linux-arm-kernel, linux-kernel,
Martin Blumenstingl
HHI_VIID_CLK_CNTL[19] is not part of the public S805 datasheet. However,
the GXBB driver defines this bit as a gate called "vclk2" and in the
3.10 kernel GPL code dump the following line can found:
WRITE_LCD_CBUS_REG_BITS(HHI_VIID_CLK_CNTL, 0, 19, 1); //disable vclk2_en
Add this gate clock to the Meson8/Meson8b/Meson8m2 clock controller to
complete the VCLK2 clock tree.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/clk/meson/meson8b.c | 30 +++++++++++++++++++++++++-----
drivers/clk/meson/meson8b.h | 3 ++-
2 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index d5b90d61a530..862f0756b50f 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -1387,6 +1387,22 @@ static struct clk_regmap meson8b_vclk2_clk_in_en = {
},
};
+static struct clk_regmap meson8b_vclk2_clk_en = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_VIID_CLK_DIV,
+ .bit_idx = 19,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "vclk2_en",
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &meson8b_vclk2_clk_in_en.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
static struct clk_regmap meson8b_vclk2_div1_gate = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_VIID_CLK_DIV,
@@ -1396,7 +1412,7 @@ static struct clk_regmap meson8b_vclk2_div1_gate = {
.name = "vclk2_div1_en",
.ops = &clk_regmap_gate_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
- &meson8b_vclk2_clk_in_en.hw
+ &meson8b_vclk2_clk_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1410,7 +1426,7 @@ static struct clk_fixed_factor meson8b_vclk2_div2_div = {
.name = "vclk2_div2",
.ops = &clk_fixed_factor_ops,
.parent_hws = (const struct clk_hw *[]) {
- &meson8b_vclk2_clk_in_en.hw
+ &meson8b_vclk2_clk_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1440,7 +1456,7 @@ static struct clk_fixed_factor meson8b_vclk2_div4_div = {
.name = "vclk2_div4",
.ops = &clk_fixed_factor_ops,
.parent_hws = (const struct clk_hw *[]) {
- &meson8b_vclk2_clk_in_en.hw
+ &meson8b_vclk2_clk_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1470,7 +1486,7 @@ static struct clk_fixed_factor meson8b_vclk2_div6_div = {
.name = "vclk2_div6",
.ops = &clk_fixed_factor_ops,
.parent_hws = (const struct clk_hw *[]) {
- &meson8b_vclk2_clk_in_en.hw
+ &meson8b_vclk2_clk_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1500,7 +1516,7 @@ static struct clk_fixed_factor meson8b_vclk2_div12_div = {
.name = "vclk2_div12",
.ops = &clk_fixed_factor_ops,
.parent_hws = (const struct clk_hw *[]) {
- &meson8b_vclk2_clk_in_en.hw
+ &meson8b_vclk2_clk_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2848,6 +2864,7 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
[CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
[CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
[CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
+ [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
[CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
[CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
[CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
@@ -3054,6 +3071,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
[CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
[CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
[CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
+ [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
[CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
[CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
[CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
@@ -3271,6 +3289,7 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
[CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
[CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
[CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
+ [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
[CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
[CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
[CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
@@ -3470,6 +3489,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
&meson8b_vclk_div12_div_gate,
&meson8b_vclk2_in_sel,
&meson8b_vclk2_clk_in_en,
+ &meson8b_vclk2_clk_en,
&meson8b_vclk2_div1_gate,
&meson8b_vclk2_div2_div_gate,
&meson8b_vclk2_div4_div_gate,
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index c8ab2a632295..699c5bc7c817 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -181,8 +181,9 @@
#define CLKID_CTS_MCLK_I958_SEL 210
#define CLKID_CTS_MCLK_I958_DIV 211
#define CLKID_VCLK_EN 214
+#define CLKID_VCLK2_EN 215
-#define CLK_NR_CLKS 215
+#define CLK_NR_CLKS 216
/*
* include the CLKID and RESETID that have
--
2.27.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 0/2] clk: meson8b: add two missing gate clocks
2020-06-29 20:39 [PATCH 0/2] clk: meson8b: add two missing gate clocks Martin Blumenstingl
2020-06-29 20:39 ` [PATCH 1/2] clk: meson: meson8b: add the vclk_en gate clock Martin Blumenstingl
2020-06-29 20:39 ` [PATCH 2/2] clk: meson: meson8b: add the vclk2_en " Martin Blumenstingl
@ 2020-07-09 17:16 ` Jerome Brunet
2 siblings, 0 replies; 4+ messages in thread
From: Jerome Brunet @ 2020-07-09 17:16 UTC (permalink / raw)
To: Martin Blumenstingl, linux-amlogic
Cc: narmstrong, linux-clk, linux-arm-kernel, linux-kernel
On Mon 29 Jun 2020 at 22:39, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
> While trying to figure out how to set up the video clocks on the 32-bit
> SoCs I found that the current clock tree is missing two gates. This adds
> the missing gates based on evidence found in the public S805 datasheet,
> the GXBB clock driver and 3.10 vendor kernel.
>
> I didn't add any Fixes tag because this clock tree is still read-only
> and the HDMI PLL (the top-most clock in this tree) needs more work as
> well.
>
>
> Martin Blumenstingl (2):
> clk: meson: meson8b: add the vclk_en gate clock
> clk: meson: meson8b: add the vclk2_en gate clock
>
> drivers/clk/meson/meson8b.c | 60 ++++++++++++++++++++++++++++++-------
> drivers/clk/meson/meson8b.h | 4 ++-
> 2 files changed, 53 insertions(+), 11 deletions(-)
Applied Thx.
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-07-09 17:16 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2020-06-29 20:39 [PATCH 0/2] clk: meson8b: add two missing gate clocks Martin Blumenstingl
2020-06-29 20:39 ` [PATCH 1/2] clk: meson: meson8b: add the vclk_en gate clock Martin Blumenstingl
2020-06-29 20:39 ` [PATCH 2/2] clk: meson: meson8b: add the vclk2_en " Martin Blumenstingl
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