* [PATCH v10 0/3] Add basic SoC Support for Mediatek MT6779 SoC @ 2020-07-30 13:30 Hanks Chen 2020-07-30 13:30 ` [PATCH v10 1/3] dt-bindings: pinctrl: add bindings for MediaTek " Hanks Chen ` (2 more replies) 0 siblings, 3 replies; 16+ messages in thread From: Hanks Chen @ 2020-07-30 13:30 UTC (permalink / raw) To: Linus Walleij, Rob Herring, Matthias Brugger, Michael Turquette, Stephen Boyd Cc: mtk01761, YueHaibing, Andy Teng, linux-gpio, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-clk, CC Hwang, Loda Chou, Hanks Chen Change since v10: Commit "dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC" -- remove the patches which were applied to linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=b07b616214857c9db01e2807cde2f6bba8019fc3 -- follow the latest 'dt-schema' and fix the dts sample Change since v9: Commit "dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC" -- remove driving desciprtion and reuse the generic schemas. Commit "pinctrl: mediatek: add pinctrl support for MT6779 SoC" -- fix build error to support ko. -- follow the APIs as below. Commit "arm64: dts: add dts nodes for MT6779" -- remove the clk interface of UART3 in another mail thread. https://lkml.org/lkml/2020/7/21/1444 Change since v8: Commit "dt-bindings: pinctrl: add bindings for MediaTek" -- update the format Commit "arm64: dts: add dts nodes for MT6779" -- fix the typo in uart node Change since v7: Commit "dt-bindings: pinctrl: add bindings for MediaTek" -- fix typo and change order of patch Commit "clk: mediatek: add UART0 clock support" -- add fixes tag and real name Commit "arm64: dts: add dts nodes for MT6779" -- expose all three UARTs in the dtsi Change since v6: Commit "dt-bindings: pinctrl: add bindings for MediaTek" -- fix format of bindings and add interrupt definition. Commit "pinctrl: mediatek: update pinmux definitions for" -- use the standard include path Commit "pinctrl: mediatek: avoid virtual gpio trying to set" -- remove unnecessary error handler Commit "pinctrl: mediatek: add pinctrl support for MT6779 SoC" -- add some useful help text in kconfig Commit "clk: mediatek: add UART0 clock support" -- add UART0 clock support Commit "arm64: dts: add dts nodes for MT6779" -- add "baud" and "bus" clocks for uart -- add new approach for mmsys Change since v5: 1. remove unnecessary string in commit message Change since v4: 1. fix format of pinctrl bindings Change since v3: 1. add bindings for "mediatek,mt6779-pinctrl" 2. add some comments into the code (e.g. virtual gpio ...) 3. add Acked-by tags 4. add pmu node into dts 5. support ppi partition and fix base address in gic node of dts Change since v2: 1. add Reviewed-by tags 2. fix checkpatch warnings with strict level Change since v1: first patchset Andy Teng (1): dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC Hanks Chen (2): arm64: dts: add dts nodes for MT6779 clk: mediatek: add UART0 clock support .../pinctrl/mediatek,mt6779-pinctrl.yaml | 202 +++++++++++++ arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 ++ arch/arm64/boot/dts/mediatek/mt6779.dtsi | 271 ++++++++++++++++++ drivers/clk/mediatek/clk-mt6779.c | 2 + 5 files changed, 507 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi -- 2.18.0 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v10 1/3] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC 2020-07-30 13:30 [PATCH v10 0/3] Add basic SoC Support for Mediatek MT6779 SoC Hanks Chen @ 2020-07-30 13:30 ` Hanks Chen 2020-07-31 18:26 ` Rob Herring 2020-08-03 23:31 ` Linus Walleij 2020-07-30 13:30 ` [PATCH v10 2/3] arm64: dts: add dts nodes for MT6779 Hanks Chen 2020-07-30 13:30 ` [PATCH v10 3/3] clk: mediatek: add UART0 clock support Hanks Chen 2 siblings, 2 replies; 16+ messages in thread From: Hanks Chen @ 2020-07-30 13:30 UTC (permalink / raw) To: Linus Walleij, Rob Herring, Matthias Brugger, Michael Turquette, Stephen Boyd Cc: mtk01761, YueHaibing, Andy Teng, linux-gpio, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-clk, CC Hwang, Loda Chou, Hanks Chen From: Andy Teng <andy.teng@mediatek.com> Add devicetree bindings for MediaTek MT6779 pinctrl driver. Signed-off-by: Andy Teng <andy.teng@mediatek.com> Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> --- .../pinctrl/mediatek,mt6779-pinctrl.yaml | 202 ++++++++++++++++++ 1 file changed, 202 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml new file mode 100644 index 000000000000..152c151c27ad --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -0,0 +1,202 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT6779 Pin Controller Device Tree Bindings + +maintainers: + - Andy Teng <andy.teng@mediatek.com> + +description: |+ + The pin controller node should be the child of a syscon node with the + required property: + - compatible: "syscon" + +properties: + compatible: + const: mediatek,mt6779-pinctrl + + reg: + minItems: 9 + maxItems: 9 + + reg-names: + items: + - const: "gpio" + - const: "iocfg_rm" + - const: "iocfg_br" + - const: "iocfg_lm" + - const: "iocfg_lb" + - const: "iocfg_rt" + - const: "iocfg_lt" + - const: "iocfg_tl" + - const: "eint" + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + + gpio-ranges: + minItems: 1 + maxItems: 5 + description: | + GPIO valid number range. + + interrupt-controller: true + + interrupts: + maxItems: 1 + description: | + Specifies the summary IRQ. + + "#interrupt-cells": + const: 2 + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + - gpio-ranges + - interrupt-controller + - interrupts + - "#interrupt-cells" + +patternProperties: + '-[0-9]*$': + type: object + patternProperties: + '-pins*$': + type: object + description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input schmitt. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pinmux: + description: + integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined + as macros in boot/dts/<soc>-pinfunc.h directly. + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + input-disable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + mediatek,pull-up-adv: + description: | + Pull up setings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + required: + - pinmux + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/mt6779-pinfunc.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6779-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11c20000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11ea0000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rm", + "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", + "iocfg_lt", "iocfg_tl", + "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 210>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; + + mmc0_pins_default: mmc0-0 { + cmd-dat-pins { + pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO172__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO169__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO177__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO170__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO173__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO171__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO174__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO167__FUNC_MSDC0_CMD>; + input-enable; + mediatek,pull-up-adv = <1>; + }; + clk-pins { + pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>; + mediatek,pull-down-adv = <2>; + }; + rst-pins { + pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>; + mediatek,pull-up-adv = <0>; + }; + }; + }; + + mmc0 { + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-names = "default"; + }; + }; -- 2.18.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v10 1/3] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC 2020-07-30 13:30 ` [PATCH v10 1/3] dt-bindings: pinctrl: add bindings for MediaTek " Hanks Chen @ 2020-07-31 18:26 ` Rob Herring 2020-08-03 23:31 ` Linus Walleij 1 sibling, 0 replies; 16+ messages in thread From: Rob Herring @ 2020-07-31 18:26 UTC (permalink / raw) To: Hanks Chen Cc: Rob Herring, YueHaibing, Loda Chou, linux-mediatek, linux-gpio, Michael Turquette, Stephen Boyd, Linus Walleij, mtk01761, linux-arm-kernel, CC Hwang, linux-kernel, devicetree, linux-clk, Andy Teng, Matthias Brugger On Thu, 30 Jul 2020 21:30:14 +0800, Hanks Chen wrote: > From: Andy Teng <andy.teng@mediatek.com> > > Add devicetree bindings for MediaTek MT6779 pinctrl driver. > > Signed-off-by: Andy Teng <andy.teng@mediatek.com> > Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> > --- > .../pinctrl/mediatek,mt6779-pinctrl.yaml | 202 ++++++++++++++++++ > 1 file changed, 202 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v10 1/3] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC 2020-07-30 13:30 ` [PATCH v10 1/3] dt-bindings: pinctrl: add bindings for MediaTek " Hanks Chen 2020-07-31 18:26 ` Rob Herring @ 2020-08-03 23:31 ` Linus Walleij 1 sibling, 0 replies; 16+ messages in thread From: Linus Walleij @ 2020-08-03 23:31 UTC (permalink / raw) To: Hanks Chen Cc: Rob Herring, Matthias Brugger, Michael Turquette, Stephen Boyd, mtk01761, YueHaibing, Andy Teng, open list:GPIO SUBSYSTEM, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux ARM, moderated list:ARM/Mediatek SoC support, linux-kernel, linux-clk, CC Hwang, Loda Chou On Thu, Jul 30, 2020 at 3:30 PM Hanks Chen <hanks.chen@mediatek.com> wrote: > From: Andy Teng <andy.teng@mediatek.com> > > Add devicetree bindings for MediaTek MT6779 pinctrl driver. > > Signed-off-by: Andy Teng <andy.teng@mediatek.com> > Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> I pulled out the v9 version of this patch and applied v10 instead. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v10 2/3] arm64: dts: add dts nodes for MT6779 2020-07-30 13:30 [PATCH v10 0/3] Add basic SoC Support for Mediatek MT6779 SoC Hanks Chen 2020-07-30 13:30 ` [PATCH v10 1/3] dt-bindings: pinctrl: add bindings for MediaTek " Hanks Chen @ 2020-07-30 13:30 ` Hanks Chen 2020-08-05 2:24 ` Hanks Chen 2020-10-09 12:30 ` Matthias Brugger 2020-07-30 13:30 ` [PATCH v10 3/3] clk: mediatek: add UART0 clock support Hanks Chen 2 siblings, 2 replies; 16+ messages in thread From: Hanks Chen @ 2020-07-30 13:30 UTC (permalink / raw) To: Linus Walleij, Rob Herring, Matthias Brugger, Michael Turquette, Stephen Boyd Cc: mtk01761, YueHaibing, Andy Teng, linux-gpio, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-clk, CC Hwang, Loda Chou, Hanks Chen this adds initial MT6779 dts settings for board support, including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc. Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++ arch/arm64/boot/dts/mediatek/mt6779.dtsi | 271 ++++++++++++++++++++ 3 files changed, 303 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index a57af9da9f5c..4d1b0f9d8d1c 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts new file mode 100644 index 000000000000..164f5cbb3821 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Mars.C <mars.cheng@mediatek.com> + * + */ + +/dts-v1/; +#include "mt6779.dtsi" + +/ { + model = "MediaTek MT6779 EVB"; + compatible = "mediatek,mt6779-evb", "mediatek,mt6779"; + + aliases { + serial0 = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x1e800000>; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi new file mode 100644 index 000000000000..370f309d32de --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Mars.C <mars.cheng@mediatek.com> + * + */ + +#include <dt-bindings/clock/mt6779-clk.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/mt6779-pinfunc.h> + +/ { + compatible = "mediatek,mt6779"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x200>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x300>; + }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x400>; + }; + + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x500>; + }; + + cpu6: cpu@6 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + enable-method = "psci"; + reg = <0x600>; + }; + + cpu7: cpu@7 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + enable-method = "psci"; + reg = <0x700>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>; + }; + + clk26m: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@0c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c040000 0 0x200000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 \ + &cpu2 &cpu3 &cpu4 &cpu5>; + }; + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu6 &cpu7>; + }; + }; + + }; + + sysirq: intpol-controller@0c53a650 { + compatible = "mediatek,mt6779-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x0c53a650 0 0x50>; + }; + + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt6779-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg_ao: clock-controller@10001000 { + compatible = "mediatek,mt6779-infracfg_ao", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6779-pinctrl", "syscon"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11c20000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11ea0000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rm", + "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", + "iocfg_lt", "iocfg_tl", + "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 210>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; + }; + + apmixed: clock-controller@1000c000 { + compatible = "mediatek,mt6779-apmixed", "syscon"; + reg = <0 0x1000c000 0 0xe00>; + #clock-cells = <1>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6779-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6779-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt6779-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + audio: clock-controller@11210000 { + compatible = "mediatek,mt6779-audio", "syscon"; + reg = <0 0x11210000 0 0x1000>; + #clock-cells = <1>; + }; + + mfgcfg: clock-controller@13fbf000 { + compatible = "mediatek,mt6779-mfgcfg", "syscon"; + reg = <0 0x13fbf000 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt6779-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: clock-controller@15020000 { + compatible = "mediatek,mt6779-imgsys", "syscon"; + reg = <0 0x15020000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: clock-controller@16000000 { + compatible = "mediatek,mt6779-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@17000000 { + compatible = "mediatek,mt6779-vencsys", "syscon"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys: clock-controller@1a000000 { + compatible = "mediatek,mt6779-camsys", "syscon"; + reg = <0 0x1a000000 0 0x10000>; + #clock-cells = <1>; + }; + + ipesys: clock-controller@1b000000 { + compatible = "mediatek,mt6779-ipesys", "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + + }; +}; -- 2.18.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v10 2/3] arm64: dts: add dts nodes for MT6779 2020-07-30 13:30 ` [PATCH v10 2/3] arm64: dts: add dts nodes for MT6779 Hanks Chen @ 2020-08-05 2:24 ` Hanks Chen 2020-08-27 8:20 ` Matthias Brugger 2020-10-09 12:30 ` Matthias Brugger 1 sibling, 1 reply; 16+ messages in thread From: Hanks Chen @ 2020-08-05 2:24 UTC (permalink / raw) To: Linus Walleij, Matthias Brugger Cc: Rob Herring, Matthias Brugger, Michael Turquette, Stephen Boyd, mtk01761, YueHaibing, Andy Teng, linux-gpio, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-clk, CC Hwang, Loda Chou Hi Matthias and all, Gentle ping on this patch. Thanks Hanks Chen On Thu, 2020-07-30 at 21:30 +0800, Hanks Chen wrote: > this adds initial MT6779 dts settings for board support, > including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc. > > Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/Makefile | 1 + > arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++ > arch/arm64/boot/dts/mediatek/mt6779.dtsi | 271 ++++++++++++++++++++ > 3 files changed, 303 insertions(+) > create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts > create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile > index a57af9da9f5c..4d1b0f9d8d1c 100644 > --- a/arch/arm64/boot/dts/mediatek/Makefile > +++ b/arch/arm64/boot/dts/mediatek/Makefile > @@ -1,6 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0 > dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb > diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts > new file mode 100644 > index 000000000000..164f5cbb3821 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts > @@ -0,0 +1,31 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (c) 2019 MediaTek Inc. > + * Author: Mars.C <mars.cheng@mediatek.com> > + * > + */ > + > +/dts-v1/; > +#include "mt6779.dtsi" > + > +/ { > + model = "MediaTek MT6779 EVB"; > + compatible = "mediatek,mt6779-evb", "mediatek,mt6779"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0 0x40000000 0 0x1e800000>; > + }; > + > + chosen { > + stdout-path = "serial0:921600n8"; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi > new file mode 100644 > index 000000000000..370f309d32de > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi > @@ -0,0 +1,271 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (c) 2019 MediaTek Inc. > + * Author: Mars.C <mars.cheng@mediatek.com> > + * > + */ > + > +#include <dt-bindings/clock/mt6779-clk.h> > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/pinctrl/mt6779-pinfunc.h> > + > +/ { > + compatible = "mediatek,mt6779"; > + interrupt-parent = <&sysirq>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + reg = <0x000>; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + reg = <0x100>; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + reg = <0x200>; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + reg = <0x300>; > + }; > + > + cpu4: cpu@4 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + reg = <0x400>; > + }; > + > + cpu5: cpu@5 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + reg = <0x500>; > + }; > + > + cpu6: cpu@6 { > + device_type = "cpu"; > + compatible = "arm,cortex-a75"; > + enable-method = "psci"; > + reg = <0x600>; > + }; > + > + cpu7: cpu@7 { > + device_type = "cpu"; > + compatible = "arm,cortex-a75"; > + enable-method = "psci"; > + reg = <0x700>; > + }; > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>; > + }; > + > + clk26m: oscillator@0 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <26000000>; > + clock-output-names = "clk26m"; > + }; > + > + clk32k: oscillator@1 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32768>; > + clock-output-names = "clk32k"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + ranges; > + > + gic: interrupt-controller@0c000000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <4>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + reg = <0 0x0c000000 0 0x40000>, /* GICD */ > + <0 0x0c040000 0 0x200000>; /* GICR */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; > + > + ppi-partitions { > + ppi_cluster0: interrupt-partition-0 { > + affinity = <&cpu0 &cpu1 \ > + &cpu2 &cpu3 &cpu4 &cpu5>; > + }; > + ppi_cluster1: interrupt-partition-1 { > + affinity = <&cpu6 &cpu7>; > + }; > + }; > + > + }; > + > + sysirq: intpol-controller@0c53a650 { > + compatible = "mediatek,mt6779-sysirq", > + "mediatek,mt6577-sysirq"; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupt-parent = <&gic>; > + reg = <0 0x0c53a650 0 0x50>; > + }; > + > + topckgen: clock-controller@10000000 { > + compatible = "mediatek,mt6779-topckgen", "syscon"; > + reg = <0 0x10000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + infracfg_ao: clock-controller@10001000 { > + compatible = "mediatek,mt6779-infracfg_ao", "syscon"; > + reg = <0 0x10001000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + pio: pinctrl@10005000 { > + compatible = "mediatek,mt6779-pinctrl", "syscon"; > + reg = <0 0x10005000 0 0x1000>, > + <0 0x11c20000 0 0x1000>, > + <0 0x11d10000 0 0x1000>, > + <0 0x11e20000 0 0x1000>, > + <0 0x11e70000 0 0x1000>, > + <0 0x11ea0000 0 0x1000>, > + <0 0x11f20000 0 0x1000>, > + <0 0x11f30000 0 0x1000>, > + <0 0x1000b000 0 0x1000>; > + reg-names = "gpio", "iocfg_rm", > + "iocfg_br", "iocfg_lm", > + "iocfg_lb", "iocfg_rt", > + "iocfg_lt", "iocfg_tl", > + "eint"; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&pio 0 0 210>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + apmixed: clock-controller@1000c000 { > + compatible = "mediatek,mt6779-apmixed", "syscon"; > + reg = <0 0x1000c000 0 0xe00>; > + #clock-cells = <1>; > + }; > + > + uart0: serial@11002000 { > + compatible = "mediatek,mt6779-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11002000 0 0x400>; > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + uart1: serial@11003000 { > + compatible = "mediatek,mt6779-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11003000 0 0x400>; > + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + uart2: serial@11004000 { > + compatible = "mediatek,mt6779-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11004000 0 0x400>; > + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + audio: clock-controller@11210000 { > + compatible = "mediatek,mt6779-audio", "syscon"; > + reg = <0 0x11210000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + mfgcfg: clock-controller@13fbf000 { > + compatible = "mediatek,mt6779-mfgcfg", "syscon"; > + reg = <0 0x13fbf000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + mmsys: syscon@14000000 { > + compatible = "mediatek,mt6779-mmsys", "syscon"; > + reg = <0 0x14000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + imgsys: clock-controller@15020000 { > + compatible = "mediatek,mt6779-imgsys", "syscon"; > + reg = <0 0x15020000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vdecsys: clock-controller@16000000 { > + compatible = "mediatek,mt6779-vdecsys", "syscon"; > + reg = <0 0x16000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vencsys: clock-controller@17000000 { > + compatible = "mediatek,mt6779-vencsys", "syscon"; > + reg = <0 0x17000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + camsys: clock-controller@1a000000 { > + compatible = "mediatek,mt6779-camsys", "syscon"; > + reg = <0 0x1a000000 0 0x10000>; > + #clock-cells = <1>; > + }; > + > + ipesys: clock-controller@1b000000 { > + compatible = "mediatek,mt6779-ipesys", "syscon"; > + reg = <0 0x1b000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + }; > +}; ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v10 2/3] arm64: dts: add dts nodes for MT6779 2020-08-05 2:24 ` Hanks Chen @ 2020-08-27 8:20 ` Matthias Brugger 0 siblings, 0 replies; 16+ messages in thread From: Matthias Brugger @ 2020-08-27 8:20 UTC (permalink / raw) To: Hanks Chen, Linus Walleij Cc: Rob Herring, Michael Turquette, Stephen Boyd, mtk01761, YueHaibing, Andy Teng, linux-gpio, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-clk, CC Hwang, Loda Chou On 05/08/2020 04:24, Hanks Chen wrote: > Hi Matthias and all, > > Gentle ping on this patch. > I'm fine with the patch. I'm waiting on the clk part to be accepted, then I'll take this one. Regards, Matthias > Thanks > > > Hanks Chen > > On Thu, 2020-07-30 at 21:30 +0800, Hanks Chen wrote: >> this adds initial MT6779 dts settings for board support, >> including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc. >> >> Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> >> --- >> arch/arm64/boot/dts/mediatek/Makefile | 1 + >> arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++ >> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 271 ++++++++++++++++++++ >> 3 files changed, 303 insertions(+) >> create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts >> create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi >> >> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile >> index a57af9da9f5c..4d1b0f9d8d1c 100644 >> --- a/arch/arm64/boot/dts/mediatek/Makefile >> +++ b/arch/arm64/boot/dts/mediatek/Makefile >> @@ -1,6 +1,7 @@ >> # SPDX-License-Identifier: GPL-2.0 >> dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb >> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb >> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb >> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb >> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb >> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb >> diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts >> new file mode 100644 >> index 000000000000..164f5cbb3821 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts >> @@ -0,0 +1,31 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * Copyright (c) 2019 MediaTek Inc. >> + * Author: Mars.C <mars.cheng@mediatek.com> >> + * >> + */ >> + >> +/dts-v1/; >> +#include "mt6779.dtsi" >> + >> +/ { >> + model = "MediaTek MT6779 EVB"; >> + compatible = "mediatek,mt6779-evb", "mediatek,mt6779"; >> + >> + aliases { >> + serial0 = &uart0; >> + }; >> + >> + memory@40000000 { >> + device_type = "memory"; >> + reg = <0 0x40000000 0 0x1e800000>; >> + }; >> + >> + chosen { >> + stdout-path = "serial0:921600n8"; >> + }; >> +}; >> + >> +&uart0 { >> + status = "okay"; >> +}; >> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi >> new file mode 100644 >> index 000000000000..370f309d32de >> --- /dev/null >> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi >> @@ -0,0 +1,271 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * Copyright (c) 2019 MediaTek Inc. >> + * Author: Mars.C <mars.cheng@mediatek.com> >> + * >> + */ >> + >> +#include <dt-bindings/clock/mt6779-clk.h> >> +#include <dt-bindings/interrupt-controller/irq.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/pinctrl/mt6779-pinfunc.h> >> + >> +/ { >> + compatible = "mediatek,mt6779"; >> + interrupt-parent = <&sysirq>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + psci { >> + compatible = "arm,psci-0.2"; >> + method = "smc"; >> + }; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu0: cpu@0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a55"; >> + enable-method = "psci"; >> + reg = <0x000>; >> + }; >> + >> + cpu1: cpu@1 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a55"; >> + enable-method = "psci"; >> + reg = <0x100>; >> + }; >> + >> + cpu2: cpu@2 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a55"; >> + enable-method = "psci"; >> + reg = <0x200>; >> + }; >> + >> + cpu3: cpu@3 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a55"; >> + enable-method = "psci"; >> + reg = <0x300>; >> + }; >> + >> + cpu4: cpu@4 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a55"; >> + enable-method = "psci"; >> + reg = <0x400>; >> + }; >> + >> + cpu5: cpu@5 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a55"; >> + enable-method = "psci"; >> + reg = <0x500>; >> + }; >> + >> + cpu6: cpu@6 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a75"; >> + enable-method = "psci"; >> + reg = <0x600>; >> + }; >> + >> + cpu7: cpu@7 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a75"; >> + enable-method = "psci"; >> + reg = <0x700>; >> + }; >> + }; >> + >> + pmu { >> + compatible = "arm,armv8-pmuv3"; >> + interrupt-parent = <&gic>; >> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>; >> + }; >> + >> + clk26m: oscillator@0 { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + clock-frequency = <26000000>; >> + clock-output-names = "clk26m"; >> + }; >> + >> + clk32k: oscillator@1 { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + clock-frequency = <32768>; >> + clock-output-names = "clk32k"; >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupt-parent = <&gic>; >> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, >> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, >> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, >> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; >> + }; >> + >> + soc { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + compatible = "simple-bus"; >> + ranges; >> + >> + gic: interrupt-controller@0c000000 { >> + compatible = "arm,gic-v3"; >> + #interrupt-cells = <4>; >> + interrupt-parent = <&gic>; >> + interrupt-controller; >> + reg = <0 0x0c000000 0 0x40000>, /* GICD */ >> + <0 0x0c040000 0 0x200000>; /* GICR */ >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; >> + >> + ppi-partitions { >> + ppi_cluster0: interrupt-partition-0 { >> + affinity = <&cpu0 &cpu1 \ >> + &cpu2 &cpu3 &cpu4 &cpu5>; >> + }; >> + ppi_cluster1: interrupt-partition-1 { >> + affinity = <&cpu6 &cpu7>; >> + }; >> + }; >> + >> + }; >> + >> + sysirq: intpol-controller@0c53a650 { >> + compatible = "mediatek,mt6779-sysirq", >> + "mediatek,mt6577-sysirq"; >> + interrupt-controller; >> + #interrupt-cells = <3>; >> + interrupt-parent = <&gic>; >> + reg = <0 0x0c53a650 0 0x50>; >> + }; >> + >> + topckgen: clock-controller@10000000 { >> + compatible = "mediatek,mt6779-topckgen", "syscon"; >> + reg = <0 0x10000000 0 0x1000>; >> + #clock-cells = <1>; >> + }; >> + >> + infracfg_ao: clock-controller@10001000 { >> + compatible = "mediatek,mt6779-infracfg_ao", "syscon"; >> + reg = <0 0x10001000 0 0x1000>; >> + #clock-cells = <1>; >> + }; >> + >> + pio: pinctrl@10005000 { >> + compatible = "mediatek,mt6779-pinctrl", "syscon"; >> + reg = <0 0x10005000 0 0x1000>, >> + <0 0x11c20000 0 0x1000>, >> + <0 0x11d10000 0 0x1000>, >> + <0 0x11e20000 0 0x1000>, >> + <0 0x11e70000 0 0x1000>, >> + <0 0x11ea0000 0 0x1000>, >> + <0 0x11f20000 0 0x1000>, >> + <0 0x11f30000 0 0x1000>, >> + <0 0x1000b000 0 0x1000>; >> + reg-names = "gpio", "iocfg_rm", >> + "iocfg_br", "iocfg_lm", >> + "iocfg_lb", "iocfg_rt", >> + "iocfg_lt", "iocfg_tl", >> + "eint"; >> + gpio-controller; >> + #gpio-cells = <2>; >> + gpio-ranges = <&pio 0 0 210>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + >> + apmixed: clock-controller@1000c000 { >> + compatible = "mediatek,mt6779-apmixed", "syscon"; >> + reg = <0 0x1000c000 0 0xe00>; >> + #clock-cells = <1>; >> + }; >> + >> + uart0: serial@11002000 { >> + compatible = "mediatek,mt6779-uart", >> + "mediatek,mt6577-uart"; >> + reg = <0 0x11002000 0 0x400>; >> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; >> + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>; >> + clock-names = "baud", "bus"; >> + status = "disabled"; >> + }; >> + >> + uart1: serial@11003000 { >> + compatible = "mediatek,mt6779-uart", >> + "mediatek,mt6577-uart"; >> + reg = <0 0x11003000 0 0x400>; >> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>; >> + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>; >> + clock-names = "baud", "bus"; >> + status = "disabled"; >> + }; >> + >> + uart2: serial@11004000 { >> + compatible = "mediatek,mt6779-uart", >> + "mediatek,mt6577-uart"; >> + reg = <0 0x11004000 0 0x400>; >> + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_LOW>; >> + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>; >> + clock-names = "baud", "bus"; >> + status = "disabled"; >> + }; >> + >> + audio: clock-controller@11210000 { >> + compatible = "mediatek,mt6779-audio", "syscon"; >> + reg = <0 0x11210000 0 0x1000>; >> + #clock-cells = <1>; >> + }; >> + >> + mfgcfg: clock-controller@13fbf000 { >> + compatible = "mediatek,mt6779-mfgcfg", "syscon"; >> + reg = <0 0x13fbf000 0 0x1000>; >> + #clock-cells = <1>; >> + }; >> + >> + mmsys: syscon@14000000 { >> + compatible = "mediatek,mt6779-mmsys", "syscon"; >> + reg = <0 0x14000000 0 0x1000>; >> + #clock-cells = <1>; >> + }; >> + >> + imgsys: clock-controller@15020000 { >> + compatible = "mediatek,mt6779-imgsys", "syscon"; >> + reg = <0 0x15020000 0 0x1000>; >> + #clock-cells = <1>; >> + }; >> + >> + vdecsys: clock-controller@16000000 { >> + compatible = "mediatek,mt6779-vdecsys", "syscon"; >> + reg = <0 0x16000000 0 0x1000>; >> + #clock-cells = <1>; >> + }; >> + >> + vencsys: clock-controller@17000000 { >> + compatible = "mediatek,mt6779-vencsys", "syscon"; >> + reg = <0 0x17000000 0 0x1000>; >> + #clock-cells = <1>; >> + }; >> + >> + camsys: clock-controller@1a000000 { >> + compatible = "mediatek,mt6779-camsys", "syscon"; >> + reg = <0 0x1a000000 0 0x10000>; >> + #clock-cells = <1>; >> + }; >> + >> + ipesys: clock-controller@1b000000 { >> + compatible = "mediatek,mt6779-ipesys", "syscon"; >> + reg = <0 0x1b000000 0 0x1000>; >> + #clock-cells = <1>; >> + }; >> + >> + }; >> +}; > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v10 2/3] arm64: dts: add dts nodes for MT6779 2020-07-30 13:30 ` [PATCH v10 2/3] arm64: dts: add dts nodes for MT6779 Hanks Chen 2020-08-05 2:24 ` Hanks Chen @ 2020-10-09 12:30 ` Matthias Brugger 1 sibling, 0 replies; 16+ messages in thread From: Matthias Brugger @ 2020-10-09 12:30 UTC (permalink / raw) To: Hanks Chen, Linus Walleij, Rob Herring, Michael Turquette, Stephen Boyd Cc: mtk01761, YueHaibing, Andy Teng, linux-gpio, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-clk, CC Hwang, Loda Chou On 30/07/2020 15:30, Hanks Chen wrote: > this adds initial MT6779 dts settings for board support, > including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc. > > Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/Makefile | 1 + > arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++ > arch/arm64/boot/dts/mediatek/mt6779.dtsi | 271 ++++++++++++++++++++ > 3 files changed, 303 insertions(+) > create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts > create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile > index a57af9da9f5c..4d1b0f9d8d1c 100644 > --- a/arch/arm64/boot/dts/mediatek/Makefile > +++ b/arch/arm64/boot/dts/mediatek/Makefile > @@ -1,6 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0 > dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb > diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts > new file mode 100644 > index 000000000000..164f5cbb3821 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts > @@ -0,0 +1,31 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (c) 2019 MediaTek Inc. > + * Author: Mars.C <mars.cheng@mediatek.com> > + * > + */ > + > +/dts-v1/; > +#include "mt6779.dtsi" > + > +/ { > + model = "MediaTek MT6779 EVB"; > + compatible = "mediatek,mt6779-evb", "mediatek,mt6779"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0 0x40000000 0 0x1e800000>; > + }; > + > + chosen { > + stdout-path = "serial0:921600n8"; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi > new file mode 100644 > index 000000000000..370f309d32de > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi > @@ -0,0 +1,271 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (c) 2019 MediaTek Inc. > + * Author: Mars.C <mars.cheng@mediatek.com> > + * > + */ > + > +#include <dt-bindings/clock/mt6779-clk.h> > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/pinctrl/mt6779-pinfunc.h> > + > +/ { > + compatible = "mediatek,mt6779"; > + interrupt-parent = <&sysirq>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + reg = <0x000>; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + reg = <0x100>; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + reg = <0x200>; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + reg = <0x300>; > + }; > + > + cpu4: cpu@4 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + reg = <0x400>; > + }; > + > + cpu5: cpu@5 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + reg = <0x500>; > + }; > + > + cpu6: cpu@6 { > + device_type = "cpu"; > + compatible = "arm,cortex-a75"; > + enable-method = "psci"; > + reg = <0x600>; > + }; > + > + cpu7: cpu@7 { > + device_type = "cpu"; > + compatible = "arm,cortex-a75"; > + enable-method = "psci"; > + reg = <0x700>; > + }; > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>; > + }; > + > + clk26m: oscillator@0 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <26000000>; > + clock-output-names = "clk26m"; > + }; > + > + clk32k: oscillator@1 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32768>; > + clock-output-names = "clk32k"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + ranges; > + > + gic: interrupt-controller@0c000000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <4>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + reg = <0 0x0c000000 0 0x40000>, /* GICD */ > + <0 0x0c040000 0 0x200000>; /* GICR */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; > + > + ppi-partitions { > + ppi_cluster0: interrupt-partition-0 { > + affinity = <&cpu0 &cpu1 \ > + &cpu2 &cpu3 &cpu4 &cpu5>; > + }; > + ppi_cluster1: interrupt-partition-1 { > + affinity = <&cpu6 &cpu7>; > + }; > + }; > + > + }; > + > + sysirq: intpol-controller@0c53a650 { > + compatible = "mediatek,mt6779-sysirq", > + "mediatek,mt6577-sysirq"; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupt-parent = <&gic>; > + reg = <0 0x0c53a650 0 0x50>; This looks a bit suspicious to me. Unfortunately I'm not able to find any reference in the datasheets. Anyway, patch now applied to v5.10-tmp/dts64 Thanks! Matthias > + }; > + > + topckgen: clock-controller@10000000 { > + compatible = "mediatek,mt6779-topckgen", "syscon"; > + reg = <0 0x10000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + infracfg_ao: clock-controller@10001000 { > + compatible = "mediatek,mt6779-infracfg_ao", "syscon"; > + reg = <0 0x10001000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + pio: pinctrl@10005000 { > + compatible = "mediatek,mt6779-pinctrl", "syscon"; > + reg = <0 0x10005000 0 0x1000>, > + <0 0x11c20000 0 0x1000>, > + <0 0x11d10000 0 0x1000>, > + <0 0x11e20000 0 0x1000>, > + <0 0x11e70000 0 0x1000>, > + <0 0x11ea0000 0 0x1000>, > + <0 0x11f20000 0 0x1000>, > + <0 0x11f30000 0 0x1000>, > + <0 0x1000b000 0 0x1000>; > + reg-names = "gpio", "iocfg_rm", > + "iocfg_br", "iocfg_lm", > + "iocfg_lb", "iocfg_rt", > + "iocfg_lt", "iocfg_tl", > + "eint"; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&pio 0 0 210>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + apmixed: clock-controller@1000c000 { > + compatible = "mediatek,mt6779-apmixed", "syscon"; > + reg = <0 0x1000c000 0 0xe00>; > + #clock-cells = <1>; > + }; > + > + uart0: serial@11002000 { > + compatible = "mediatek,mt6779-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11002000 0 0x400>; > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + uart1: serial@11003000 { > + compatible = "mediatek,mt6779-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11003000 0 0x400>; > + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + uart2: serial@11004000 { > + compatible = "mediatek,mt6779-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11004000 0 0x400>; > + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + audio: clock-controller@11210000 { > + compatible = "mediatek,mt6779-audio", "syscon"; > + reg = <0 0x11210000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + mfgcfg: clock-controller@13fbf000 { > + compatible = "mediatek,mt6779-mfgcfg", "syscon"; > + reg = <0 0x13fbf000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + mmsys: syscon@14000000 { > + compatible = "mediatek,mt6779-mmsys", "syscon"; > + reg = <0 0x14000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + imgsys: clock-controller@15020000 { > + compatible = "mediatek,mt6779-imgsys", "syscon"; > + reg = <0 0x15020000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vdecsys: clock-controller@16000000 { > + compatible = "mediatek,mt6779-vdecsys", "syscon"; > + reg = <0 0x16000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vencsys: clock-controller@17000000 { > + compatible = "mediatek,mt6779-vencsys", "syscon"; > + reg = <0 0x17000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + camsys: clock-controller@1a000000 { > + compatible = "mediatek,mt6779-camsys", "syscon"; > + reg = <0 0x1a000000 0 0x10000>; > + #clock-cells = <1>; > + }; > + > + ipesys: clock-controller@1b000000 { > + compatible = "mediatek,mt6779-ipesys", "syscon"; > + reg = <0 0x1b000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + }; > +}; > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v10 3/3] clk: mediatek: add UART0 clock support 2020-07-30 13:30 [PATCH v10 0/3] Add basic SoC Support for Mediatek MT6779 SoC Hanks Chen 2020-07-30 13:30 ` [PATCH v10 1/3] dt-bindings: pinctrl: add bindings for MediaTek " Hanks Chen 2020-07-30 13:30 ` [PATCH v10 2/3] arm64: dts: add dts nodes for MT6779 Hanks Chen @ 2020-07-30 13:30 ` Hanks Chen 2020-09-08 6:25 ` Hanks Chen 2020-10-08 21:45 ` Stephen Boyd 2 siblings, 2 replies; 16+ messages in thread From: Hanks Chen @ 2020-07-30 13:30 UTC (permalink / raw) To: Linus Walleij, Rob Herring, Matthias Brugger, Michael Turquette, Stephen Boyd Cc: mtk01761, YueHaibing, Andy Teng, linux-gpio, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-clk, CC Hwang, Loda Chou, Hanks Chen Add MT6779 UART0 clock support. Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support") Signed-off-by: Wendell Lin <wendell.lin@mediatek.com> Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> --- drivers/clk/mediatek/clk-mt6779.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 9766cccf5844..6e0d3a166729 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = { "pwm_sel", 19), GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21), + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", + "uart_sel", 22), GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", -- 2.18.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v10 3/3] clk: mediatek: add UART0 clock support 2020-07-30 13:30 ` [PATCH v10 3/3] clk: mediatek: add UART0 clock support Hanks Chen @ 2020-09-08 6:25 ` Hanks Chen 2020-10-03 10:06 ` Hanks Chen 2020-10-08 21:45 ` Stephen Boyd 1 sibling, 1 reply; 16+ messages in thread From: Hanks Chen @ 2020-09-08 6:25 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Matthias Brugger Cc: Linus Walleij, Rob Herring, Matthias Brugger, Michael Turquette, Stephen Boyd, mtk01761, YueHaibing, Andy Teng, linux-gpio, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-clk, CC Hwang, Loda Chou Hi all, Gentle ping on this patch. Thanks Hanks Chen On Thu, 2020-07-30 at 21:30 +0800, Hanks Chen wrote: > Add MT6779 UART0 clock support. > > Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support") > Signed-off-by: Wendell Lin <wendell.lin@mediatek.com> > Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > drivers/clk/mediatek/clk-mt6779.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c > index 9766cccf5844..6e0d3a166729 100644 > --- a/drivers/clk/mediatek/clk-mt6779.c > +++ b/drivers/clk/mediatek/clk-mt6779.c > @@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = { > "pwm_sel", 19), > GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", > "pwm_sel", 21), > + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", > + "uart_sel", 22), > GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", > "uart_sel", 23), > GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v10 3/3] clk: mediatek: add UART0 clock support 2020-09-08 6:25 ` Hanks Chen @ 2020-10-03 10:06 ` Hanks Chen 2020-10-08 2:00 ` Stephen Boyd 0 siblings, 1 reply; 16+ messages in thread From: Hanks Chen @ 2020-10-03 10:06 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd Cc: Matthias Brugger, devicetree, CC Hwang, Andy Teng, Linus Walleij, YueHaibing, linux-kernel, linux-clk, linux-gpio, Rob Herring, linux-mediatek, Loda Chou, mtk01761, linux-arm-kernel Hi Michael & Stephen, Please kindly let me know your comments about this patch. Thanks Regards, Hanks On Tue, 2020-09-08 at 14:25 +0800, Hanks Chen wrote: > Hi all, > > Gentle ping on this patch. > > Thanks > > > Hanks Chen > > > On Thu, 2020-07-30 at 21:30 +0800, Hanks Chen wrote: > > Add MT6779 UART0 clock support. > > > > Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support") > > Signed-off-by: Wendell Lin <wendell.lin@mediatek.com> > > Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> > > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > > --- > > drivers/clk/mediatek/clk-mt6779.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c > > index 9766cccf5844..6e0d3a166729 100644 > > --- a/drivers/clk/mediatek/clk-mt6779.c > > +++ b/drivers/clk/mediatek/clk-mt6779.c > > @@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = { > > "pwm_sel", 19), > > GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", > > "pwm_sel", 21), > > + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", > > + "uart_sel", 22), > > GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", > > "uart_sel", 23), > > GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v10 3/3] clk: mediatek: add UART0 clock support 2020-10-03 10:06 ` Hanks Chen @ 2020-10-08 2:00 ` Stephen Boyd 2020-10-08 2:39 ` Hanks Chen 2020-10-08 7:25 ` Matthias Brugger 0 siblings, 2 replies; 16+ messages in thread From: Stephen Boyd @ 2020-10-08 2:00 UTC (permalink / raw) To: Hanks Chen, Michael Turquette Cc: Matthias Brugger, devicetree, CC Hwang, Andy Teng, Linus Walleij, YueHaibing, linux-kernel, linux-clk, linux-gpio, Rob Herring, linux-mediatek, Loda Chou, mtk01761, linux-arm-kernel Quoting Hanks Chen (2020-10-03 03:06:47) > Hi Michael & Stephen, > > Please kindly let me know your comments about this patch. > Thanks > What's the base for this patch? I tried applying to v5.9-rc1 and it didn't work. ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v10 3/3] clk: mediatek: add UART0 clock support 2020-10-08 2:00 ` Stephen Boyd @ 2020-10-08 2:39 ` Hanks Chen 2020-10-08 21:45 ` Stephen Boyd 2020-10-08 7:25 ` Matthias Brugger 1 sibling, 1 reply; 16+ messages in thread From: Hanks Chen @ 2020-10-08 2:39 UTC (permalink / raw) To: Stephen Boyd Cc: Michael Turquette, Matthias Brugger, devicetree, CC Hwang, Andy Teng, Linus Walleij, YueHaibing, linux-kernel, linux-clk, linux-gpio, Rob Herring, linux-mediatek, Loda Chou, mtk01761, linux-arm-kernel On Wed, 2020-10-07 at 19:00 -0700, Stephen Boyd wrote: > Quoting Hanks Chen (2020-10-03 03:06:47) > > Hi Michael & Stephen, > > > > Please kindly let me know your comments about this patch. > > Thanks > > > > What's the base for this patch? I tried applying to v5.9-rc1 and it > didn't work. Sorry, what does that mean? Do you have encountered a merged conflict or run time failed? I based on kernel-5.8-rc1 to add it and it can boot to kernel shell. Thanks! Hanks Chen ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v10 3/3] clk: mediatek: add UART0 clock support 2020-10-08 2:39 ` Hanks Chen @ 2020-10-08 21:45 ` Stephen Boyd 0 siblings, 0 replies; 16+ messages in thread From: Stephen Boyd @ 2020-10-08 21:45 UTC (permalink / raw) To: Hanks Chen Cc: Michael Turquette, Matthias Brugger, devicetree, CC Hwang, Andy Teng, Linus Walleij, YueHaibing, linux-kernel, linux-clk, linux-gpio, Rob Herring, linux-mediatek, Loda Chou, mtk01761, linux-arm-kernel Quoting Hanks Chen (2020-10-07 19:39:13) > On Wed, 2020-10-07 at 19:00 -0700, Stephen Boyd wrote: > > Quoting Hanks Chen (2020-10-03 03:06:47) > > > Hi Michael & Stephen, > > > > > > Please kindly let me know your comments about this patch. > > > Thanks > > > > > > > What's the base for this patch? I tried applying to v5.9-rc1 and it > > didn't work. > > Sorry, what does that mean? > > Do you have encountered a merged conflict or run time failed? > > I based on kernel-5.8-rc1 to add it and it can boot to kernel shell. > Ah I see what it is. The email isn't actually plain text, it is base64 encoded and so git am gets confused by the CRLF line endings that are encoded in there. Any chance you can send patches in actual plain text format in the future? ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v10 3/3] clk: mediatek: add UART0 clock support 2020-10-08 2:00 ` Stephen Boyd 2020-10-08 2:39 ` Hanks Chen @ 2020-10-08 7:25 ` Matthias Brugger 1 sibling, 0 replies; 16+ messages in thread From: Matthias Brugger @ 2020-10-08 7:25 UTC (permalink / raw) To: Stephen Boyd, Hanks Chen, Michael Turquette Cc: devicetree, CC Hwang, Andy Teng, Linus Walleij, YueHaibing, linux-kernel, linux-clk, linux-gpio, Rob Herring, linux-mediatek, Loda Chou, mtk01761, linux-arm-kernel Hi Stephen, On 08/10/2020 04:00, Stephen Boyd wrote: > Quoting Hanks Chen (2020-10-03 03:06:47) >> Hi Michael & Stephen, >> >> Please kindly let me know your comments about this patch. >> Thanks >> > > What's the base for this patch? I tried applying to v5.9-rc1 and it > didn't work. > Can you please double check. The file the patch touches didn't get touched since v5.5-rc1. I tried to apply it and it didn't give me any error. I paste my way of applying patches just in case: b4.sh am -l -o /tmp -n patch -P 3 1596115816-11758-4-git-send-email-hanks.chen@mediatek.com && git am -3 -s /tmp/patch.mbx Regards, Matthias ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v10 3/3] clk: mediatek: add UART0 clock support 2020-07-30 13:30 ` [PATCH v10 3/3] clk: mediatek: add UART0 clock support Hanks Chen 2020-09-08 6:25 ` Hanks Chen @ 2020-10-08 21:45 ` Stephen Boyd 1 sibling, 0 replies; 16+ messages in thread From: Stephen Boyd @ 2020-10-08 21:45 UTC (permalink / raw) To: Hanks Chen, Linus Walleij, Matthias Brugger, Michael Turquette, Rob Herring Cc: mtk01761, YueHaibing, Andy Teng, linux-gpio, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-clk, CC Hwang, Loda Chou, Hanks Chen Quoting Hanks Chen (2020-07-30 06:30:16) > Add MT6779 UART0 clock support. > > Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support") > Signed-off-by: Wendell Lin <wendell.lin@mediatek.com> > Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- Applied to clk-next ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2020-10-09 12:30 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-07-30 13:30 [PATCH v10 0/3] Add basic SoC Support for Mediatek MT6779 SoC Hanks Chen 2020-07-30 13:30 ` [PATCH v10 1/3] dt-bindings: pinctrl: add bindings for MediaTek " Hanks Chen 2020-07-31 18:26 ` Rob Herring 2020-08-03 23:31 ` Linus Walleij 2020-07-30 13:30 ` [PATCH v10 2/3] arm64: dts: add dts nodes for MT6779 Hanks Chen 2020-08-05 2:24 ` Hanks Chen 2020-08-27 8:20 ` Matthias Brugger 2020-10-09 12:30 ` Matthias Brugger 2020-07-30 13:30 ` [PATCH v10 3/3] clk: mediatek: add UART0 clock support Hanks Chen 2020-09-08 6:25 ` Hanks Chen 2020-10-03 10:06 ` Hanks Chen 2020-10-08 2:00 ` Stephen Boyd 2020-10-08 2:39 ` Hanks Chen 2020-10-08 21:45 ` Stephen Boyd 2020-10-08 7:25 ` Matthias Brugger 2020-10-08 21:45 ` Stephen Boyd
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