From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Mark Brown <broonie@kernel.org>,
Liam Girdwood <lgirdwood@gmail.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Peter Geis <pgwipeout@gmail.com>,
Nicolas Chauvet <kwizart@gmail.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Kevin Hilman <khilman@kernel.org>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Viresh Kumar <vireshk@kernel.org>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>
Cc: devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-media@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-clk@vger.kernel.org
Subject: [PATCH v2 28/48] soc/tegra: Introduce core power domain driver
Date: Thu, 17 Dec 2020 21:06:18 +0300 [thread overview]
Message-ID: <20201217180638.22748-29-digetx@gmail.com> (raw)
In-Reply-To: <20201217180638.22748-1-digetx@gmail.com>
NVIDIA Tegra SoCs have multiple power domains, each domain corresponds
to an external SoC power rail. Core power domain covers vast majority of
hardware blocks within a Tegra SoC. The voltage of a power domain should
be set to a value which satisfies all devices within a power domain. Add
driver for the core power domain in order to manage the voltage state of
the domain. This allows us to support a system-wide DVFS on Tegra.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/soc/tegra/Kconfig | 6 ++
drivers/soc/tegra/Makefile | 1 +
drivers/soc/tegra/core-power-domain.c | 125 ++++++++++++++++++++++++++
include/soc/tegra/common.h | 6 ++
4 files changed, 138 insertions(+)
create mode 100644 drivers/soc/tegra/core-power-domain.c
diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig
index bcd61ae59ba3..fccbc168dd87 100644
--- a/drivers/soc/tegra/Kconfig
+++ b/drivers/soc/tegra/Kconfig
@@ -16,6 +16,7 @@ config ARCH_TEGRA_2x_SOC
select SOC_TEGRA_COMMON
select SOC_TEGRA_FLOWCTRL
select SOC_TEGRA_PMC
+ select SOC_TEGRA_CORE_POWER_DOMAIN
select SOC_TEGRA20_VOLTAGE_COUPLER
select TEGRA_TIMER
help
@@ -31,6 +32,7 @@ config ARCH_TEGRA_3x_SOC
select SOC_TEGRA_COMMON
select SOC_TEGRA_FLOWCTRL
select SOC_TEGRA_PMC
+ select SOC_TEGRA_CORE_POWER_DOMAIN
select SOC_TEGRA30_VOLTAGE_COUPLER
select TEGRA_TIMER
help
@@ -170,3 +172,7 @@ config SOC_TEGRA20_VOLTAGE_COUPLER
config SOC_TEGRA30_VOLTAGE_COUPLER
bool "Voltage scaling support for Tegra30 SoCs"
depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST
+
+config SOC_TEGRA_CORE_POWER_DOMAIN
+ bool
+ select PM_GENERIC_DOMAINS
diff --git a/drivers/soc/tegra/Makefile b/drivers/soc/tegra/Makefile
index 9c809c1814bd..8f1294f954b4 100644
--- a/drivers/soc/tegra/Makefile
+++ b/drivers/soc/tegra/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_SOC_TEGRA_PMC) += pmc.o
obj-$(CONFIG_SOC_TEGRA_POWERGATE_BPMP) += powergate-bpmp.o
obj-$(CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER) += regulators-tegra20.o
obj-$(CONFIG_SOC_TEGRA30_VOLTAGE_COUPLER) += regulators-tegra30.o
+obj-$(CONFIG_SOC_TEGRA_CORE_POWER_DOMAIN) += core-power-domain.o
diff --git a/drivers/soc/tegra/core-power-domain.c b/drivers/soc/tegra/core-power-domain.c
new file mode 100644
index 000000000000..7c0cec8c79fd
--- /dev/null
+++ b/drivers/soc/tegra/core-power-domain.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * NVIDIA Tegra SoC Core Power Domain Driver
+ */
+
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_opp.h>
+#include <linux/slab.h>
+
+#include <soc/tegra/common.h>
+
+static struct lock_class_key tegra_core_domain_lock_class;
+static bool tegra_core_domain_state_synced;
+
+static int tegra_genpd_set_performance_state(struct generic_pm_domain *genpd,
+ unsigned int level)
+{
+ struct dev_pm_opp *opp;
+ int err;
+
+ opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level);
+ if (IS_ERR(opp)) {
+ dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n",
+ level, opp);
+ return PTR_ERR(opp);
+ }
+
+ err = dev_pm_opp_set_voltage(&genpd->dev, opp);
+ dev_pm_opp_put(opp);
+
+ if (err) {
+ dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n",
+ level, err);
+ return err;
+ }
+
+ return 0;
+}
+
+static unsigned int
+tegra_genpd_opp_to_performance_state(struct generic_pm_domain *genpd,
+ struct dev_pm_opp *opp)
+{
+ return dev_pm_opp_get_level(opp);
+}
+
+static int tegra_core_domain_probe(struct platform_device *pdev)
+{
+ struct generic_pm_domain *genpd;
+ struct opp_table *opp_table;
+ const char *rname = "power";
+ int err;
+
+ genpd = devm_kzalloc(&pdev->dev, sizeof(*genpd), GFP_KERNEL);
+ if (!genpd)
+ return -ENOMEM;
+
+ genpd->name = pdev->dev.of_node->name;
+ genpd->set_performance_state = tegra_genpd_set_performance_state;
+ genpd->opp_to_performance_state = tegra_genpd_opp_to_performance_state;
+
+ opp_table = devm_pm_opp_set_regulators(&pdev->dev, &rname, 1);
+ if (IS_ERR(opp_table))
+ return dev_err_probe(&pdev->dev, PTR_ERR(opp_table),
+ "failed to set OPP regulator\n");
+
+ err = pm_genpd_init(genpd, NULL, false);
+ if (err) {
+ dev_err(&pdev->dev, "failed to init genpd: %d\n", err);
+ return err;
+ }
+
+ /*
+ * We have a "PMC -> Core" hierarchy of the power domains where
+ * PMC needs to resume and change performance (voltage) of the
+ * Core domain from the PMC GENPD on/off callbacks, hence we need
+ * to annotate the lock in order to remove confusion from the
+ * lockdep checker when a nested access happens.
+ */
+ lockdep_set_class(&genpd->mlock, &tegra_core_domain_lock_class);
+
+ err = of_genpd_add_provider_simple(pdev->dev.of_node, genpd);
+ if (err) {
+ dev_err(&pdev->dev, "failed to add genpd: %d\n", err);
+ goto remove_genpd;
+ }
+
+ return 0;
+
+remove_genpd:
+ pm_genpd_remove(genpd);
+
+ return err;
+}
+
+bool tegra_soc_core_domain_state_synced(void)
+{
+ return tegra_core_domain_state_synced;
+}
+
+static void tegra_core_domain_sync_state(struct device *dev)
+{
+ tegra_core_domain_state_synced = true;
+
+ dev_pm_opp_sync_regulators(dev);
+}
+
+static const struct of_device_id tegra_core_domain_match[] = {
+ { .compatible = "nvidia,tegra20-core-domain", },
+ { .compatible = "nvidia,tegra30-core-domain", },
+ { }
+};
+
+static struct platform_driver tegra_core_domain_driver = {
+ .driver = {
+ .name = "tegra-core-power",
+ .of_match_table = tegra_core_domain_match,
+ .suppress_bind_attrs = true,
+ .sync_state = tegra_core_domain_sync_state,
+ },
+ .probe = tegra_core_domain_probe,
+};
+builtin_platform_driver(tegra_core_domain_driver);
diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h
index 57b56793a9e5..6c2ccbbbf073 100644
--- a/include/soc/tegra/common.h
+++ b/include/soc/tegra/common.h
@@ -27,6 +27,7 @@ struct tegra_core_opp_params {
#ifdef CONFIG_ARCH_TEGRA
bool soc_is_tegra(void);
+bool tegra_soc_core_domain_state_synced(void);
int devm_tegra_core_dev_init_opp_table(struct device *dev,
struct tegra_core_opp_params *cfg);
#else
@@ -35,6 +36,11 @@ static inline bool soc_is_tegra(void)
return false;
}
+static inline bool tegra_soc_core_domain_state_synced(void)
+{
+ return false;
+}
+
static inline int
devm_tegra_core_dev_init_opp_table(struct device *dev,
struct tegra_core_opp_params *cfg)
--
2.29.2
next prev parent reply other threads:[~2020-12-17 18:12 UTC|newest]
Thread overview: 121+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-17 18:05 [PATCH v2 00/48] Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs Dmitry Osipenko
2020-12-17 18:05 ` [PATCH v2 01/48] dt-bindings: memory: tegra20: emc: Replace core regulator with power domain Dmitry Osipenko
2020-12-21 22:53 ` Rob Herring
2020-12-17 18:05 ` [PATCH v2 02/48] dt-bindings: memory: tegra30: " Dmitry Osipenko
2020-12-21 22:54 ` Rob Herring
2020-12-22 19:16 ` Dmitry Osipenko
2020-12-17 18:05 ` [PATCH v2 03/48] dt-bindings: memory: tegra124: " Dmitry Osipenko
2020-12-17 18:05 ` [PATCH v2 04/48] dt-bindings: host1x: Document OPP and power domain properties Dmitry Osipenko
2020-12-22 0:09 ` Rob Herring
2020-12-17 18:05 ` [PATCH v2 05/48] media: dt: bindings: tegra-vde: " Dmitry Osipenko
2020-12-22 0:09 ` Rob Herring
2020-12-17 18:05 ` [PATCH v2 06/48] dt-bindings: clock: tegra: Document clocks sub-node Dmitry Osipenko
2020-12-22 0:14 ` Rob Herring
2020-12-22 19:16 ` Dmitry Osipenko
2020-12-17 18:05 ` [PATCH v2 07/48] dt-bindings: arm: tegra: Add binding for core power domain Dmitry Osipenko
2020-12-19 10:57 ` Krzysztof Kozlowski
2020-12-20 18:26 ` Dmitry Osipenko
2020-12-17 18:05 ` [PATCH v2 08/48] regulator: Make regulator_sync_voltage() usable by coupled regulators Dmitry Osipenko
2020-12-17 18:05 ` [PATCH v2 09/48] opp: Add dev_pm_opp_sync_regulators() Dmitry Osipenko
2020-12-22 6:41 ` Viresh Kumar
2020-12-17 18:06 ` [PATCH v2 10/48] opp: Add dev_pm_opp_set_voltage() Dmitry Osipenko
2020-12-22 6:41 ` Viresh Kumar
2020-12-17 18:06 ` [PATCH v2 11/48] opp: Add dev_pm_opp_find_level_ceil() Dmitry Osipenko
2020-12-22 6:42 ` Viresh Kumar
2020-12-22 19:15 ` Dmitry Osipenko
2020-12-23 4:19 ` Viresh Kumar
2020-12-23 20:37 ` Dmitry Osipenko
2020-12-24 6:43 ` Viresh Kumar
2020-12-24 13:00 ` Dmitry Osipenko
2020-12-28 6:22 ` Viresh Kumar
2020-12-28 14:03 ` Dmitry Osipenko
2020-12-30 4:46 ` Viresh Kumar
2020-12-30 14:02 ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 12/48] opp: Add dev_pm_opp_get_required_pstate() Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 13/48] opp: Add resource-managed versions of OPP API functions Dmitry Osipenko
2020-12-22 8:55 ` Viresh Kumar
2020-12-22 19:14 ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 14/48] opp: Filter out OPPs based on availability of a required-OPP Dmitry Osipenko
2020-12-22 8:59 ` Viresh Kumar
2020-12-22 19:17 ` Dmitry Osipenko
2020-12-23 4:22 ` Viresh Kumar
2020-12-23 20:48 ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 15/48] opp: Support set_opp() customization without requiring to use regulators Dmitry Osipenko
2020-12-22 9:01 ` Viresh Kumar
2020-12-22 19:18 ` Dmitry Osipenko
2020-12-23 6:01 ` Viresh Kumar
2020-12-23 20:38 ` Dmitry Osipenko
2020-12-24 4:10 ` Viresh Kumar
2020-12-24 12:16 ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 16/48] opp: Handle missing OPP table in dev_pm_opp_xlate_performance_state() Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 17/48] opp: Correct debug message in _opp_add_static_v2() Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 18/48] opp: Print OPP level in debug message of _opp_add_static_v2() Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 19/48] opp: Fix adding OPP entries in a wrong order if rate is unavailable Dmitry Osipenko
2020-12-22 9:12 ` Viresh Kumar
2020-12-22 19:19 ` Dmitry Osipenko
2020-12-23 4:34 ` Viresh Kumar
2020-12-23 20:36 ` Dmitry Osipenko
2020-12-24 6:28 ` Viresh Kumar
2020-12-24 12:14 ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 20/48] PM: domains: Make set_performance_state() callback optional Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 21/48] PM: domains: Add "performance" column to debug summary Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 22/48] soc/tegra: pmc: Fix imbalanced clock disabling in error code path Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 23/48] soc/tegra: pmc: Pulse resets after removing power clamp Dmitry Osipenko
2020-12-30 14:56 ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 24/48] soc/tegra: pmc: Ensure that clock rates aren't too high Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 25/48] soc/tegra: pmc: Print out domain name when reset fails to acquire Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 26/48] soc/tegra: Add devm_tegra_core_dev_init_opp_table() Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 27/48] soc/tegra: Add CONFIG_SOC_TEGRA_COMMON and select PM_OPP by default Dmitry Osipenko
2020-12-17 18:06 ` Dmitry Osipenko [this message]
2020-12-22 6:40 ` [PATCH v2 28/48] soc/tegra: Introduce core power domain driver Viresh Kumar
2020-12-22 19:21 ` Dmitry Osipenko
2020-12-22 19:39 ` Dmitry Osipenko
2020-12-23 5:57 ` Viresh Kumar
2020-12-23 20:37 ` Dmitry Osipenko
2020-12-23 20:59 ` Dmitry Osipenko
2020-12-24 6:51 ` Viresh Kumar
2020-12-24 12:14 ` Dmitry Osipenko
2021-01-12 13:57 ` Ulf Hansson
2020-12-17 18:06 ` [PATCH v2 29/48] soc/tegra: pmc: Link domains to the parent Core domain Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 30/48] soc/tegra: regulators: Fix locking up when voltage-spread is out of range Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 31/48] soc/tegra: regulators: Support Core domain state syncing Dmitry Osipenko
2021-01-12 13:57 ` Ulf Hansson
2020-12-17 18:06 ` [PATCH v2 32/48] clk: tegra: Support runtime PM, power domain and OPP Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 33/48] gpu: host1x: Add host1x_channel_stop() Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 34/48] gpu: host1x: Support power management Dmitry Osipenko
2020-12-17 18:21 ` Mikko Perttunen
2020-12-17 18:45 ` Dmitry Osipenko
2020-12-17 20:58 ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 35/48] drm/tegra: dc: Support OPP and SoC core voltage scaling Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 36/48] drm/tegra: gr2d: Correct swapped device-tree compatibles Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 37/48] drm/tegra: gr2d: Support OPP and power management Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 38/48] drm/tegra: g3d: " Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 39/48] drm/tegra: vic: Stop channel before suspending Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 40/48] media: staging: tegra-vde: Support OPP and generic power domain Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 41/48] memory: tegra20-emc: Use devm_tegra_core_dev_init_opp_table() Dmitry Osipenko
2020-12-19 11:02 ` Krzysztof Kozlowski
2020-12-20 18:34 ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 42/48] memory: tegra30-emc: " Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 43/48] ARM: tegra: Add OPP tables and power domains to Tegra20 device-tree Dmitry Osipenko
2020-12-22 5:47 ` Viresh Kumar
2020-12-22 19:24 ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 44/48] ARM: tegra: Add OPP tables and power domains to Tegra30 device-tree Dmitry Osipenko
2020-12-22 9:14 ` Viresh Kumar
2020-12-22 19:25 ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 45/48] ARM: tegra: acer-a500: Enable core voltage scaling Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 46/48] ARM: tegra: ventana: " Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 47/48] ARM: tegra: ventana: Support CPU voltage scaling and thermal throttling Dmitry Osipenko
2020-12-17 18:28 ` Daniel Lezcano
2020-12-17 19:01 ` Dmitry Osipenko
2020-12-17 19:36 ` Daniel Lezcano
2020-12-17 20:28 ` Dmitry Osipenko
2020-12-17 21:19 ` Daniel Lezcano
2020-12-17 21:56 ` Dmitry Osipenko
2020-12-17 18:06 ` [PATCH v2 48/48] ARM: tegra: cardhu: " Dmitry Osipenko
2020-12-17 18:28 ` Daniel Lezcano
2020-12-18 7:14 ` [PATCH v2 00/48] Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs Viresh Kumar
2020-12-18 13:51 ` Dmitry Osipenko
2020-12-22 9:15 ` Viresh Kumar
2020-12-22 19:14 ` Dmitry Osipenko
2021-01-05 17:11 ` Krzysztof Kozlowski
2021-01-07 19:39 ` Dmitry Osipenko
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