From: Guenter Roeck <linux@roeck-us.net>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: mturquette@baylibre.com, sboyd@kernel.org,
linux-clk@vger.kernel.org, narmstrong@baylibre.com,
jbrunet@baylibre.com, khilman@baylibre.com,
linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 2/3] clk: divider: Switch from .round_rate to .determine_rate by default
Date: Thu, 1 Jul 2021 13:25:40 -0700 [thread overview]
Message-ID: <20210701202540.GA1085600@roeck-us.net> (raw)
In-Reply-To: <20210627223959.188139-3-martin.blumenstingl@googlemail.com>
On Mon, Jun 28, 2021 at 12:39:58AM +0200, Martin Blumenstingl wrote:
> .determine_rate is meant to replace .round_rate. The former comes with a
> benefit which is especially relevant on 32-bit systems: since
> .determine_rate uses an "unsigned long" (compared to a "signed long"
> which is used by .round_rate) the maximum value on 32-bit systems
> increases from 2^31 (or approx. 2.14GHz) to 2^32 (or approx. 4.29GHz).
> Switch to a .determine_rate implementation by default so 32-bit systems
> can benefit from the increased maximum value as well as so we have one
> fewer user of .round_rate.
>
> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
In next-20210701:
0.000000] 8<--- cut here ---
[ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00000000
[ 0.000000] pgd = (ptrval)
[ 0.000000] [00000000] *pgd=00000000
[ 0.000000] Internal error: Oops: 80000005 [#1] SMP ARM
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.13.0-next-20210701 #1
[ 0.000000] Hardware name: Freescale i.MX6 Ultralite (Device Tree)
[ 0.000000] PC is at 0x0
[ 0.000000] LR is at clk_core_determine_round_nolock+0xb4/0xe0
[ 0.000000] pc : [<00000000>] lr : [<c07be330>] psr: a00000d3
[ 0.000000] sp : c1701e48 ip : 00000000 fp : c1f6b340
[ 0.000000] r10: c1f6b33c r9 : d082007c r8 : c1709a18
[ 0.000000] r7 : 05e69ec0 r6 : 00000000 r5 : c1701e58 r4 : c2090480
[ 0.000000] r3 : 00000000 r2 : c1701e64 r1 : 05e69ec0 r0 : c208fe80
[ 0.000000] Flags: NzCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment none
[ 0.000000] Control: 10c5387d Table: 8000406a DAC: 00000051
[ 0.000000] Register r0 information: slab kmalloc-64 start c208fe80 pointer offset 0 size 64
[ 0.000000] Register r1 information: non-paged memory
[ 0.000000] Register r2 information: non-slab/vmalloc memory
[ 0.000000] Register r3 information: NULL pointer
[ 0.000000] Register r4 information: slab kmalloc-192 start c2090480 pointer offset 0 size 192
[ 0.000000] Register r5 information: non-slab/vmalloc memory
[ 0.000000] Register r6 information: NULL pointer
[ 0.000000] Register r7 information: non-paged memory
[ 0.000000] Register r8 information: non-slab/vmalloc memory
[ 0.000000] Register r9 information: 0-page vmalloc region starting at 0xd0820000 allocated at of_iomap+0x4c/0x68
[ 0.000000] Register r10 information: non-slab/vmalloc memory
[ 0.000000] Register r11 information: non-slab/vmalloc memory
[ 0.000000] Register r12 information: NULL pointer
[ 0.000000] Process swapper/0 (pid: 0, stack limit = 0x(ptrval))
[ 0.000000] Stack: (0xc1701e48 to 0xc1702000)
[ 0.000000] 1e40: c2090480 c1700000 00000000 c07c5480 05e69ec0 00000000
[ 0.000000] 1e60: ffffffff 179a7b00 c208d500 e6ff0344 c208ff00 05e69ec0 d0820080 00000000
[ 0.000000] 1e80: 0000001c c07c55c0 c1f6b324 c2012c04 d0820080 c163c310 c1f6b340 00000000
[ 0.000000] 1ea0: 00000804 d0820074 0000001c 00000000 c186052c c109a5b0 c186052c c0caf26c
[ 0.000000] 1ec0: cbdc67ac d0820000 c2012c04 d0820060 d0820048 d0820028 cbdcc0cc d0820018
[ 0.000000] 1ee0: d0820020 d0820038 d0820030 c2012c04 c1701f1c 00000000 c2005e80 c1701f1c
[ 0.000000] 1f00: 00000004 c2005e88 cbdcc0cc cbdcc138 00000001 c162a4e4 c1700000 c1700000
[ 0.000000] 1f20: 00000000 c2005e88 c2005e88 cbdc5884 00000000 c1701fc8 c17093cc c0838f44
[ 0.000000] 1f40: c1600dd0 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 0.000000] 1f60: 00000000 00000000 00000000 00000000 00000000 e6ff0344 00000000 c1902000
[ 0.000000] 1f80: c1663a80 00000012 c1700000 c1709380 00000000 c170caa8 c14cb424 c1604d34
[ 0.000000] 1fa0: c1902000 c1600e0c ffffffff ffffffff 00000000 c1600588 00000000 c1700000
[ 0.000000] 1fc0: 00000000 c1663a80 e6fa0e44 00000000 00000000 c1600330 00000051 10c0387d
[ 0.000000] 1fe0: ffffffff 8833b000 410fc075 10c5387d 00000000 00000000 00000000 00000000
[ 0.000000] [<c07be330>] (clk_core_determine_round_nolock) from [<c07c5480>] (clk_core_set_rate_nolock+0x184/0x294)
[ 0.000000] [<c07c5480>] (clk_core_set_rate_nolock) from [<c07c55c0>] (clk_set_rate+0x30/0x64)
[ 0.000000] [<c07c55c0>] (clk_set_rate) from [<c163c310>] (imx6ul_clocks_init+0x2798/0x2a44)
[ 0.000000] [<c163c310>] (imx6ul_clocks_init) from [<c162a4e4>] (of_clk_init+0x180/0x26c)
[ 0.000000] [<c162a4e4>] (of_clk_init) from [<c1604d34>] (time_init+0x20/0x30)
[ 0.000000] [<c1604d34>] (time_init) from [<c1600e0c>] (start_kernel+0x4c8/0x6cc)
[ 0.000000] [<c1600e0c>] (start_kernel) from [<00000000>] (0x0)
[ 0.000000] Code: bad PC value
[ 0.000000] ---[ end trace 7009a0f298fd39e9 ]---
[ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
Bisct points to this patch as culprit. Reverting it fixes the problem.
Guenter
next prev parent reply other threads:[~2021-07-01 20:25 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-27 22:39 [PATCH v3 0/3] clk: meson: rounding for fast clocks on 32-bit SoCs Martin Blumenstingl
2021-06-27 22:39 ` [PATCH v3 1/3] clk: divider: Add re-usable determine_rate implementations Martin Blumenstingl
2021-06-30 18:39 ` Stephen Boyd
2021-06-27 22:39 ` [PATCH v3 2/3] clk: divider: Switch from .round_rate to .determine_rate by default Martin Blumenstingl
2021-06-30 18:39 ` Stephen Boyd
2021-07-01 20:25 ` Guenter Roeck [this message]
2021-07-01 20:57 ` Martin Blumenstingl
2021-07-01 21:43 ` Guenter Roeck
2021-07-02 0:53 ` Stephen Boyd
2021-07-02 1:02 ` Stephen Boyd
2021-07-02 9:19 ` Martin Blumenstingl
[not found] ` <CGME20210702124612eucas1p1762911deb37e4fb03adc9239bb715135@eucas1p1.samsung.com>
2021-07-02 12:46 ` Marek Szyprowski
2021-07-02 21:00 ` Stephen Boyd
2021-07-02 20:59 ` Stephen Boyd
2021-07-02 22:57 ` Martin Blumenstingl
2021-07-02 1:04 ` Stephen Boyd
2021-06-27 22:39 ` [PATCH v3 3/3] clk: meson: regmap: switch to determine_rate for the dividers Martin Blumenstingl
2021-06-30 18:39 ` Stephen Boyd
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