From: Rob Herring <robh@kernel.org>
To: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
punit1.agrawal@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 3/4] dt-bindings: clock: Add DT bindings for SMU of Toshiba Visconti TMPV770x SoC
Date: Wed, 14 Jul 2021 13:24:47 -0600 [thread overview]
Message-ID: <20210714192447.GA3059664@robh.at.kernel.org> (raw)
In-Reply-To: <20210624034337.282386-4-nobuhiro1.iwamatsu@toshiba.co.jp>
On Thu, Jun 24, 2021 at 12:43:36PM +0900, Nobuhiro Iwamatsu wrote:
> Add device tree bindings for SMU (System Management Unit) controller of
> Toshiba Visconti TMPV770x SoC series.
>
> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
> ---
> .../clock/toshiba,tmpv770x-pismu.yaml | 50 +++++++++++++++++++
> 1 file changed, 50 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml
> new file mode 100644
> index 000000000000..18fdf4f2831b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml
> @@ -0,0 +1,50 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pismu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Toshiba Visconti5 TMPV770x SMU controller Device Tree Bindings
> +
> +maintainers:
> + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
> +
> +description:
> + Toshia Visconti5 SMU (System Management Unit) which supports the clock
> + and resets on TMPV770x.
> +
> +properties:
> + compatible:
> + const: toshiba,tmpv7708-pismu
> +
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> + '#reset-cells':
> + const: 1
Is there a connection to the PLLs? What are the clock inputs?
> +
> +required:
> + - compatible
> + - reg
> + - "#clock-cells"
> + - "#reset-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + pismu: pismu@24200000 {
clock-controller@...
> + compatible = "toshiba,tmpv7708-pismu";
> + reg = <0 0x24200000 0 0x2140>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> + };
> +...
> --
> 2.32.0
>
>
next prev parent reply other threads:[~2021-07-14 19:24 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-24 3:43 [PATCH v3 0/4] clk: visconti: Add support common clock driver and reset driver Nobuhiro Iwamatsu
2021-06-24 3:43 ` [PATCH v3 1/4] " Nobuhiro Iwamatsu
2021-07-14 19:21 ` Rob Herring
2021-07-20 1:39 ` Nobuhiro Iwamatsu
2021-06-24 3:43 ` [PATCH v3 2/4] dt-bindings: clock: Add DT bindings for PLL of Toshiba Visconti TMPV770x SoC Nobuhiro Iwamatsu
2021-07-14 19:23 ` Rob Herring
2021-07-20 1:40 ` Nobuhiro Iwamatsu
2021-06-24 3:43 ` [PATCH v3 3/4] dt-bindings: clock: Add DT bindings for SMU " Nobuhiro Iwamatsu
2021-07-14 19:24 ` Rob Herring [this message]
2021-07-20 1:53 ` Nobuhiro Iwamatsu
2021-06-24 3:43 ` [PATCH v3 4/4] MAINTAINERS: Add entries for Toshiba Visconti PLL and clock controller Nobuhiro Iwamatsu
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