[PATCH v4 0/4] Add GbEthernet Clock support

[Biju Das <biju.das.jz@bp.renesas.com>]

This patch series aims to add GbEthernet clock support.
GbEthernet clock support involves handing mux clock support
for HP clock and coupled clock for axi/chi module clocks which
shares same bit for controlling the clock output.

This patch series depend upon [1]
[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20210922112405.26413-2-biju.das.jz@bp.renesas.com/

v3->v4:
 * Renamed PLL5_2_DIV12 and PLL6_2_DIV2 to PLL5_250 and PLL6_250.
 * Added locking, in case both clocks are changed concurrently
 * initialized mstp_clock.enabled to match the current hardware state.
v2->v3:
 * Rebased to latest renesas-clk
 * Updated commit header for all patches
 * Replaced CLK_PLL5_2 with PLL5_FOUT3
 * Removed CLK_PLL6_2 and pll6_2 as the clk is sourced from PLL6
 * Added enabled flag to track the status of clock, if it is coupled
   with another clock
 * Introduced siblings pointer which points to the other coupled
   clock
 * coupled clock linking is done during module clk register.
 * rzg2l_mod_clock_is_enabled function returns soft state of the
   module clocks, if it is coupled with another clock
v1->v2:
 * No change. Separated clock patches from driver patch series as per [1]
 [1]
  https://www.spinics.net/lists/linux-renesas-soc/msg59067.html
v1:-
 * New patch

Biju Das (4):
  clk: renesas: rzg2l: Add support to handle MUX clocks
  clk: renesas: r9a07g044: Add ethernet clock sources
  clk: renesas: rzg2l: Add support to handle coupled clocks
  clk: renesas: r9a07g044: Add GbEthernet clock/reset

 drivers/clk/renesas/r9a07g044-cpg.c | 29 ++++++++-
 drivers/clk/renesas/rzg2l-cpg.c     | 96 +++++++++++++++++++++++++++++
 drivers/clk/renesas/rzg2l-cpg.h     | 26 +++++++-
 3 files changed, 149 insertions(+), 2 deletions(-)

-- 
2.17.1