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From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
To: Stephen Boyd <sboyd@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Michael Turquette <mturquette@baylibre.com>
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>,
	Serge Semin <fancer.lancer@gmail.com>,
	Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
	Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	<linux-clk@vger.kernel.org>, <linux-mips@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: [PATCH RESEND v5 4/8] clk: baikal-t1: Add shared xGMAC ref/ptp clocks internal parent
Date: Fri, 24 Jun 2022 17:18:48 +0300	[thread overview]
Message-ID: <20220624141853.7417-5-Sergey.Semin@baikalelectronics.ru> (raw)
In-Reply-To: <20220624141853.7417-1-Sergey.Semin@baikalelectronics.ru>

Baikal-T1 CCU reference manual says that both xGMAC reference and xGMAC
PTP clocks are generated by two different wrappers with the same constant
divider thus each producing a 156.25 MHz signal. But for some reason both
of these clock sources are gated by a single switch-flag in the CCU
registers space - CCU_SYS_XGMAC_BASE.BIT(0). In order to make the clocks
handled independently we need to define a shared parental gate so the base
clock signal would be switched off only if both of the child-clocks are
disabled.

Note the ID is intentionally set to -2 since we are going to add a one
more internal clock identifier in the next commit.

Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver")
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>

---

Changelog v4:
- Change the ID macro name to the more descriptive CCU_SYS_XGMAC_CLK.
---
 drivers/clk/baikal-t1/ccu-div.c     | 1 +
 drivers/clk/baikal-t1/ccu-div.h     | 6 ++++++
 drivers/clk/baikal-t1/clk-ccu-div.c | 8 +++++---
 3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/baikal-t1/ccu-div.c b/drivers/clk/baikal-t1/ccu-div.c
index 4062092d67f9..bbfa3526ee10 100644
--- a/drivers/clk/baikal-t1/ccu-div.c
+++ b/drivers/clk/baikal-t1/ccu-div.c
@@ -579,6 +579,7 @@ struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *div_init)
 		goto err_free_div;
 	}
 	parent_data.fw_name = div_init->parent_name;
+	parent_data.name = div_init->parent_name;
 	hw_init.parent_data = &parent_data;
 	hw_init.num_parents = 1;
 
diff --git a/drivers/clk/baikal-t1/ccu-div.h b/drivers/clk/baikal-t1/ccu-div.h
index 795665caefbd..b6a9c8e45318 100644
--- a/drivers/clk/baikal-t1/ccu-div.h
+++ b/drivers/clk/baikal-t1/ccu-div.h
@@ -13,6 +13,12 @@
 #include <linux/bits.h>
 #include <linux/of.h>
 
+/*
+ * CCU Divider private clock IDs
+ * @CCU_SYS_XGMAC_CLK: CCU XGMAC internal clock
+ */
+#define CCU_SYS_XGMAC_CLK		-2
+
 /*
  * CCU Divider private flags
  * @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
diff --git a/drivers/clk/baikal-t1/clk-ccu-div.c b/drivers/clk/baikal-t1/clk-ccu-div.c
index ea77eec40ddd..3953ae5664be 100644
--- a/drivers/clk/baikal-t1/clk-ccu-div.c
+++ b/drivers/clk/baikal-t1/clk-ccu-div.c
@@ -204,10 +204,12 @@ static const struct ccu_div_info sys_info[] = {
 			  "eth_clk", CCU_SYS_GMAC1_BASE, 5),
 	CCU_DIV_FIXED_INFO(CCU_SYS_GMAC1_PTP_CLK, "sys_gmac1_ptp_clk",
 			   "eth_clk", 10),
-	CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
-			  "eth_clk", CCU_SYS_XGMAC_BASE, 8),
+	CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_CLK, "sys_xgmac_clk",
+			  "eth_clk", CCU_SYS_XGMAC_BASE, 1),
+	CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
+			   "sys_xgmac_clk", 8),
 	CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_PTP_CLK, "sys_xgmac_ptp_clk",
-			   "eth_clk", 8),
+			   "sys_xgmac_clk", 8),
 	CCU_DIV_GATE_INFO(CCU_SYS_USB_CLK, "sys_usb_clk",
 			  "eth_clk", CCU_SYS_USB_BASE, 10),
 	CCU_DIV_VAR_INFO(CCU_SYS_PVT_CLK, "sys_pvt_clk",
-- 
2.35.1


  parent reply	other threads:[~2022-06-24 14:36 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-24 14:18 [PATCH RESEND v5 0/8] clk/resets: baikal-t1: Add DDR/PCIe resets and xGMAC/SATA fixes Serge Semin
2022-06-24 14:18 ` [PATCH RESEND v5 1/8] reset: Fix devm bulk optional exclusive control getter Serge Semin
2022-06-26 22:35   ` Dmitry Osipenko
2022-06-27 22:20     ` Serge Semin
2022-06-29 14:02   ` Philipp Zabel
2022-06-29 15:06     ` Serge Semin
2022-06-24 14:18 ` [PATCH RESEND v5 2/8] clk: vc5: Fix 5P49V6901 outputs disabling when enabling FOD Serge Semin
2022-06-24 14:18 ` [PATCH RESEND v5 3/8] clk: baikal-t1: Fix invalid xGMAC PTP clock divider Serge Semin
2022-06-24 14:18 ` Serge Semin [this message]
2022-06-24 14:18 ` [PATCH RESEND v5 5/8] clk: baikal-t1: Add SATA internal ref clock buffer Serge Semin
2022-06-24 14:18 ` [PATCH RESEND v5 6/8] clk: baikal-t1: Move reset-controls code into a dedicated module Serge Semin
2022-06-29 15:12   ` Philipp Zabel
2022-07-05 22:07     ` Serge Semin
2022-07-06  9:16       ` Philipp Zabel
2022-07-06 22:10         ` Serge Semin
2022-07-08 19:32           ` Serge Semin
2022-06-24 14:18 ` [PATCH RESEND v5 7/8] clk: baikal-t1: Add DDR/PCIe directly controlled resets support Serge Semin
2022-06-29 15:16   ` Philipp Zabel
2022-07-05 22:11     ` Serge Semin
2022-06-24 14:18 ` [PATCH RESEND v5 8/8] clk: baikal-t1: Convert to platform device driver Serge Semin

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