[PATCH v1 0/6] arm64: dts: meson: a1: introduce several peripheral IPs

[PATCH v1 0/6] arm64: dts: meson: a1: introduce several peripheral IPs

[Dmitry Rokosov]

This patch series introduces device tree declarations for various
peripheral IPs of the A1 SoC family, including clock controllers, EFUSE,
USB, SPI Flash Controller, SDIO, and UART_AO:
    - CLK: A1 SoC has four types on the board, namely PLL, Peripherals,
      CPU, and Audio, but only Amlogic A1 PLL and Peripherals clock
      controllers are currently supported.
    - EFUSE: consists of a 4k bit One Time Programmable (OTP) memory
      divided into 32 128-bit blocks, and data is accessed using the APB
      bus through software or the Key-ladder integrated with the EFUSE
      block.
    - USB: only one USB 2.0 high-speed port is available in the A1 SoC,
      supporting both HOST and DEVICE modes for OTG.
    - SPI Flash Controller: 4-bit QPI/SPI NOR Flash or NAND FLASH
      controller.
    - SDIO: for WiFi/IEEE802.11 connection.
    - UART_AO: for Bluetooth connection.

Alexey Romanov (1):
  arm64: dts: meson: a1: enable efuse controller and setup its clk

Dmitry Rokosov (2):
  arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers
  arm64: dts: meson: a1: support USB controller in OTG mode

Jan Dakinevich (1):
  arm64: dts: meson: a1: add eMMC controller and its pins

Martin Kurbanov (1):
  arm64: dts: meson: a1: introduce SPI Flash Controller

Oleg Lyovin (1):
  arm64: dts: meson: a1: introduce UART_AO mux definitions

 arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 164 ++++++++++++++++++++++
 1 file changed, 164 insertions(+)

-- 
2.36.0

[PATCH v1 1/6] arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers

[Dmitry Rokosov]

This patch adds clkc and clkc_pll dts nodes to A1 SoC main dtsi.
The first one clk controller is responsible for all SoC peripherals
clocks excluding audio clocks. The second one clk controller is used by
A1 SoC PLLs. Actually, there are two different APB heads, so we have two
different drivers.

Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
 arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 26 +++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index eed96f262844..a24228808c9c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -6,6 +6,8 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/gpio/meson-a1-gpio.h>
+#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
+#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
 
 / {
 	compatible = "amlogic,a1";
@@ -126,6 +128,30 @@ uart_AO_B: serial@2000 {
 				status = "disabled";
 			};
 
+			clkc_periphs: clock-controller@800 {
+				compatible = "amlogic,a1-peripherals-clkc";
+				reg = <0 0x800 0 0x104>;
+				#clock-cells = <1>;
+				clocks = <&clkc_pll CLKID_FCLK_DIV2>,
+					 <&clkc_pll CLKID_FCLK_DIV3>,
+					 <&clkc_pll CLKID_FCLK_DIV5>,
+					 <&clkc_pll CLKID_FCLK_DIV7>,
+					 <&clkc_pll CLKID_HIFI_PLL>,
+					 <&xtal>;
+				clock-names = "fclk_div2", "fclk_div3",
+					      "fclk_div5", "fclk_div7",
+					      "hifi_pll", "xtal";
+			};
+
+			clkc_pll: pll-clock-controller@7c80 {
+				compatible = "amlogic,a1-pll-clkc";
+				reg = <0 0x7c80 0 0x18c>;
+				#clock-cells = <1>;
+				clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
+					 <&clkc_periphs CLKID_HIFIPLL_IN>;
+				clock-names = "fixpll_in", "hifipll_in";
+			};
+
 			gpio_intc: interrupt-controller@0440 {
 				compatible = "amlogic,meson-a1-gpio-intc",
 					     "amlogic,meson-gpio-intc";
-- 
2.36.0

[PATCH v1 2/6] arm64: dts: meson: a1: support USB controller in OTG mode

[Dmitry Rokosov]

Amlogic A1 SoC family has USB2.0 controller based on dwc2 and dwc3
heads. It supports otg/host/peripheral modes.

Signed-off-by: Yue Wang <yue.wang@amlogic.com>
Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 59 +++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index a24228808c9c..b2563c7d3842 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -8,6 +8,8 @@
 #include <dt-bindings/gpio/meson-a1-gpio.h>
 #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
 #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
+#include <dt-bindings/power/meson-a1-power.h>
+#include <dt-bindings/reset/amlogic,meson-a1-reset.h>
 
 / {
 	compatible = "amlogic,a1";
@@ -161,6 +163,17 @@ gpio_intc: interrupt-controller@0440 {
 				amlogic,channel-interrupts =
 					<49 50 51 52 53 54 55 56>;
 			};
+
+			usb2_phy1: phy@4000 {
+				compatible = "amlogic,a1-usb2-phy";
+				clocks = <&clkc_periphs CLKID_USB_PHY_IN>;
+				clock-names = "xtal";
+				reg = <0x0 0x4000 0x0 0x60>;
+				resets = <&reset RESET_USBPHY>;
+				reset-names = "phy";
+				#phy-cells = <0>;
+				power-domains = <&pwrc PWRC_USB_ID>;
+			};
 		};
 
 		gic: interrupt-controller@ff901000 {
@@ -175,6 +188,52 @@ gic: interrupt-controller@ff901000 {
 			#interrupt-cells = <3>;
 			#address-cells = <0>;
 		};
+
+		usb: usb@fe004400 {
+			status = "disabled";
+			compatible = "amlogic,meson-a1-usb-ctrl";
+			reg = <0x0 0xfe004400 0x0 0xa0>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			clocks = <&clkc_periphs CLKID_USB_CTRL>,
+				 <&clkc_periphs CLKID_USB_BUS>,
+				 <&clkc_periphs CLKID_USB_CTRL_IN>;
+			clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl";
+			resets = <&reset RESET_USBCTRL>;
+			reset-name = "usb_ctrl";
+
+			dr_mode = "otg";
+
+			phys = <&usb2_phy1>;
+			phy-names = "usb2-phy1";
+
+			dwc2: usb@ff500000 {
+				compatible = "amlogic,meson-a1-usb", "snps,dwc2";
+				reg = <0x0 0xff500000 0x0 0x40000>;
+				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb2_phy1>;
+				phy-names = "usb2-phy";
+				clocks = <&clkc_periphs CLKID_USB_PHY>;
+				clock-names = "otg";
+				dr_mode = "peripheral";
+				g-rx-fifo-size = <192>;
+				g-np-tx-fifo-size = <128>;
+				g-tx-fifo-size = <128 128 16 16 16>;
+			};
+
+			dwc3: usb@ff400000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0xff400000 0x0 0x100000>;
+				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+				dr_mode = "host";
+				snps,dis_u2_susphy_quirk;
+				snps,quirk-frame-length-adjustment = <0x20>;
+				snps,parkmode-disable-ss-quirk;
+			};
+		};
 	};
 
 	timer {
-- 
2.36.0

[PATCH v1 3/6] arm64: dts: meson: a1: enable efuse controller and setup its clk

[Dmitry Rokosov]

From: Alexey Romanov <avromanov@sberdevices.ru>

EFUSE A1 controller uses CLKID_OTP clock and PWRC_OTP_ID power domain.

Signed-off-by: Alexey Romanov <avromanov@sberdevices.ru>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
 arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index b2563c7d3842..63faccfc1134 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -44,6 +44,16 @@ l2: l2-cache0 {
 		};
 	};
 
+	efuse: efuse {
+		compatible = "amlogic,meson-gxbb-efuse";
+		clocks = <&clkc_periphs CLKID_OTP>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		secure-monitor = <&sm>;
+		power-domains = <&pwrc PWRC_OTP_ID>;
+		status = "okay";
+	};
+
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
-- 
2.36.0

[PATCH v1 4/6] arm64: dts: meson: a1: introduce SPI Flash Controller

[Dmitry Rokosov]

From: Martin Kurbanov <mmkurbanov@sberdevices.ru>

This controller can be used for spinand flash connection.

Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
 arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 63faccfc1134..0efd922ca7e1 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -199,6 +199,16 @@ gic: interrupt-controller@ff901000 {
 			#address-cells = <0>;
 		};
 
+		spifc: spi@fd000400 {
+			compatible = "amlogic,a1-spifc";
+			reg = <0x0 0xfd000400 0x0 0x290>;
+			clocks = <&clkc_periphs CLKID_SPIFC>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			power-domains = <&pwrc PWRC_SPIFC_ID>;
+			status = "disabled";
+		};
+
 		usb: usb@fe004400 {
 			status = "disabled";
 			compatible = "amlogic,meson-a1-usb-ctrl";
-- 
2.36.0

[PATCH v1 5/6] arm64: dts: meson: a1: introduce UART_AO mux definitions

[Dmitry Rokosov]

From: Oleg Lyovin <ovlevin@sberdevices.ru>

The Amlogic A1 has a UART_AO port, which can be used, for example, for
BT HCI H4 connection.

This patch adds mux definitions for it.

Signed-off-by: Oleg Lyovin <ovlevin@sberdevices.ru>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
 arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 0efd922ca7e1..3eb6aa9c00e0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -118,6 +118,22 @@ gpio: bank@400 {
 					gpio-ranges = <&periphs_pinctrl 0 0 62>;
 				};
 
+				uart_a_pins: uart_a {
+					mux {
+						groups = "uart_a_tx",
+							 "uart_a_rx";
+						function = "uart_a";
+					};
+				};
+
+				uart_a_cts_rts_pins: uart_a_cts_rts {
+					mux {
+						groups = "uart_a_cts",
+							 "uart_a_rts";
+						function = "uart_a";
+						bias-pull-down;
+					};
+				};
 			};
 
 			uart_AO: serial@1c00 {
-- 
2.36.0

[PATCH v1 6/6] arm64: dts: meson: a1: add eMMC controller and its pins

[Dmitry Rokosov]

From: Jan Dakinevich <yvdakinevich@sberdevices.ru>

The definition is inspired by a similar one for AXG SoC family.
'sdio_pins' and 'sdio_clk_gate_pins' pinctrls are supposed to be used as
"default" and "clk-gate" in board-specific device trees.

'meson-gx' driver during initialization sets clock to safe low-frequency
value (400kHz). However, both source clocks ("clkin0" and "clkin1") are
high-frequency by default, and using of eMMC's internal divider is not
enough to achieve so low values. To provide low-frequency source,
reparent "sd_emmc_sel2" clock using 'assigned-clocks' property.

Signed-off-by: Jan Dakinevich <yvdakinevich@sberdevices.ru>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
 arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 43 +++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 3eb6aa9c00e0..a25170c61462 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -134,6 +134,32 @@ mux {
 						bias-pull-down;
 					};
 				};
+
+				sdio_pins: sdio {
+					mux-0 {
+						groups = "sdcard_d0_x",
+							 "sdcard_d1_x",
+							 "sdcard_d2_x",
+							 "sdcard_d3_x",
+							 "sdcard_cmd_x";
+						function = "sdcard";
+						bias-pull-up;
+					};
+
+					mux-1 {
+						groups = "sdcard_clk_x";
+						function = "sdcard";
+						bias-disable;
+					};
+				};
+
+				sdio_clk_gate_pins: sdio_clk_gate {
+					mux {
+						groups = "sdcard_clk_x";
+						function = "sdcard";
+						bias-pull-down;
+					};
+				};
 			};
 
 			uart_AO: serial@1c00 {
@@ -200,6 +226,23 @@ usb2_phy1: phy@4000 {
 				#phy-cells = <0>;
 				power-domains = <&pwrc PWRC_USB_ID>;
 			};
+
+			sd_emmc: sd@10000 {
+				compatible = "amlogic,meson-axg-mmc";
+				reg = <0x0 0x10000 0x0 0x800>;
+				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clkc_periphs CLKID_SD_EMMC_A>,
+					 <&clkc_periphs CLKID_SD_EMMC>,
+					 <&clkc_pll CLKID_FCLK_DIV2>;
+				clock-names = "core",
+					      "clkin0",
+					      "clkin1";
+				assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_SEL2>;
+				assigned-clock-parents = <&xtal>;
+				resets = <&reset RESET_SD_EMMC_A>;
+				power-domains = <&pwrc PWRC_SD_EMMC_ID>;
+				status = "disabled";
+			};
 		};
 
 		gic: interrupt-controller@ff901000 {
-- 
2.36.0

Re: [PATCH v1 0/6] arm64: dts: meson: a1: introduce several peripheral IPs

[Dmitry Rokosov]

Hello Neil, Krzysztof, Jerome, Martin, Rob and Conor,

Would you please review this patch? The latest modifications enable CLK,
EFUSE, USB, SDIO (WiFi), and UART (BT) functionality on A1 boards.

On Wed, Jun 07, 2023 at 11:16:35PM +0300, Dmitry Rokosov wrote:
> This patch series introduces device tree declarations for various
> peripheral IPs of the A1 SoC family, including clock controllers, EFUSE,
> USB, SPI Flash Controller, SDIO, and UART_AO:
>     - CLK: A1 SoC has four types on the board, namely PLL, Peripherals,
>       CPU, and Audio, but only Amlogic A1 PLL and Peripherals clock
>       controllers are currently supported.
>     - EFUSE: consists of a 4k bit One Time Programmable (OTP) memory
>       divided into 32 128-bit blocks, and data is accessed using the APB
>       bus through software or the Key-ladder integrated with the EFUSE
>       block.
>     - USB: only one USB 2.0 high-speed port is available in the A1 SoC,
>       supporting both HOST and DEVICE modes for OTG.
>     - SPI Flash Controller: 4-bit QPI/SPI NOR Flash or NAND FLASH
>       controller.
>     - SDIO: for WiFi/IEEE802.11 connection.
>     - UART_AO: for Bluetooth connection.
> 
> Alexey Romanov (1):
>   arm64: dts: meson: a1: enable efuse controller and setup its clk
> 
> Dmitry Rokosov (2):
>   arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers
>   arm64: dts: meson: a1: support USB controller in OTG mode
> 
> Jan Dakinevich (1):
>   arm64: dts: meson: a1: add eMMC controller and its pins
> 
> Martin Kurbanov (1):
>   arm64: dts: meson: a1: introduce SPI Flash Controller
> 
> Oleg Lyovin (1):
>   arm64: dts: meson: a1: introduce UART_AO mux definitions
> 
>  arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 164 ++++++++++++++++++++++
>  1 file changed, 164 insertions(+)
> 
> -- 
> 2.36.0
> 

-- 
Thank you,
Dmitry

Re: [PATCH v1 0/6] arm64: dts: meson: a1: introduce several peripheral IPs

[Krzysztof Kozlowski]

On 23/06/2023 10:22, Dmitry Rokosov wrote:
> Hello Neil, Krzysztof, Jerome, Martin, Rob and Conor,
> 
> Would you please review this patch? The latest modifications enable CLK,
> EFUSE, USB, SDIO (WiFi), and UART (BT) functionality on A1 boards.
> 

It's not a binding...

Best regards,
Krzysztof

Re: [PATCH v1 0/6] arm64: dts: meson: a1: introduce several peripheral IPs

[Dmitry Rokosov]

Krzysztof,

On Fri, Jun 23, 2023 at 10:49:19AM +0200, Krzysztof Kozlowski wrote:
> On 23/06/2023 10:22, Dmitry Rokosov wrote:
> > Hello Neil, Krzysztof, Jerome, Martin, Rob and Conor,
> > 
> > Would you please review this patch? The latest modifications enable CLK,
> > EFUSE, USB, SDIO (WiFi), and UART (BT) functionality on A1 boards.
> > 
> 
> It's not a binding...
> 
> Best regards,
> Krzysztof
> 

Ah, I was thinking that you could also review the changes made to the
device tree board files. I apologize for any inconvenience caused by
additional notifications.

-- 
Thank you,
Dmitry

Re: [PATCH v1 3/6] arm64: dts: meson: a1: enable efuse controller and setup its clk

[Martin Blumenstingl]

On Wed, Jun 7, 2023 at 10:16 PM Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
[...]
> +       efuse: efuse {
> +               compatible = "amlogic,meson-gxbb-efuse";
> +               clocks = <&clkc_periphs CLKID_OTP>;
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               secure-monitor = <&sm>;
> +               power-domains = <&pwrc PWRC_OTP_ID>;
> +               status = "okay";
If eFuse is always enabled then we can just drop status = "okay" as
that's the default.

Re: [PATCH v1 1/6] arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers

[Martin Blumenstingl]

On Wed, Jun 7, 2023 at 10:16 PM Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
>
> This patch adds clkc and clkc_pll dts nodes to A1 SoC main dtsi.
> The first one clk controller is responsible for all SoC peripherals
> clocks excluding audio clocks. The second one clk controller is used by
> A1 SoC PLLs. Actually, there are two different APB heads, so we have two
> different drivers.
>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
>  arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 26 +++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> index eed96f262844..a24228808c9c 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> @@ -6,6 +6,8 @@
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/gpio/meson-a1-gpio.h>
> +#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
> +#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
>
>  / {
>         compatible = "amlogic,a1";
> @@ -126,6 +128,30 @@ uart_AO_B: serial@2000 {
>                                 status = "disabled";
>                         };
>
> +                       clkc_periphs: clock-controller@800 {
please keep the entries sorted - so &clkc_periphs should come after
&periphs_pinctrl

> +                               compatible = "amlogic,a1-peripherals-clkc";
> +                               reg = <0 0x800 0 0x104>;
> +                               #clock-cells = <1>;
> +                               clocks = <&clkc_pll CLKID_FCLK_DIV2>,
> +                                        <&clkc_pll CLKID_FCLK_DIV3>,
> +                                        <&clkc_pll CLKID_FCLK_DIV5>,
> +                                        <&clkc_pll CLKID_FCLK_DIV7>,
> +                                        <&clkc_pll CLKID_HIFI_PLL>,
> +                                        <&xtal>;
> +                               clock-names = "fclk_div2", "fclk_div3",
> +                                             "fclk_div5", "fclk_div7",
> +                                             "hifi_pll", "xtal";
> +                       };
[...]

>                         gpio_intc: interrupt-controller@0440 {
note to self: at some point we'll have to re-order &gpio_intc, but
that's out of scope for this patch


Best regards,
Martin

Re: [PATCH v1 4/6] arm64: dts: meson: a1: introduce SPI Flash Controller

[Martin Blumenstingl]

On Wed, Jun 7, 2023 at 10:16 PM Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
>
> From: Martin Kurbanov <mmkurbanov@sberdevices.ru>
>
> This controller can be used for spinand flash connection.
>
> Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
>  arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> index 63faccfc1134..0efd922ca7e1 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> @@ -199,6 +199,16 @@ gic: interrupt-controller@ff901000 {
>                         #address-cells = <0>;
>                 };
>
> +               spifc: spi@fd000400 {
please also sort this numerically, so it should appear before &apb

Re: [PATCH v1 5/6] arm64: dts: meson: a1: introduce UART_AO mux definitions

[Martin Blumenstingl]

On Wed, Jun 7, 2023 at 10:16 PM Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
>
> From: Oleg Lyovin <ovlevin@sberdevices.ru>
>
> The Amlogic A1 has a UART_AO port, which can be used, for example, for
> BT HCI H4 connection.
>
> This patch adds mux definitions for it.
In the past we've only taken the pinctrl definitions if we have a
board that uses them.
Neil, do we still have the same policy in place? If so this patch
should be sent with the series that adds support for your A1 board.

> Signed-off-by: Oleg Lyovin <ovlevin@sberdevices.ru>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
>  arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> index 0efd922ca7e1..3eb6aa9c00e0 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> @@ -118,6 +118,22 @@ gpio: bank@400 {
>                                         gpio-ranges = <&periphs_pinctrl 0 0 62>;
>                                 };
>
> +                               uart_a_pins: uart_a {
Only our newer .dtsi (e.g. meson-g12-common.dtsi) are following the
pattern where node names should use dashes instead of underscores.
So please use: uart_a_pins: uart-a { ...

[...]
> +                               uart_a_cts_rts_pins: uart_a_cts_rts {
similar to the comment from above:
uart_a_cts_rts_pins: uart-a-cts-rts { ...

> +                                       mux {
> +                                               groups = "uart_a_cts",
> +                                                        "uart_a_rts";
> +                                               function = "uart_a";
> +                                               bias-pull-down;
Out of curiosity: is this pull down needed on all boards or just specific ones?
It seems like all other SoCs use bias-disable for the RTS/CTS pins.


Best regards,
Martin

Re: [PATCH v1 6/6] arm64: dts: meson: a1: add eMMC controller and its pins

[Martin Blumenstingl]

On Wed, Jun 7, 2023 at 10:16 PM Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
>
> From: Jan Dakinevich <yvdakinevich@sberdevices.ru>
>
> The definition is inspired by a similar one for AXG SoC family.
> 'sdio_pins' and 'sdio_clk_gate_pins' pinctrls are supposed to be used as
> "default" and "clk-gate" in board-specific device trees.
Let's wait for Neil's response on the other patch for the question
about pin mux settings

> 'meson-gx' driver during initialization sets clock to safe low-frequency
> value (400kHz). However, both source clocks ("clkin0" and "clkin1") are
> high-frequency by default, and using of eMMC's internal divider is not
> enough to achieve so low values. To provide low-frequency source,
> reparent "sd_emmc_sel2" clock using 'assigned-clocks' property.
Even if the pinctrl part should be postponed then I think it's worth
adding &sd_emmc

Re: [PATCH v1 5/6] arm64: dts: meson: a1: introduce UART_AO mux definitions

[neil.armstrong]

Hi,

On 25/06/2023 23:07, Martin Blumenstingl wrote:
> On Wed, Jun 7, 2023 at 10:16 PM Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
>>
>> From: Oleg Lyovin <ovlevin@sberdevices.ru>
>>
>> The Amlogic A1 has a UART_AO port, which can be used, for example, for
>> BT HCI H4 connection.
>>
>> This patch adds mux definitions for it.
> In the past we've only taken the pinctrl definitions if we have a
> board that uses them.
> Neil, do we still have the same policy in place? If so this patch
> should be sent with the series that adds support for your A1 board.

Yes and no, if the work is done I'll take it, but yeah since upstream linux
hates dead code, let's only define what's necessary.

> 
>> Signed-off-by: Oleg Lyovin <ovlevin@sberdevices.ru>
>> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
>> ---
>>   arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 16 ++++++++++++++++
>>   1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> index 0efd922ca7e1..3eb6aa9c00e0 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> @@ -118,6 +118,22 @@ gpio: bank@400 {
>>                                          gpio-ranges = <&periphs_pinctrl 0 0 62>;
>>                                  };
>>
>> +                               uart_a_pins: uart_a {
> Only our newer .dtsi (e.g. meson-g12-common.dtsi) are following the
> pattern where node names should use dashes instead of underscores.
> So please use: uart_a_pins: uart-a { ...

The new scheme which should be use should be:

uart_a_pins: uart-a-pins-state {

but it wasn't enforced in the pinctrl yaml pushed by heiner, but for sure
no underscores in the node name.

> 
> [...]
>> +                               uart_a_cts_rts_pins: uart_a_cts_rts {
> similar to the comment from above:
> uart_a_cts_rts_pins: uart-a-cts-rts { ...
> 
>> +                                       mux {
>> +                                               groups = "uart_a_cts",
>> +                                                        "uart_a_rts";
>> +                                               function = "uart_a";
>> +                                               bias-pull-down;
> Out of curiosity: is this pull down needed on all boards or just specific ones?
> It seems like all other SoCs use bias-disable for the RTS/CTS pins.
> 
> 
> Best regards,
> Martin

Re: [PATCH v1 6/6] arm64: dts: meson: a1: add eMMC controller and its pins

[neil.armstrong]

Hi,

On 25/06/2023 23:11, Martin Blumenstingl wrote:
> On Wed, Jun 7, 2023 at 10:16 PM Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
>>
>> From: Jan Dakinevich <yvdakinevich@sberdevices.ru>
>>
>> The definition is inspired by a similar one for AXG SoC family.
>> 'sdio_pins' and 'sdio_clk_gate_pins' pinctrls are supposed to be used as
>> "default" and "clk-gate" in board-specific device trees.
> Let's wait for Neil's response on the other patch for the question
> about pin mux settings
> 
>> 'meson-gx' driver during initialization sets clock to safe low-frequency
>> value (400kHz). However, both source clocks ("clkin0" and "clkin1") are
>> high-frequency by default, and using of eMMC's internal divider is not
>> enough to achieve so low values. To provide low-frequency source,
>> reparent "sd_emmc_sel2" clock using 'assigned-clocks' property.
> Even if the pinctrl part should be postponed then I think it's worth
> adding &sd_emmc

Yeah it's weird to add HW definition and to not enable them,
so please enable them in the board if you add them in the DTSI.

Neil

Re: [PATCH v1 1/6] arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers

[Dmitry Rokosov]

Hello Martin,

Thank you for the review!

On Sun, Jun 25, 2023 at 11:00:06PM +0200, Martin Blumenstingl wrote:
> On Wed, Jun 7, 2023 at 10:16 PM Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
> >
> > This patch adds clkc and clkc_pll dts nodes to A1 SoC main dtsi.
> > The first one clk controller is responsible for all SoC peripherals
> > clocks excluding audio clocks. The second one clk controller is used by
> > A1 SoC PLLs. Actually, there are two different APB heads, so we have two
> > different drivers.
> >
> > Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> > ---
> >  arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 26 +++++++++++++++++++++++
> >  1 file changed, 26 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> > index eed96f262844..a24228808c9c 100644
> > --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> > +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> > @@ -6,6 +6,8 @@
> >  #include <dt-bindings/interrupt-controller/irq.h>
> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >  #include <dt-bindings/gpio/meson-a1-gpio.h>
> > +#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
> > +#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
> >
> >  / {
> >         compatible = "amlogic,a1";
> > @@ -126,6 +128,30 @@ uart_AO_B: serial@2000 {
> >                                 status = "disabled";
> >                         };
> >
> > +                       clkc_periphs: clock-controller@800 {
> please keep the entries sorted - so &clkc_periphs should come after
> &periphs_pinctrl
> 

Sure

> > +                               compatible = "amlogic,a1-peripherals-clkc";
> > +                               reg = <0 0x800 0 0x104>;
> > +                               #clock-cells = <1>;
> > +                               clocks = <&clkc_pll CLKID_FCLK_DIV2>,
> > +                                        <&clkc_pll CLKID_FCLK_DIV3>,
> > +                                        <&clkc_pll CLKID_FCLK_DIV5>,
> > +                                        <&clkc_pll CLKID_FCLK_DIV7>,
> > +                                        <&clkc_pll CLKID_HIFI_PLL>,
> > +                                        <&xtal>;
> > +                               clock-names = "fclk_div2", "fclk_div3",
> > +                                             "fclk_div5", "fclk_div7",
> > +                                             "hifi_pll", "xtal";
> > +                       };
> [...]
> 
> >                         gpio_intc: interrupt-controller@0440 {
> note to self: at some point we'll have to re-order &gpio_intc, but
> that's out of scope for this patch

I have noticed that the 'meson-a1.dtsi' file contains unsorted items. As
part of the current patch series, I can re-order them to improve the dt
structure.

-- 
Thank you,
Dmitry

Re: [PATCH v1 3/6] arm64: dts: meson: a1: enable efuse controller and setup its clk

[Dmitry Rokosov]

On Sun, Jun 25, 2023 at 10:50:37PM +0200, Martin Blumenstingl wrote:
> On Wed, Jun 7, 2023 at 10:16 PM Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
> [...]
> > +       efuse: efuse {
> > +               compatible = "amlogic,meson-gxbb-efuse";
> > +               clocks = <&clkc_periphs CLKID_OTP>;
> > +               #address-cells = <1>;
> > +               #size-cells = <1>;
> > +               secure-monitor = <&sm>;
> > +               power-domains = <&pwrc PWRC_OTP_ID>;
> > +               status = "okay";
> If eFuse is always enabled then we can just drop status = "okay" as
> that's the default.

Ahh, okay. I wasn't aware of that behavior. Thank you for pointing it
out!

-- 
Thank you,
Dmitry

Re: [PATCH v1 4/6] arm64: dts: meson: a1: introduce SPI Flash Controller

[Dmitry Rokosov]

On Sun, Jun 25, 2023 at 11:03:21PM +0200, Martin Blumenstingl wrote:
> On Wed, Jun 7, 2023 at 10:16 PM Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
> >
> > From: Martin Kurbanov <mmkurbanov@sberdevices.ru>
> >
> > This controller can be used for spinand flash connection.
> >
> > Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru>
> > Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> > ---
> >  arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> > index 63faccfc1134..0efd922ca7e1 100644
> > --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> > +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> > @@ -199,6 +199,16 @@ gic: interrupt-controller@ff901000 {
> >                         #address-cells = <0>;
> >                 };
> >
> > +               spifc: spi@fd000400 {
> please also sort this numerically, so it should appear before &apb

Sure, not a problem. If things have base addresses, all of them ought to
be sorted numerically.

-- 
Thank you,
Dmitry

Re: [PATCH v1 6/6] arm64: dts: meson: a1: add eMMC controller and its pins

[Dmitry Rokosov]

Hello Neil,

Thank you for the review!

On Mon, Jun 26, 2023 at 03:36:23PM +0200, neil.armstrong@linaro.org wrote:
> Hi,
> 
> On 25/06/2023 23:11, Martin Blumenstingl wrote:
> > On Wed, Jun 7, 2023 at 10:16 PM Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
> > > 
> > > From: Jan Dakinevich <yvdakinevich@sberdevices.ru>
> > > 
> > > The definition is inspired by a similar one for AXG SoC family.
> > > 'sdio_pins' and 'sdio_clk_gate_pins' pinctrls are supposed to be used as
> > > "default" and "clk-gate" in board-specific device trees.
> > Let's wait for Neil's response on the other patch for the question
> > about pin mux settings
> > 
> > > 'meson-gx' driver during initialization sets clock to safe low-frequency
> > > value (400kHz). However, both source clocks ("clkin0" and "clkin1") are
> > > high-frequency by default, and using of eMMC's internal divider is not
> > > enough to achieve so low values. To provide low-frequency source,
> > > reparent "sd_emmc_sel2" clock using 'assigned-clocks' property.
> > Even if the pinctrl part should be postponed then I think it's worth
> > adding &sd_emmc
> 
> Yeah it's weird to add HW definition and to not enable them,
> so please enable them in the board if you add them in the DTSI.

Unfortunately, I'm unable to provide our internal board DTS. However, I
have an AD401 reference board on hand, so it's possible to test
everything there. I'll include these changes in the next version.

-- 
Thank you,
Dmitry

Re: [PATCH v1 5/6] arm64: dts: meson: a1: introduce UART_AO mux definitions

[Dmitry Rokosov]

Martin,

On Sun, Jun 25, 2023 at 11:07:51PM +0200, Martin Blumenstingl wrote:
> On Wed, Jun 7, 2023 at 10:16 PM Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
> >
> > From: Oleg Lyovin <ovlevin@sberdevices.ru>
> >
> > The Amlogic A1 has a UART_AO port, which can be used, for example, for
> > BT HCI H4 connection.
> >
> > This patch adds mux definitions for it.
> In the past we've only taken the pinctrl definitions if we have a
> board that uses them.
> Neil, do we still have the same policy in place? If so this patch
> should be sent with the series that adds support for your A1 board.
> 
> > Signed-off-by: Oleg Lyovin <ovlevin@sberdevices.ru>
> > Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> > ---
> >  arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> > index 0efd922ca7e1..3eb6aa9c00e0 100644
> > --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> > +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> > @@ -118,6 +118,22 @@ gpio: bank@400 {
> >                                         gpio-ranges = <&periphs_pinctrl 0 0 62>;
> >                                 };
> >
> > +                               uart_a_pins: uart_a {
> Only our newer .dtsi (e.g. meson-g12-common.dtsi) are following the
> pattern where node names should use dashes instead of underscores.
> So please use: uart_a_pins: uart-a { ...
> 

Okay, no problem. I'll rename the nodes in the next patch series
version.

> [...]
> > +                               uart_a_cts_rts_pins: uart_a_cts_rts {
> similar to the comment from above:
> uart_a_cts_rts_pins: uart-a-cts-rts { ...
> 

Ok

> > +                                       mux {
> > +                                               groups = "uart_a_cts",
> > +                                                        "uart_a_rts";
> > +                                               function = "uart_a";
> > +                                               bias-pull-down;
> Out of curiosity: is this pull down needed on all boards or just specific ones?
> It seems like all other SoCs use bias-disable for the RTS/CTS pins.
> 

That's a good question. The Amlogic custom kernel DTSI declares
bias-pull-down for CTS/RTS pins in UART_A. There is no information about
this in the A1 datasheet. However, from my understanding, it is related
to the usage of the UART_A. Typically, the UART_A endpoint on A1 boards
is used for BT connections, which is why Amlogic applies bias-pull-down
in the common DTSI. If my assumption is correct, it would be better to
move the bias-pull-down node parameter to the custom board DTS. I will
investigate this further and rework it in the next version if necessary.

-- 
Thank you,
Dmitry

Re: [PATCH v1 5/6] arm64: dts: meson: a1: introduce UART_AO mux definitions

[Dmitry Rokosov]

Neil, Martin,

On Mon, Jun 26, 2023 at 03:34:38PM +0200, neil.armstrong@linaro.org wrote:
> Hi,
> 
> On 25/06/2023 23:07, Martin Blumenstingl wrote:
> > On Wed, Jun 7, 2023 at 10:16 PM Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
> > > 
> > > From: Oleg Lyovin <ovlevin@sberdevices.ru>
> > > 
> > > The Amlogic A1 has a UART_AO port, which can be used, for example, for
> > > BT HCI H4 connection.
> > > 
> > > This patch adds mux definitions for it.
> > In the past we've only taken the pinctrl definitions if we have a
> > board that uses them.
> > Neil, do we still have the same policy in place? If so this patch
> > should be sent with the series that adds support for your A1 board.
> 
> Yes and no, if the work is done I'll take it, but yeah since upstream linux
> hates dead code, let's only define what's necessary.
> 

I'll prepare the patches for ad401 reference board, and share the in the
next patch series version.

> > 
> > > Signed-off-by: Oleg Lyovin <ovlevin@sberdevices.ru>
> > > Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> > > ---
> > >   arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 16 ++++++++++++++++
> > >   1 file changed, 16 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> > > index 0efd922ca7e1..3eb6aa9c00e0 100644
> > > --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> > > +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> > > @@ -118,6 +118,22 @@ gpio: bank@400 {
> > >                                          gpio-ranges = <&periphs_pinctrl 0 0 62>;
> > >                                  };
> > > 
> > > +                               uart_a_pins: uart_a {
> > Only our newer .dtsi (e.g. meson-g12-common.dtsi) are following the
> > pattern where node names should use dashes instead of underscores.
> > So please use: uart_a_pins: uart-a { ...
> 
> The new scheme which should be use should be:
> 
> uart_a_pins: uart-a-pins-state {
> 
> but it wasn't enforced in the pinctrl yaml pushed by heiner, but for sure
> no underscores in the node name.
> 

Okay, got it

> > 
> > [...]
> > > +                               uart_a_cts_rts_pins: uart_a_cts_rts {
> > similar to the comment from above:
> > uart_a_cts_rts_pins: uart-a-cts-rts { ...
> > 
> > > +                                       mux {
> > > +                                               groups = "uart_a_cts",
> > > +                                                        "uart_a_rts";
> > > +                                               function = "uart_a";
> > > +                                               bias-pull-down;
> > Out of curiosity: is this pull down needed on all boards or just specific ones?
> > It seems like all other SoCs use bias-disable for the RTS/CTS pins.
> > 
> > 
> > Best regards,
> > Martin
> 

-- 
Thank you,
Dmitry

Re: [PATCH v1 1/6] arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers

[Martin Blumenstingl]

On Wed, Jun 28, 2023 at 4:18 PM Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
[...]
> >
> > >                         gpio_intc: interrupt-controller@0440 {
> > note to self: at some point we'll have to re-order &gpio_intc, but
> > that's out of scope for this patch
>
> I have noticed that the 'meson-a1.dtsi' file contains unsorted items. As
> part of the current patch series, I can re-order them to improve the dt
> structure.
That would be awesome!