* [PATCH V4 0/4] Add camera clock controller support for SM8550
@ 2023-06-09 11:50 Jagadeesh Kona
2023-06-09 11:50 ` [PATCH V4 1/4] dt-bindings: clock: qcom: Add SM8550 camera clock controller Jagadeesh Kona
` (5 more replies)
0 siblings, 6 replies; 21+ messages in thread
From: Jagadeesh Kona @ 2023-06-09 11:50 UTC (permalink / raw)
To: Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Vladimir Zapolskiy, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Taniya Das, Jagadeesh Kona,
Satya Priya Kakitapalli, Imran Shaik, Ajit Pandey
Add bindings, driver and devicetree node for camera clock controller on
SM8550.
Jagadeesh Kona (4):
dt-bindings: clock: qcom: Add SM8550 camera clock controller
clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550
clk: qcom: camcc-sm8550: Add support for qdss, sleep and xo clocks
arm64: dts: qcom: sm8550: Add camera clock controller
.../bindings/clock/qcom,sm8450-camcc.yaml | 8 +-
arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/camcc-sm8550.c | 3585 +++++++++++++++++
include/dt-bindings/clock/qcom,sm8550-camcc.h | 187 +
6 files changed, 3801 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/qcom/camcc-sm8550.c
create mode 100644 include/dt-bindings/clock/qcom,sm8550-camcc.h
--
2.40.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH V4 1/4] dt-bindings: clock: qcom: Add SM8550 camera clock controller
2023-06-09 11:50 [PATCH V4 0/4] Add camera clock controller support for SM8550 Jagadeesh Kona
@ 2023-06-09 11:50 ` Jagadeesh Kona
2023-06-09 11:50 ` [PATCH V4 2/4] clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550 Jagadeesh Kona
` (4 subsequent siblings)
5 siblings, 0 replies; 21+ messages in thread
From: Jagadeesh Kona @ 2023-06-09 11:50 UTC (permalink / raw)
To: Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Vladimir Zapolskiy, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Taniya Das, Jagadeesh Kona,
Satya Priya Kakitapalli, Imran Shaik, Ajit Pandey,
Krzysztof Kozlowski
Add device tree bindings for the camera clock controller on
Qualcomm SM8550 platform.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes since V3:
- No changes
Changes since V2:
- No changes
Changes since V1:
- Removed new YAML file and reused SM8450 CAMCC YAML file for SM8550
.../bindings/clock/qcom,sm8450-camcc.yaml | 8 +-
include/dt-bindings/clock/qcom,sm8550-camcc.h | 187 ++++++++++++++++++
2 files changed, 193 insertions(+), 2 deletions(-)
create mode 100644 include/dt-bindings/clock/qcom,sm8550-camcc.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
index 87ae74166807..8dbc9004202f 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
@@ -13,11 +13,15 @@ description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on SM8450.
- See also:: include/dt-bindings/clock/qcom,sm8450-camcc.h
+ See also::
+ include/dt-bindings/clock/qcom,sm8450-camcc.h
+ include/dt-bindings/clock/qcom,sm8550-camcc.h
properties:
compatible:
- const: qcom,sm8450-camcc
+ enum:
+ - qcom,sm8450-camcc
+ - qcom,sm8550-camcc
clocks:
items:
diff --git a/include/dt-bindings/clock/qcom,sm8550-camcc.h b/include/dt-bindings/clock/qcom,sm8550-camcc.h
new file mode 100644
index 000000000000..a2a256691c2b
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8550-camcc.h
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8550_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8550_H
+
+/* CAM_CC clocks */
+#define CAM_CC_BPS_AHB_CLK 0
+#define CAM_CC_BPS_CLK 1
+#define CAM_CC_BPS_CLK_SRC 2
+#define CAM_CC_BPS_FAST_AHB_CLK 3
+#define CAM_CC_CAMNOC_AXI_CLK 4
+#define CAM_CC_CAMNOC_AXI_CLK_SRC 5
+#define CAM_CC_CAMNOC_DCD_XO_CLK 6
+#define CAM_CC_CAMNOC_XO_CLK 7
+#define CAM_CC_CCI_0_CLK 8
+#define CAM_CC_CCI_0_CLK_SRC 9
+#define CAM_CC_CCI_1_CLK 10
+#define CAM_CC_CCI_1_CLK_SRC 11
+#define CAM_CC_CCI_2_CLK 12
+#define CAM_CC_CCI_2_CLK_SRC 13
+#define CAM_CC_CORE_AHB_CLK 14
+#define CAM_CC_CPAS_AHB_CLK 15
+#define CAM_CC_CPAS_BPS_CLK 16
+#define CAM_CC_CPAS_CRE_CLK 17
+#define CAM_CC_CPAS_FAST_AHB_CLK 18
+#define CAM_CC_CPAS_IFE_0_CLK 19
+#define CAM_CC_CPAS_IFE_1_CLK 20
+#define CAM_CC_CPAS_IFE_2_CLK 21
+#define CAM_CC_CPAS_IFE_LITE_CLK 22
+#define CAM_CC_CPAS_IPE_NPS_CLK 23
+#define CAM_CC_CPAS_SBI_CLK 24
+#define CAM_CC_CPAS_SFE_0_CLK 25
+#define CAM_CC_CPAS_SFE_1_CLK 26
+#define CAM_CC_CPHY_RX_CLK_SRC 27
+#define CAM_CC_CRE_AHB_CLK 28
+#define CAM_CC_CRE_CLK 29
+#define CAM_CC_CRE_CLK_SRC 30
+#define CAM_CC_CSI0PHYTIMER_CLK 31
+#define CAM_CC_CSI0PHYTIMER_CLK_SRC 32
+#define CAM_CC_CSI1PHYTIMER_CLK 33
+#define CAM_CC_CSI1PHYTIMER_CLK_SRC 34
+#define CAM_CC_CSI2PHYTIMER_CLK 35
+#define CAM_CC_CSI2PHYTIMER_CLK_SRC 36
+#define CAM_CC_CSI3PHYTIMER_CLK 37
+#define CAM_CC_CSI3PHYTIMER_CLK_SRC 38
+#define CAM_CC_CSI4PHYTIMER_CLK 39
+#define CAM_CC_CSI4PHYTIMER_CLK_SRC 40
+#define CAM_CC_CSI5PHYTIMER_CLK 41
+#define CAM_CC_CSI5PHYTIMER_CLK_SRC 42
+#define CAM_CC_CSI6PHYTIMER_CLK 43
+#define CAM_CC_CSI6PHYTIMER_CLK_SRC 44
+#define CAM_CC_CSI7PHYTIMER_CLK 45
+#define CAM_CC_CSI7PHYTIMER_CLK_SRC 46
+#define CAM_CC_CSID_CLK 47
+#define CAM_CC_CSID_CLK_SRC 48
+#define CAM_CC_CSID_CSIPHY_RX_CLK 49
+#define CAM_CC_CSIPHY0_CLK 50
+#define CAM_CC_CSIPHY1_CLK 51
+#define CAM_CC_CSIPHY2_CLK 52
+#define CAM_CC_CSIPHY3_CLK 53
+#define CAM_CC_CSIPHY4_CLK 54
+#define CAM_CC_CSIPHY5_CLK 55
+#define CAM_CC_CSIPHY6_CLK 56
+#define CAM_CC_CSIPHY7_CLK 57
+#define CAM_CC_DRV_AHB_CLK 58
+#define CAM_CC_DRV_XO_CLK 59
+#define CAM_CC_FAST_AHB_CLK_SRC 60
+#define CAM_CC_GDSC_CLK 61
+#define CAM_CC_ICP_AHB_CLK 62
+#define CAM_CC_ICP_CLK 63
+#define CAM_CC_ICP_CLK_SRC 64
+#define CAM_CC_IFE_0_CLK 65
+#define CAM_CC_IFE_0_CLK_SRC 66
+#define CAM_CC_IFE_0_DSP_CLK 67
+#define CAM_CC_IFE_0_DSP_CLK_SRC 68
+#define CAM_CC_IFE_0_FAST_AHB_CLK 69
+#define CAM_CC_IFE_1_CLK 70
+#define CAM_CC_IFE_1_CLK_SRC 71
+#define CAM_CC_IFE_1_DSP_CLK 72
+#define CAM_CC_IFE_1_DSP_CLK_SRC 73
+#define CAM_CC_IFE_1_FAST_AHB_CLK 74
+#define CAM_CC_IFE_2_CLK 75
+#define CAM_CC_IFE_2_CLK_SRC 76
+#define CAM_CC_IFE_2_DSP_CLK 77
+#define CAM_CC_IFE_2_DSP_CLK_SRC 78
+#define CAM_CC_IFE_2_FAST_AHB_CLK 79
+#define CAM_CC_IFE_LITE_AHB_CLK 80
+#define CAM_CC_IFE_LITE_CLK 81
+#define CAM_CC_IFE_LITE_CLK_SRC 82
+#define CAM_CC_IFE_LITE_CPHY_RX_CLK 83
+#define CAM_CC_IFE_LITE_CSID_CLK 84
+#define CAM_CC_IFE_LITE_CSID_CLK_SRC 85
+#define CAM_CC_IPE_NPS_AHB_CLK 86
+#define CAM_CC_IPE_NPS_CLK 87
+#define CAM_CC_IPE_NPS_CLK_SRC 88
+#define CAM_CC_IPE_NPS_FAST_AHB_CLK 89
+#define CAM_CC_IPE_PPS_CLK 90
+#define CAM_CC_IPE_PPS_FAST_AHB_CLK 91
+#define CAM_CC_JPEG_1_CLK 92
+#define CAM_CC_JPEG_CLK 93
+#define CAM_CC_JPEG_CLK_SRC 94
+#define CAM_CC_MCLK0_CLK 95
+#define CAM_CC_MCLK0_CLK_SRC 96
+#define CAM_CC_MCLK1_CLK 97
+#define CAM_CC_MCLK1_CLK_SRC 98
+#define CAM_CC_MCLK2_CLK 99
+#define CAM_CC_MCLK2_CLK_SRC 100
+#define CAM_CC_MCLK3_CLK 101
+#define CAM_CC_MCLK3_CLK_SRC 102
+#define CAM_CC_MCLK4_CLK 103
+#define CAM_CC_MCLK4_CLK_SRC 104
+#define CAM_CC_MCLK5_CLK 105
+#define CAM_CC_MCLK5_CLK_SRC 106
+#define CAM_CC_MCLK6_CLK 107
+#define CAM_CC_MCLK6_CLK_SRC 108
+#define CAM_CC_MCLK7_CLK 109
+#define CAM_CC_MCLK7_CLK_SRC 110
+#define CAM_CC_PLL0 111
+#define CAM_CC_PLL0_OUT_EVEN 112
+#define CAM_CC_PLL0_OUT_ODD 113
+#define CAM_CC_PLL1 114
+#define CAM_CC_PLL1_OUT_EVEN 115
+#define CAM_CC_PLL2 116
+#define CAM_CC_PLL3 117
+#define CAM_CC_PLL3_OUT_EVEN 118
+#define CAM_CC_PLL4 119
+#define CAM_CC_PLL4_OUT_EVEN 120
+#define CAM_CC_PLL5 121
+#define CAM_CC_PLL5_OUT_EVEN 122
+#define CAM_CC_PLL6 123
+#define CAM_CC_PLL6_OUT_EVEN 124
+#define CAM_CC_PLL7 125
+#define CAM_CC_PLL7_OUT_EVEN 126
+#define CAM_CC_PLL8 127
+#define CAM_CC_PLL8_OUT_EVEN 128
+#define CAM_CC_PLL9 129
+#define CAM_CC_PLL9_OUT_EVEN 130
+#define CAM_CC_PLL10 131
+#define CAM_CC_PLL10_OUT_EVEN 132
+#define CAM_CC_PLL11 133
+#define CAM_CC_PLL11_OUT_EVEN 134
+#define CAM_CC_PLL12 135
+#define CAM_CC_PLL12_OUT_EVEN 136
+#define CAM_CC_QDSS_DEBUG_CLK 137
+#define CAM_CC_QDSS_DEBUG_CLK_SRC 138
+#define CAM_CC_QDSS_DEBUG_XO_CLK 139
+#define CAM_CC_SBI_CLK 140
+#define CAM_CC_SBI_FAST_AHB_CLK 141
+#define CAM_CC_SFE_0_CLK 142
+#define CAM_CC_SFE_0_CLK_SRC 143
+#define CAM_CC_SFE_0_FAST_AHB_CLK 144
+#define CAM_CC_SFE_1_CLK 145
+#define CAM_CC_SFE_1_CLK_SRC 146
+#define CAM_CC_SFE_1_FAST_AHB_CLK 147
+#define CAM_CC_SLEEP_CLK 148
+#define CAM_CC_SLEEP_CLK_SRC 149
+#define CAM_CC_SLOW_AHB_CLK_SRC 150
+#define CAM_CC_XO_CLK_SRC 151
+
+/* CAM_CC power domains */
+#define CAM_CC_BPS_GDSC 0
+#define CAM_CC_IFE_0_GDSC 1
+#define CAM_CC_IFE_1_GDSC 2
+#define CAM_CC_IFE_2_GDSC 3
+#define CAM_CC_IPE_0_GDSC 4
+#define CAM_CC_SBI_GDSC 5
+#define CAM_CC_SFE_0_GDSC 6
+#define CAM_CC_SFE_1_GDSC 7
+#define CAM_CC_TITAN_TOP_GDSC 8
+
+/* CAM_CC resets */
+#define CAM_CC_BPS_BCR 0
+#define CAM_CC_DRV_BCR 1
+#define CAM_CC_ICP_BCR 2
+#define CAM_CC_IFE_0_BCR 3
+#define CAM_CC_IFE_1_BCR 4
+#define CAM_CC_IFE_2_BCR 5
+#define CAM_CC_IPE_0_BCR 6
+#define CAM_CC_QDSS_DEBUG_BCR 7
+#define CAM_CC_SBI_BCR 8
+#define CAM_CC_SFE_0_BCR 9
+#define CAM_CC_SFE_1_BCR 10
+
+#endif
--
2.40.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH V4 2/4] clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550
2023-06-09 11:50 [PATCH V4 0/4] Add camera clock controller support for SM8550 Jagadeesh Kona
2023-06-09 11:50 ` [PATCH V4 1/4] dt-bindings: clock: qcom: Add SM8550 camera clock controller Jagadeesh Kona
@ 2023-06-09 11:50 ` Jagadeesh Kona
2023-06-09 16:22 ` Dmitry Baryshkov
2023-06-09 11:50 ` [PATCH V4 3/4] clk: qcom: camcc-sm8550: Add support for qdss, sleep and xo clocks Jagadeesh Kona
` (3 subsequent siblings)
5 siblings, 1 reply; 21+ messages in thread
From: Jagadeesh Kona @ 2023-06-09 11:50 UTC (permalink / raw)
To: Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Vladimir Zapolskiy, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Taniya Das, Jagadeesh Kona,
Satya Priya Kakitapalli, Imran Shaik, Ajit Pandey
Add support for the camera clock controller for camera clients to be
able to request for camcc clocks on SM8550 platform.
Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
---
Changes since V3:
- No changes
Changes since V2:
- No changes
Changes since V1:
- Sorted the PLL names in proper order
- Updated all PLL configurations to lower case hex
- Reused evo ops instead of adding new ops for ole pll
- Moved few clocks to separate patch to fix patch too long error
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/camcc-sm8550.c | 3405 +++++++++++++++++++++++++++++++
3 files changed, 3413 insertions(+)
create mode 100644 drivers/clk/qcom/camcc-sm8550.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 9cd1f05d436b..85efed78dc9a 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -756,6 +756,13 @@ config SM_CAMCC_8450
Support for the camera clock controller on SM8450 devices.
Say Y if you want to support camera devices and camera functionality.
+config SM_CAMCC_8550
+ tristate "SM8550 Camera Clock Controller"
+ select SM_GCC_8550
+ help
+ Support for the camera clock controller on SM8550 devices.
+ Say Y if you want to support camera devices and camera functionality.
+
config SM_DISPCC_6115
tristate "SM6115 Display Clock Controller"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 75d035150118..97c8cefc2fd0 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_SDX_GCC_75) += gcc-sdx75.o
obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
+obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o
obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c
new file mode 100644
index 000000000000..85f0c1e09b2b
--- /dev/null
+++ b/drivers/clk/qcom/camcc-sm8550.c
@@ -0,0 +1,3405 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,sm8550-camcc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "common.h"
+#include "gdsc.h"
+#include "reset.h"
+
+enum {
+ DT_IFACE,
+ DT_BI_TCXO,
+};
+
+enum {
+ P_BI_TCXO,
+ P_CAM_CC_PLL0_OUT_EVEN,
+ P_CAM_CC_PLL0_OUT_MAIN,
+ P_CAM_CC_PLL0_OUT_ODD,
+ P_CAM_CC_PLL1_OUT_EVEN,
+ P_CAM_CC_PLL2_OUT_EVEN,
+ P_CAM_CC_PLL2_OUT_MAIN,
+ P_CAM_CC_PLL3_OUT_EVEN,
+ P_CAM_CC_PLL4_OUT_EVEN,
+ P_CAM_CC_PLL5_OUT_EVEN,
+ P_CAM_CC_PLL6_OUT_EVEN,
+ P_CAM_CC_PLL7_OUT_EVEN,
+ P_CAM_CC_PLL8_OUT_EVEN,
+ P_CAM_CC_PLL9_OUT_EVEN,
+ P_CAM_CC_PLL9_OUT_ODD,
+ P_CAM_CC_PLL10_OUT_EVEN,
+ P_CAM_CC_PLL11_OUT_EVEN,
+ P_CAM_CC_PLL12_OUT_EVEN,
+};
+
+static const struct pll_vco lucid_ole_vco[] = {
+ { 249600000, 2300000000, 0 },
+};
+
+static const struct pll_vco rivian_ole_vco[] = {
+ { 777000000, 1285000000, 0 },
+};
+
+static const struct alpha_pll_config cam_cc_pll0_config = {
+ /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
+ .l = 0x4444003e,
+ .alpha = 0x8000,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00008400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll0 = {
+ .offset = 0x0,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll0",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
+ .offset = 0x0,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll0_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll0_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
+ { 0x2, 3 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
+ .offset = 0x0,
+ .post_div_shift = 14,
+ .post_div_table = post_div_table_cam_cc_pll0_out_odd,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll0_out_odd",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll1_config = {
+ /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
+ .l = 0x4444002f,
+ .alpha = 0x6555,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll1 = {
+ .offset = 0x1000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll1",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
+ .offset = 0x1000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll1_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll1_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll1.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll2_config = {
+ .l = 0x32,
+ .alpha = 0x0,
+ .config_ctl_val = 0x10000030,
+ .config_ctl_hi_val = 0x80890263,
+ .config_ctl_hi1_val = 0x00000217,
+ .user_ctl_val = 0x00000000,
+ .user_ctl_hi_val = 0x00100000,
+};
+
+static struct clk_alpha_pll cam_cc_pll2 = {
+ .offset = 0x2000,
+ .vco_table = rivian_ole_vco,
+ .num_vco = ARRAY_SIZE(rivian_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll2",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_rivian_evo_ops,
+ },
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll3_config = {
+ /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
+ .l = 0x44440030,
+ .alpha = 0x8aaa,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll3 = {
+ .offset = 0x3000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll3",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
+ .offset = 0x3000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll3_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll3_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll3.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll4_config = {
+ /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
+ .l = 0x44440030,
+ .alpha = 0x8aaa,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll4 = {
+ .offset = 0x4000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll4",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
+ .offset = 0x4000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll4_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll4_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll4.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll5_config = {
+ /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
+ .l = 0x44440030,
+ .alpha = 0x8aaa,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll5 = {
+ .offset = 0x5000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll5",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
+ .offset = 0x5000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll5_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll5_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll5.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll6_config = {
+ /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
+ .l = 0x44440030,
+ .alpha = 0x8aaa,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll6 = {
+ .offset = 0x6000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll6",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
+ .offset = 0x6000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll6_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll6_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll6.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll7_config = {
+ /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
+ .l = 0x44440030,
+ .alpha = 0x8aaa,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll7 = {
+ .offset = 0x7000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll7",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
+ .offset = 0x7000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll7_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll7_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll7.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll8_config = {
+ /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
+ .l = 0x44440014,
+ .alpha = 0xd555,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll8 = {
+ .offset = 0x8000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll8",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = {
+ .offset = 0x8000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll8_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll8_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll8.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll9_config = {
+ /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
+ .l = 0x44440032,
+ .alpha = 0x0,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll9 = {
+ .offset = 0x9000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll9",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll9_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll9_out_even = {
+ .offset = 0x9000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll9_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll9_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll9.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll10_config = {
+ /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
+ .l = 0x44440030,
+ .alpha = 0x8aaa,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll10 = {
+ .offset = 0xa000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll10",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll10_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll10_out_even = {
+ .offset = 0xa000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll10_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll10_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll10_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll10.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll11_config = {
+ /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
+ .l = 0x44440030,
+ .alpha = 0x8aaa,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll11 = {
+ .offset = 0xb000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll11",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll11_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll11_out_even = {
+ .offset = 0xb000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll11_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll11_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll11_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll11.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll12_config = {
+ /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
+ .l = 0x44440030,
+ .alpha = 0x8aaa,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll12 = {
+ .offset = 0xc000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll12",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll12_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll12_out_even = {
+ .offset = 0xc000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll12_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll12_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll12_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll12.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct parent_map cam_cc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL0_OUT_MAIN, 1 },
+ { P_CAM_CC_PLL0_OUT_EVEN, 2 },
+ { P_CAM_CC_PLL0_OUT_ODD, 3 },
+ { P_CAM_CC_PLL9_OUT_ODD, 4 },
+ { P_CAM_CC_PLL9_OUT_EVEN, 5 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_0[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll0.clkr.hw },
+ { .hw = &cam_cc_pll0_out_even.clkr.hw },
+ { .hw = &cam_cc_pll0_out_odd.clkr.hw },
+ { .hw = &cam_cc_pll9.clkr.hw },
+ { .hw = &cam_cc_pll9_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL2_OUT_EVEN, 3 },
+ { P_CAM_CC_PLL2_OUT_MAIN, 5 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_1[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll2.clkr.hw },
+ { .hw = &cam_cc_pll2.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_2[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL8_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_2[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll8_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_3[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL3_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_3[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll3_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_4[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL10_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_4[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll10_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_5[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL4_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_5[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll4_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_6[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL11_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_6[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll11_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_7[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL5_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_7[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll5_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_8[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL12_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_8[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll12_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_9[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL1_OUT_EVEN, 4 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_9[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll1_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_10[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL6_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_10[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll6_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_11[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL7_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_11[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll7_out_even.clkr.hw },
+};
+
+static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(200000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
+ F(400000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
+ F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
+ F(785000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_bps_clk_src = {
+ .cmd_rcgr = 0x10278,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_2,
+ .freq_tbl = ftbl_cam_cc_bps_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_bps_clk_src",
+ .parent_data = cam_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
+ .cmd_rcgr = 0x13de0,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_camnoc_axi_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_cci_0_clk_src = {
+ .cmd_rcgr = 0x13900,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cci_0_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_cci_1_clk_src = {
+ .cmd_rcgr = 0x13a30,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cci_1_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_cci_2_clk_src = {
+ .cmd_rcgr = 0x13b60,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cci_2_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
+ F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
+ .cmd_rcgr = 0x11290,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cphy_rx_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = {
+ F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
+ F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
+ F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_cre_clk_src = {
+ .cmd_rcgr = 0x1353c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_cre_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cre_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
+ .cmd_rcgr = 0x15980,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi0phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
+ .cmd_rcgr = 0x15ab8,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi1phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
+ .cmd_rcgr = 0x15bec,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi2phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
+ .cmd_rcgr = 0x15d20,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi3phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_csi4phytimer_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
+ .cmd_rcgr = 0x15e54,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi4phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi4phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = {
+ .cmd_rcgr = 0x15f88,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi5phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_csi6phytimer_clk_src = {
+ .cmd_rcgr = 0x160bc,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi6phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_csi7phytimer_clk_src = {
+ .cmd_rcgr = 0x161f0,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi7phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = {
+ F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
+ F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_csid_clk_src = {
+ .cmd_rcgr = 0x13ca8,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csid_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csid_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
+ .cmd_rcgr = 0x10018,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_fast_ahb_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
+ F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
+ F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_icp_clk_src = {
+ .cmd_rcgr = 0x137c4,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_icp_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_icp_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(466000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
+ F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
+ F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
+ F(785000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_ife_0_clk_src = {
+ .cmd_rcgr = 0x11018,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_3,
+ .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_0_clk_src",
+ .parent_data = cam_cc_parent_data_3,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_ife_0_dsp_clk_src[] = {
+ F(466000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
+ F(594000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
+ F(675000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
+ F(785000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_ife_0_dsp_clk_src = {
+ .cmd_rcgr = 0x11154,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_4,
+ .freq_tbl = ftbl_cam_cc_ife_0_dsp_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_0_dsp_clk_src",
+ .parent_data = cam_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(466000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
+ F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
+ F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
+ F(785000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_ife_1_clk_src = {
+ .cmd_rcgr = 0x12018,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_5,
+ .freq_tbl = ftbl_cam_cc_ife_1_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_1_clk_src",
+ .parent_data = cam_cc_parent_data_5,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_ife_1_dsp_clk_src[] = {
+ F(466000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0),
+ F(594000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0),
+ F(675000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0),
+ F(785000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_ife_1_dsp_clk_src = {
+ .cmd_rcgr = 0x12154,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_6,
+ .freq_tbl = ftbl_cam_cc_ife_1_dsp_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_1_dsp_clk_src",
+ .parent_data = cam_cc_parent_data_6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = {
+ F(466000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
+ F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
+ F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
+ F(785000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_ife_2_clk_src = {
+ .cmd_rcgr = 0x122a8,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_7,
+ .freq_tbl = ftbl_cam_cc_ife_2_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_2_clk_src",
+ .parent_data = cam_cc_parent_data_7,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_ife_2_dsp_clk_src[] = {
+ F(466000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0),
+ F(594000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0),
+ F(675000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0),
+ F(785000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_ife_2_dsp_clk_src = {
+ .cmd_rcgr = 0x123e4,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_8,
+ .freq_tbl = ftbl_cam_cc_ife_2_dsp_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_2_dsp_clk_src",
+ .parent_data = cam_cc_parent_data_8,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_8),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
+ .cmd_rcgr = 0x13000,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csid_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_lite_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
+ .cmd_rcgr = 0x1313c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csid_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_lite_csid_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = {
+ F(455000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
+ F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
+ F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
+ F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_ipe_nps_clk_src = {
+ .cmd_rcgr = 0x103cc,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_9,
+ .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ipe_nps_clk_src",
+ .parent_data = cam_cc_parent_data_9,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_9),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
+ F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
+ F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_jpeg_clk_src = {
+ .cmd_rcgr = 0x13674,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_jpeg_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_jpeg_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4),
+ F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_mclk0_clk_src = {
+ .cmd_rcgr = 0x15000,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk0_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk1_clk_src = {
+ .cmd_rcgr = 0x15130,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk1_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk2_clk_src = {
+ .cmd_rcgr = 0x15260,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk2_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk3_clk_src = {
+ .cmd_rcgr = 0x15390,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk3_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk4_clk_src = {
+ .cmd_rcgr = 0x154c0,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk4_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk5_clk_src = {
+ .cmd_rcgr = 0x155f0,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk5_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk6_clk_src = {
+ .cmd_rcgr = 0x15720,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk6_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk7_clk_src = {
+ .cmd_rcgr = 0x15850,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk7_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = {
+ F(466000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
+ F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
+ F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
+ F(785000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_sfe_0_clk_src = {
+ .cmd_rcgr = 0x13294,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_10,
+ .freq_tbl = ftbl_cam_cc_sfe_0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sfe_0_clk_src",
+ .parent_data = cam_cc_parent_data_10,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_10),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = {
+ F(466000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
+ F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
+ F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
+ F(785000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_sfe_1_clk_src = {
+ .cmd_rcgr = 0x133f4,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_11,
+ .freq_tbl = ftbl_cam_cc_sfe_1_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sfe_1_clk_src",
+ .parent_data = cam_cc_parent_data_11,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_11),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
+ .cmd_rcgr = 0x10148,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_slow_ahb_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_branch cam_cc_bps_ahb_clk = {
+ .halt_reg = 0x10274,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x10274,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_bps_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_bps_clk = {
+ .halt_reg = 0x103a4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x103a4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_bps_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_bps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_bps_fast_ahb_clk = {
+ .halt_reg = 0x10144,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x10144,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_bps_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_camnoc_axi_clk = {
+ .halt_reg = 0x13f0c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13f0c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_camnoc_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_camnoc_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cci_0_clk = {
+ .halt_reg = 0x13a2c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13a2c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cci_0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cci_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cci_1_clk = {
+ .halt_reg = 0x13b5c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13b5c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cci_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cci_1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cci_2_clk = {
+ .halt_reg = 0x13c8c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13c8c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cci_2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cci_2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_core_ahb_clk = {
+ .halt_reg = 0x1406c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x1406c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_core_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_ahb_clk = {
+ .halt_reg = 0x13c90,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13c90,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_bps_clk = {
+ .halt_reg = 0x103b0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x103b0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_bps_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_bps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_cre_clk = {
+ .halt_reg = 0x1366c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1366c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_cre_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cre_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_fast_ahb_clk = {
+ .halt_reg = 0x13c9c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13c9c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_ife_0_clk = {
+ .halt_reg = 0x11150,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x11150,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_ife_0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_ife_1_clk = {
+ .halt_reg = 0x12150,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x12150,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_ife_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_ife_2_clk = {
+ .halt_reg = 0x123e0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x123e0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_ife_2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_ife_lite_clk = {
+ .halt_reg = 0x13138,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13138,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_ife_lite_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_lite_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_ipe_nps_clk = {
+ .halt_reg = 0x10504,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x10504,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_ipe_nps_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ipe_nps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_sbi_clk = {
+ .halt_reg = 0x1054c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1054c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_sbi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_sfe_0_clk = {
+ .halt_reg = 0x133cc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x133cc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_sfe_0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_sfe_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_sfe_1_clk = {
+ .halt_reg = 0x1352c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1352c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_sfe_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_sfe_1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cre_ahb_clk = {
+ .halt_reg = 0x13670,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13670,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cre_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cre_clk = {
+ .halt_reg = 0x13668,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13668,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cre_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cre_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi0phytimer_clk = {
+ .halt_reg = 0x15aac,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15aac,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi0phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_csi0phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi1phytimer_clk = {
+ .halt_reg = 0x15be4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15be4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi1phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_csi1phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi2phytimer_clk = {
+ .halt_reg = 0x15d18,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15d18,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi2phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_csi2phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi3phytimer_clk = {
+ .halt_reg = 0x15e4c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15e4c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi3phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_csi3phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi4phytimer_clk = {
+ .halt_reg = 0x15f80,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15f80,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi4phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_csi4phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi5phytimer_clk = {
+ .halt_reg = 0x160b4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x160b4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi5phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_csi5phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi6phytimer_clk = {
+ .halt_reg = 0x161e8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x161e8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi6phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_csi6phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi7phytimer_clk = {
+ .halt_reg = 0x1631c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1631c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi7phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_csi7phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csid_clk = {
+ .halt_reg = 0x13dd4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13dd4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csid_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_csid_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csid_csiphy_rx_clk = {
+ .halt_reg = 0x15ab4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15ab4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csid_csiphy_rx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy0_clk = {
+ .halt_reg = 0x15ab0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15ab0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csiphy0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy1_clk = {
+ .halt_reg = 0x15be8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15be8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csiphy1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy2_clk = {
+ .halt_reg = 0x15d1c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15d1c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csiphy2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy3_clk = {
+ .halt_reg = 0x15e50,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15e50,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csiphy3_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy4_clk = {
+ .halt_reg = 0x15f84,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15f84,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csiphy4_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy5_clk = {
+ .halt_reg = 0x160b8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x160b8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csiphy5_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy6_clk = {
+ .halt_reg = 0x161ec,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x161ec,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csiphy6_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy7_clk = {
+ .halt_reg = 0x16320,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x16320,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csiphy7_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_drv_ahb_clk = {
+ .halt_reg = 0x142d8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x142d8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_drv_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_icp_ahb_clk = {
+ .halt_reg = 0x138fc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x138fc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_icp_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_icp_clk = {
+ .halt_reg = 0x138f0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x138f0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_icp_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_icp_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_0_clk = {
+ .halt_reg = 0x11144,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x11144,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_0_dsp_clk = {
+ .halt_reg = 0x11280,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x11280,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_0_dsp_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_0_dsp_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_0_fast_ahb_clk = {
+ .halt_reg = 0x1128c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1128c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_0_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_1_clk = {
+ .halt_reg = 0x12144,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x12144,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_1_dsp_clk = {
+ .halt_reg = 0x12280,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x12280,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_1_dsp_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_1_dsp_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_1_fast_ahb_clk = {
+ .halt_reg = 0x1228c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1228c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_1_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_2_clk = {
+ .halt_reg = 0x123d4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x123d4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_2_dsp_clk = {
+ .halt_reg = 0x12510,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x12510,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_2_dsp_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_2_dsp_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_2_fast_ahb_clk = {
+ .halt_reg = 0x1251c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1251c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_2_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_lite_ahb_clk = {
+ .halt_reg = 0x13278,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13278,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_lite_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_lite_clk = {
+ .halt_reg = 0x1312c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1312c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_lite_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_lite_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
+ .halt_reg = 0x13274,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13274,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_lite_cphy_rx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_lite_csid_clk = {
+ .halt_reg = 0x13268,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13268,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_lite_csid_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_lite_csid_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ipe_nps_ahb_clk = {
+ .halt_reg = 0x1051c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1051c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ipe_nps_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ipe_nps_clk = {
+ .halt_reg = 0x104f8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x104f8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ipe_nps_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ipe_nps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = {
+ .halt_reg = 0x10520,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x10520,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ipe_nps_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ipe_pps_clk = {
+ .halt_reg = 0x10508,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x10508,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ipe_pps_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ipe_nps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = {
+ .halt_reg = 0x10524,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x10524,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ipe_pps_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_jpeg_1_clk = {
+ .halt_reg = 0x137ac,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x137ac,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_jpeg_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_jpeg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_jpeg_clk = {
+ .halt_reg = 0x137a0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x137a0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_jpeg_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_jpeg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk0_clk = {
+ .halt_reg = 0x1512c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1512c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_mclk0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk1_clk = {
+ .halt_reg = 0x1525c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1525c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_mclk1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk2_clk = {
+ .halt_reg = 0x1538c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1538c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_mclk2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk3_clk = {
+ .halt_reg = 0x154bc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x154bc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk3_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_mclk3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk4_clk = {
+ .halt_reg = 0x155ec,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x155ec,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk4_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_mclk4_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk5_clk = {
+ .halt_reg = 0x1571c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1571c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk5_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_mclk5_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk6_clk = {
+ .halt_reg = 0x1584c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1584c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk6_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_mclk6_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk7_clk = {
+ .halt_reg = 0x1597c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1597c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk7_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_mclk7_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sbi_clk = {
+ .halt_reg = 0x10540,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x10540,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sbi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sbi_fast_ahb_clk = {
+ .halt_reg = 0x10550,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x10550,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sbi_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sfe_0_clk = {
+ .halt_reg = 0x133c0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x133c0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sfe_0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_sfe_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = {
+ .halt_reg = 0x133d8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x133d8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sfe_0_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sfe_1_clk = {
+ .halt_reg = 0x13520,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13520,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sfe_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_sfe_1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
+ .halt_reg = 0x13538,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13538,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sfe_1_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc cam_cc_bps_gdsc = {
+ .gdscr = 0x10004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_bps_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc cam_cc_ife_0_gdsc = {
+ .gdscr = 0x11004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_ife_0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc cam_cc_ife_1_gdsc = {
+ .gdscr = 0x12004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_ife_1_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc cam_cc_ife_2_gdsc = {
+ .gdscr = 0x12294,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_ife_2_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc cam_cc_ipe_0_gdsc = {
+ .gdscr = 0x103b8,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_ipe_0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc cam_cc_sbi_gdsc = {
+ .gdscr = 0x1052c,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_sbi_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc cam_cc_sfe_0_gdsc = {
+ .gdscr = 0x13280,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_sfe_0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc cam_cc_sfe_1_gdsc = {
+ .gdscr = 0x133e0,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_sfe_1_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc cam_cc_titan_top_gdsc = {
+ .gdscr = 0x14058,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_titan_top_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct clk_regmap *cam_cc_sm8550_clocks[] = {
+ [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
+ [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
+ [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
+ [CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr,
+ [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
+ [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
+ [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
+ [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
+ [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
+ [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
+ [CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr,
+ [CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr,
+ [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
+ [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
+ [CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr,
+ [CAM_CC_CPAS_CRE_CLK] = &cam_cc_cpas_cre_clk.clkr,
+ [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr,
+ [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr,
+ [CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr,
+ [CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr,
+ [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr,
+ [CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr,
+ [CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr,
+ [CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr,
+ [CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr,
+ [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
+ [CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr,
+ [CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr,
+ [CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr,
+ [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
+ [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
+ [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
+ [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
+ [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
+ [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
+ [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
+ [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
+ [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
+ [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
+ [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr,
+ [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr,
+ [CAM_CC_CSI6PHYTIMER_CLK] = &cam_cc_csi6phytimer_clk.clkr,
+ [CAM_CC_CSI6PHYTIMER_CLK_SRC] = &cam_cc_csi6phytimer_clk_src.clkr,
+ [CAM_CC_CSI7PHYTIMER_CLK] = &cam_cc_csi7phytimer_clk.clkr,
+ [CAM_CC_CSI7PHYTIMER_CLK_SRC] = &cam_cc_csi7phytimer_clk_src.clkr,
+ [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr,
+ [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr,
+ [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr,
+ [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
+ [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
+ [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
+ [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
+ [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
+ [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
+ [CAM_CC_CSIPHY6_CLK] = &cam_cc_csiphy6_clk.clkr,
+ [CAM_CC_CSIPHY7_CLK] = &cam_cc_csiphy7_clk.clkr,
+ [CAM_CC_DRV_AHB_CLK] = &cam_cc_drv_ahb_clk.clkr,
+ [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
+ [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
+ [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
+ [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
+ [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
+ [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
+ [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
+ [CAM_CC_IFE_0_DSP_CLK_SRC] = &cam_cc_ife_0_dsp_clk_src.clkr,
+ [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr,
+ [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
+ [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
+ [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
+ [CAM_CC_IFE_1_DSP_CLK_SRC] = &cam_cc_ife_1_dsp_clk_src.clkr,
+ [CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr,
+ [CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr,
+ [CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr,
+ [CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr,
+ [CAM_CC_IFE_2_DSP_CLK_SRC] = &cam_cc_ife_2_dsp_clk_src.clkr,
+ [CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr,
+ [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
+ [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
+ [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
+ [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
+ [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
+ [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
+ [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr,
+ [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr,
+ [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr,
+ [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr,
+ [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr,
+ [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr,
+ [CAM_CC_JPEG_1_CLK] = &cam_cc_jpeg_1_clk.clkr,
+ [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
+ [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
+ [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
+ [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
+ [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
+ [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
+ [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
+ [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
+ [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
+ [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
+ [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
+ [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
+ [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
+ [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
+ [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr,
+ [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr,
+ [CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr,
+ [CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr,
+ [CAM_CC_PLL0] = &cam_cc_pll0.clkr,
+ [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
+ [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
+ [CAM_CC_PLL1] = &cam_cc_pll1.clkr,
+ [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
+ [CAM_CC_PLL2] = &cam_cc_pll2.clkr,
+ [CAM_CC_PLL3] = &cam_cc_pll3.clkr,
+ [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
+ [CAM_CC_PLL4] = &cam_cc_pll4.clkr,
+ [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
+ [CAM_CC_PLL5] = &cam_cc_pll5.clkr,
+ [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr,
+ [CAM_CC_PLL6] = &cam_cc_pll6.clkr,
+ [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr,
+ [CAM_CC_PLL7] = &cam_cc_pll7.clkr,
+ [CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr,
+ [CAM_CC_PLL8] = &cam_cc_pll8.clkr,
+ [CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr,
+ [CAM_CC_PLL9] = &cam_cc_pll9.clkr,
+ [CAM_CC_PLL9_OUT_EVEN] = &cam_cc_pll9_out_even.clkr,
+ [CAM_CC_PLL10] = &cam_cc_pll10.clkr,
+ [CAM_CC_PLL10_OUT_EVEN] = &cam_cc_pll10_out_even.clkr,
+ [CAM_CC_PLL11] = &cam_cc_pll11.clkr,
+ [CAM_CC_PLL11_OUT_EVEN] = &cam_cc_pll11_out_even.clkr,
+ [CAM_CC_PLL12] = &cam_cc_pll12.clkr,
+ [CAM_CC_PLL12_OUT_EVEN] = &cam_cc_pll12_out_even.clkr,
+ [CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr,
+ [CAM_CC_SBI_FAST_AHB_CLK] = &cam_cc_sbi_fast_ahb_clk.clkr,
+ [CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr,
+ [CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr,
+ [CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr,
+ [CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr,
+ [CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr,
+ [CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr,
+ [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
+};
+
+static struct gdsc *cam_cc_sm8550_gdscs[] = {
+ [CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc,
+ [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc,
+ [CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc,
+ [CAM_CC_IFE_2_GDSC] = &cam_cc_ife_2_gdsc,
+ [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc,
+ [CAM_CC_SBI_GDSC] = &cam_cc_sbi_gdsc,
+ [CAM_CC_SFE_0_GDSC] = &cam_cc_sfe_0_gdsc,
+ [CAM_CC_SFE_1_GDSC] = &cam_cc_sfe_1_gdsc,
+ [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc,
+};
+
+static const struct qcom_reset_map cam_cc_sm8550_resets[] = {
+ [CAM_CC_BPS_BCR] = { 0x10000 },
+ [CAM_CC_DRV_BCR] = { 0x142d0 },
+ [CAM_CC_ICP_BCR] = { 0x137c0 },
+ [CAM_CC_IFE_0_BCR] = { 0x11000 },
+ [CAM_CC_IFE_1_BCR] = { 0x12000 },
+ [CAM_CC_IFE_2_BCR] = { 0x12290 },
+ [CAM_CC_IPE_0_BCR] = { 0x103b4 },
+ [CAM_CC_QDSS_DEBUG_BCR] = { 0x13f20 },
+ [CAM_CC_SBI_BCR] = { 0x10528 },
+ [CAM_CC_SFE_0_BCR] = { 0x1327c },
+ [CAM_CC_SFE_1_BCR] = { 0x133dc },
+};
+
+static const struct regmap_config cam_cc_sm8550_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x16320,
+ .fast_io = true,
+};
+
+static struct qcom_cc_desc cam_cc_sm8550_desc = {
+ .config = &cam_cc_sm8550_regmap_config,
+ .clks = cam_cc_sm8550_clocks,
+ .num_clks = ARRAY_SIZE(cam_cc_sm8550_clocks),
+ .resets = cam_cc_sm8550_resets,
+ .num_resets = ARRAY_SIZE(cam_cc_sm8550_resets),
+ .gdscs = cam_cc_sm8550_gdscs,
+ .num_gdscs = ARRAY_SIZE(cam_cc_sm8550_gdscs),
+};
+
+static const struct of_device_id cam_cc_sm8550_match_table[] = {
+ { .compatible = "qcom,sm8550-camcc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, cam_cc_sm8550_match_table);
+
+static int cam_cc_sm8550_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ int ret;
+
+ ret = devm_pm_runtime_enable(&pdev->dev);
+ if (ret)
+ return ret;
+
+ ret = pm_runtime_resume_and_get(&pdev->dev);
+ if (ret)
+ return ret;
+
+ regmap = qcom_cc_map(pdev, &cam_cc_sm8550_desc);
+ if (IS_ERR(regmap)) {
+ pm_runtime_put(&pdev->dev);
+ return PTR_ERR(regmap);
+ }
+
+ clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
+ clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
+ clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
+ clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
+ clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
+ clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
+ clk_lucid_evo_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
+ clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
+ clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
+ clk_lucid_evo_pll_configure(&cam_cc_pll9, regmap, &cam_cc_pll9_config);
+ clk_lucid_evo_pll_configure(&cam_cc_pll10, regmap, &cam_cc_pll10_config);
+ clk_lucid_evo_pll_configure(&cam_cc_pll11, regmap, &cam_cc_pll11_config);
+ clk_lucid_evo_pll_configure(&cam_cc_pll12, regmap, &cam_cc_pll12_config);
+
+ /*
+ * Keep clocks always enabled:
+ * cam_cc_gdsc_clk
+ * cam_cc_sleep_clk
+ */
+ regmap_update_bits(regmap, 0x1419c, BIT(0), BIT(0));
+ regmap_update_bits(regmap, 0x142cc, BIT(0), BIT(0));
+
+ ret = qcom_cc_really_probe(pdev, &cam_cc_sm8550_desc, regmap);
+
+ pm_runtime_put(&pdev->dev);
+
+ return ret;
+}
+
+static struct platform_driver cam_cc_sm8550_driver = {
+ .probe = cam_cc_sm8550_probe,
+ .driver = {
+ .name = "cam_cc-sm8550",
+ .of_match_table = cam_cc_sm8550_match_table,
+ },
+};
+
+static int __init cam_cc_sm8550_init(void)
+{
+ return platform_driver_register(&cam_cc_sm8550_driver);
+}
+subsys_initcall(cam_cc_sm8550_init);
+
+static void __exit cam_cc_sm8550_exit(void)
+{
+ platform_driver_unregister(&cam_cc_sm8550_driver);
+}
+module_exit(cam_cc_sm8550_exit);
+
+MODULE_DESCRIPTION("QTI CAMCC SM8550 Driver");
+MODULE_LICENSE("GPL");
--
2.40.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH V4 3/4] clk: qcom: camcc-sm8550: Add support for qdss, sleep and xo clocks
2023-06-09 11:50 [PATCH V4 0/4] Add camera clock controller support for SM8550 Jagadeesh Kona
2023-06-09 11:50 ` [PATCH V4 1/4] dt-bindings: clock: qcom: Add SM8550 camera clock controller Jagadeesh Kona
2023-06-09 11:50 ` [PATCH V4 2/4] clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550 Jagadeesh Kona
@ 2023-06-09 11:50 ` Jagadeesh Kona
2023-06-09 11:50 ` [PATCH V4 4/4] arm64: dts: qcom: sm8550: Add camera clock controller Jagadeesh Kona
` (2 subsequent siblings)
5 siblings, 0 replies; 21+ messages in thread
From: Jagadeesh Kona @ 2023-06-09 11:50 UTC (permalink / raw)
To: Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Vladimir Zapolskiy, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Taniya Das, Jagadeesh Kona,
Satya Priya Kakitapalli, Imran Shaik, Ajit Pandey
Add support for camera qdss, sleep and xo clocks.
Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
---
Changes since V3:
- No changes.
Changes since V2:
- No changes.
Changes since V1:
- Newly added.
drivers/clk/qcom/camcc-sm8550.c | 180 ++++++++++++++++++++++++++++++++
1 file changed, 180 insertions(+)
diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c
index 85f0c1e09b2b..82374091b450 100644
--- a/drivers/clk/qcom/camcc-sm8550.c
+++ b/drivers/clk/qcom/camcc-sm8550.c
@@ -22,6 +22,8 @@
enum {
DT_IFACE,
DT_BI_TCXO,
+ DT_BI_TCXO_AO,
+ DT_SLEEP_CLK,
};
enum {
@@ -43,6 +45,7 @@ enum {
P_CAM_CC_PLL10_OUT_EVEN,
P_CAM_CC_PLL11_OUT_EVEN,
P_CAM_CC_PLL12_OUT_EVEN,
+ P_SLEEP_CLK,
};
static const struct pll_vco lucid_ole_vco[] = {
@@ -893,6 +896,22 @@ static const struct clk_parent_data cam_cc_parent_data_11[] = {
{ .hw = &cam_cc_pll7_out_even.clkr.hw },
};
+static const struct parent_map cam_cc_parent_map_12[] = {
+ { P_SLEEP_CLK, 0 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_12[] = {
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map cam_cc_parent_map_13[] = {
+ { P_BI_TCXO, 0 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_13_ao[] = {
+ { .index = DT_BI_TCXO_AO },
+};
+
static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
@@ -1577,6 +1596,29 @@ static struct clk_rcg2 cam_cc_mclk7_clk_src = {
},
};
+static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
+ F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
+ F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_qdss_debug_clk_src = {
+ .cmd_rcgr = 0x13f24,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_qdss_debug_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = {
F(466000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
@@ -1623,6 +1665,26 @@ static struct clk_rcg2 cam_cc_sfe_1_clk_src = {
},
};
+static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
+ F(32000, P_SLEEP_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_sleep_clk_src = {
+ .cmd_rcgr = 0x141a0,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_12,
+ .freq_tbl = ftbl_cam_cc_sleep_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sleep_clk_src",
+ .parent_data = cam_cc_parent_data_12,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_12),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
@@ -1644,6 +1706,26 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
},
};
+static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_xo_clk_src = {
+ .cmd_rcgr = 0x14070,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_13,
+ .freq_tbl = ftbl_cam_cc_xo_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_xo_clk_src",
+ .parent_data = cam_cc_parent_data_13_ao,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_13_ao),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
static struct clk_branch cam_cc_bps_ahb_clk = {
.halt_reg = 0x10274,
.halt_check = BRANCH_HALT,
@@ -1716,6 +1798,42 @@ static struct clk_branch cam_cc_camnoc_axi_clk = {
},
};
+static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
+ .halt_reg = 0x13f18,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13f18,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_camnoc_dcd_xo_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_camnoc_xo_clk = {
+ .halt_reg = 0x13f1c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13f1c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_camnoc_xo_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch cam_cc_cci_0_clk = {
.halt_reg = 0x13a2c,
.halt_check = BRANCH_HALT,
@@ -2382,6 +2500,24 @@ static struct clk_branch cam_cc_drv_ahb_clk = {
},
};
+static struct clk_branch cam_cc_drv_xo_clk = {
+ .halt_reg = 0x142d4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x142d4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_drv_xo_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch cam_cc_icp_ahb_clk = {
.halt_reg = 0x138fc,
.halt_check = BRANCH_HALT,
@@ -2922,6 +3058,42 @@ static struct clk_branch cam_cc_mclk7_clk = {
},
};
+static struct clk_branch cam_cc_qdss_debug_clk = {
+ .halt_reg = 0x14050,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x14050,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_qdss_debug_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_qdss_debug_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_qdss_debug_xo_clk = {
+ .halt_reg = 0x14054,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x14054,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_qdss_debug_xo_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch cam_cc_sbi_clk = {
.halt_reg = 0x10540,
.halt_check = BRANCH_HALT,
@@ -3145,6 +3317,8 @@ static struct clk_regmap *cam_cc_sm8550_clocks[] = {
[CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr,
[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
[CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
+ [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
+ [CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr,
[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
@@ -3196,6 +3370,7 @@ static struct clk_regmap *cam_cc_sm8550_clocks[] = {
[CAM_CC_CSIPHY6_CLK] = &cam_cc_csiphy6_clk.clkr,
[CAM_CC_CSIPHY7_CLK] = &cam_cc_csiphy7_clk.clkr,
[CAM_CC_DRV_AHB_CLK] = &cam_cc_drv_ahb_clk.clkr,
+ [CAM_CC_DRV_XO_CLK] = &cam_cc_drv_xo_clk.clkr,
[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
@@ -3272,6 +3447,9 @@ static struct clk_regmap *cam_cc_sm8550_clocks[] = {
[CAM_CC_PLL11_OUT_EVEN] = &cam_cc_pll11_out_even.clkr,
[CAM_CC_PLL12] = &cam_cc_pll12.clkr,
[CAM_CC_PLL12_OUT_EVEN] = &cam_cc_pll12_out_even.clkr,
+ [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr,
+ [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr,
+ [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
[CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr,
[CAM_CC_SBI_FAST_AHB_CLK] = &cam_cc_sbi_fast_ahb_clk.clkr,
[CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr,
@@ -3280,7 +3458,9 @@ static struct clk_regmap *cam_cc_sm8550_clocks[] = {
[CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr,
[CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr,
[CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr,
+ [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
+ [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
};
static struct gdsc *cam_cc_sm8550_gdscs[] = {
--
2.40.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH V4 4/4] arm64: dts: qcom: sm8550: Add camera clock controller
2023-06-09 11:50 [PATCH V4 0/4] Add camera clock controller support for SM8550 Jagadeesh Kona
` (2 preceding siblings ...)
2023-06-09 11:50 ` [PATCH V4 3/4] clk: qcom: camcc-sm8550: Add support for qdss, sleep and xo clocks Jagadeesh Kona
@ 2023-06-09 11:50 ` Jagadeesh Kona
2023-06-09 12:52 ` Konrad Dybcio
2023-06-09 12:54 ` [PATCH V4 0/4] Add camera clock controller support for SM8550 Konrad Dybcio
2023-06-12 2:25 ` Bryan O'Donoghue
5 siblings, 1 reply; 21+ messages in thread
From: Jagadeesh Kona @ 2023-06-09 11:50 UTC (permalink / raw)
To: Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Vladimir Zapolskiy, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Taniya Das, Jagadeesh Kona,
Satya Priya Kakitapalli, Imran Shaik, Ajit Pandey
Add device node for camera clock controller on Qualcomm
SM8550 platform.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
---
Changes since V3:
- No changes
Changes since V2:
- No changes
Changes since V1:
- Padded non-zero address part to 8 hex digits
arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 75cd374943eb..4d2d610fc66a 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8450-videocc.h>
+#include <dt-bindings/clock/qcom,sm8550-camcc.h>
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
#include <dt-bindings/clock/qcom,sm8550-gpucc.h>
#include <dt-bindings/clock/qcom,sm8550-tcsr.h>
@@ -2419,6 +2420,20 @@ videocc: clock-controller@aaf0000 {
#power-domain-cells = <1>;
};
+ camcc: clock-controller@ade0000 {
+ compatible = "qcom,sm8550-camcc";
+ reg = <0 0x0ade0000 0 0x20000>;
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd SM8550_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
mdss: display-subsystem@ae00000 {
compatible = "qcom,sm8550-mdss";
reg = <0 0x0ae00000 0 0x1000>;
--
2.40.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH V4 4/4] arm64: dts: qcom: sm8550: Add camera clock controller
2023-06-09 11:50 ` [PATCH V4 4/4] arm64: dts: qcom: sm8550: Add camera clock controller Jagadeesh Kona
@ 2023-06-09 12:52 ` Konrad Dybcio
2023-06-14 11:56 ` Jagadeesh Kona
0 siblings, 1 reply; 21+ messages in thread
From: Konrad Dybcio @ 2023-06-09 12:52 UTC (permalink / raw)
To: Jagadeesh Kona, Andy Gross, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Vladimir Zapolskiy, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Taniya Das, Satya Priya Kakitapalli,
Imran Shaik, Ajit Pandey
On 9.06.2023 13:50, Jagadeesh Kona wrote:
> Add device node for camera clock controller on Qualcomm
> SM8550 platform.
>
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
> ---
> Changes since V3:
> - No changes
> Changes since V2:
> - No changes
> Changes since V1:
> - Padded non-zero address part to 8 hex digits
>
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 75cd374943eb..4d2d610fc66a 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -5,6 +5,7 @@
>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/clock/qcom,sm8450-videocc.h>
> +#include <dt-bindings/clock/qcom,sm8550-camcc.h>
> #include <dt-bindings/clock/qcom,sm8550-gcc.h>
> #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
> #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
> @@ -2419,6 +2420,20 @@ videocc: clock-controller@aaf0000 {
> #power-domain-cells = <1>;
> };
>
> + camcc: clock-controller@ade0000 {
> + compatible = "qcom,sm8550-camcc";
> + reg = <0 0x0ade0000 0 0x20000>;
> + clocks = <&gcc GCC_CAMERA_AHB_CLK>,
> + <&bi_tcxo_div2>,
> + <&bi_tcxo_ao_div2>,
> + <&sleep_clk>;
> + power-domains = <&rpmhpd SM8550_MMCX>;
I see that both MMCX ("mmcx.lvl") and MXC ("mxc.lvl") (and MX, FWIW)
are consumed on msm-5.15, with the latter one powering camcc PLLs..
How are they related? Is that resolved internally or does it need
manual intervention?
Konrad
> + required-opps = <&rpmhpd_opp_low_svs>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> mdss: display-subsystem@ae00000 {
> compatible = "qcom,sm8550-mdss";
> reg = <0 0x0ae00000 0 0x1000>;
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH V4 0/4] Add camera clock controller support for SM8550
2023-06-09 11:50 [PATCH V4 0/4] Add camera clock controller support for SM8550 Jagadeesh Kona
` (3 preceding siblings ...)
2023-06-09 11:50 ` [PATCH V4 4/4] arm64: dts: qcom: sm8550: Add camera clock controller Jagadeesh Kona
@ 2023-06-09 12:54 ` Konrad Dybcio
2023-06-14 11:57 ` Jagadeesh Kona
2023-06-12 2:25 ` Bryan O'Donoghue
5 siblings, 1 reply; 21+ messages in thread
From: Konrad Dybcio @ 2023-06-09 12:54 UTC (permalink / raw)
To: Jagadeesh Kona, Andy Gross, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Vladimir Zapolskiy, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Taniya Das, Satya Priya Kakitapalli,
Imran Shaik, Ajit Pandey
On 9.06.2023 13:50, Jagadeesh Kona wrote:
> Add bindings, driver and devicetree node for camera clock controller on
> SM8550.
>
> Jagadeesh Kona (4):
> dt-bindings: clock: qcom: Add SM8550 camera clock controller
> clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550
> clk: qcom: camcc-sm8550: Add support for qdss, sleep and xo clocks
> arm64: dts: qcom: sm8550: Add camera clock controller
What's the final verdict on RINGOSC_L etc.?
Konrad
>
> .../bindings/clock/qcom,sm8450-camcc.yaml | 8 +-
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +
> drivers/clk/qcom/Kconfig | 7 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/camcc-sm8550.c | 3585 +++++++++++++++++
> include/dt-bindings/clock/qcom,sm8550-camcc.h | 187 +
> 6 files changed, 3801 insertions(+), 2 deletions(-)
> create mode 100644 drivers/clk/qcom/camcc-sm8550.c
> create mode 100644 include/dt-bindings/clock/qcom,sm8550-camcc.h
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH V4 2/4] clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550
2023-06-09 11:50 ` [PATCH V4 2/4] clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550 Jagadeesh Kona
@ 2023-06-09 16:22 ` Dmitry Baryshkov
2023-06-14 11:55 ` Jagadeesh Kona
0 siblings, 1 reply; 21+ messages in thread
From: Dmitry Baryshkov @ 2023-06-09 16:22 UTC (permalink / raw)
To: Jagadeesh Kona
Cc: Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Vladimir Zapolskiy, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Satya Priya Kakitapalli, Imran Shaik,
Ajit Pandey
On Fri, 9 Jun 2023 at 14:52, Jagadeesh Kona <quic_jkona@quicinc.com> wrote:
>
> Add support for the camera clock controller for camera clients to be
> able to request for camcc clocks on SM8550 platform.
>
> Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
> ---
> Changes since V3:
> - No changes
> Changes since V2:
> - No changes
> Changes since V1:
> - Sorted the PLL names in proper order
> - Updated all PLL configurations to lower case hex
> - Reused evo ops instead of adding new ops for ole pll
> - Moved few clocks to separate patch to fix patch too long error
>
> drivers/clk/qcom/Kconfig | 7 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/camcc-sm8550.c | 3405 +++++++++++++++++++++++++++++++
> 3 files changed, 3413 insertions(+)
> create mode 100644 drivers/clk/qcom/camcc-sm8550.c
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 9cd1f05d436b..85efed78dc9a 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -756,6 +756,13 @@ config SM_CAMCC_8450
> Support for the camera clock controller on SM8450 devices.
> Say Y if you want to support camera devices and camera functionality.
>
> +config SM_CAMCC_8550
> + tristate "SM8550 Camera Clock Controller"
> + select SM_GCC_8550
> + help
> + Support for the camera clock controller on SM8550 devices.
> + Say Y if you want to support camera devices and camera functionality.
> +
> config SM_DISPCC_6115
> tristate "SM6115 Display Clock Controller"
> depends on ARM64 || COMPILE_TEST
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 75d035150118..97c8cefc2fd0 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -101,6 +101,7 @@ obj-$(CONFIG_SDX_GCC_75) += gcc-sdx75.o
> obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
> obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
> obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
> +obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o
> obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
> obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
> obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
> diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c
> new file mode 100644
> index 000000000000..85f0c1e09b2b
> --- /dev/null
> +++ b/drivers/clk/qcom/camcc-sm8550.c
> @@ -0,0 +1,3405 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,sm8550-camcc.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "common.h"
> +#include "gdsc.h"
> +#include "reset.h"
> +
> +enum {
> + DT_IFACE,
> + DT_BI_TCXO,
> +};
> +
> +enum {
> + P_BI_TCXO,
> + P_CAM_CC_PLL0_OUT_EVEN,
> + P_CAM_CC_PLL0_OUT_MAIN,
> + P_CAM_CC_PLL0_OUT_ODD,
> + P_CAM_CC_PLL1_OUT_EVEN,
> + P_CAM_CC_PLL2_OUT_EVEN,
> + P_CAM_CC_PLL2_OUT_MAIN,
> + P_CAM_CC_PLL3_OUT_EVEN,
> + P_CAM_CC_PLL4_OUT_EVEN,
> + P_CAM_CC_PLL5_OUT_EVEN,
> + P_CAM_CC_PLL6_OUT_EVEN,
> + P_CAM_CC_PLL7_OUT_EVEN,
> + P_CAM_CC_PLL8_OUT_EVEN,
> + P_CAM_CC_PLL9_OUT_EVEN,
> + P_CAM_CC_PLL9_OUT_ODD,
> + P_CAM_CC_PLL10_OUT_EVEN,
> + P_CAM_CC_PLL11_OUT_EVEN,
> + P_CAM_CC_PLL12_OUT_EVEN,
> +};
> +
> +static const struct pll_vco lucid_ole_vco[] = {
> + { 249600000, 2300000000, 0 },
> +};
> +
> +static const struct pll_vco rivian_ole_vco[] = {
> + { 777000000, 1285000000, 0 },
> +};
> +
> +static const struct alpha_pll_config cam_cc_pll0_config = {
> + /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
> + .l = 0x4444003e,
I'd still insist on not touching the config.l field semantics.
> + .alpha = 0x8000,
> + .config_ctl_val = 0x20485699,
> + .config_ctl_hi_val = 0x00182261,
> + .config_ctl_hi1_val = 0x82aa299c,
> + .test_ctl_val = 0x00000000,
> + .test_ctl_hi_val = 0x00000003,
> + .test_ctl_hi1_val = 0x00009000,
> + .test_ctl_hi2_val = 0x00000034,
> + .user_ctl_val = 0x00008400,
> + .user_ctl_hi_val = 0x00000005,
> +};
> +
[skipped the rest, LGTM]
> +
> +static struct platform_driver cam_cc_sm8550_driver = {
> + .probe = cam_cc_sm8550_probe,
> + .driver = {
> + .name = "cam_cc-sm8550",
> + .of_match_table = cam_cc_sm8550_match_table,
> + },
> +};
> +
> +static int __init cam_cc_sm8550_init(void)
> +{
> + return platform_driver_register(&cam_cc_sm8550_driver);
> +}
> +subsys_initcall(cam_cc_sm8550_init);
As it was pointed out, this driver is built as a module by default.
Please perform the tesing and cleanup before sending the driver and
use module_platform_driver.
> +
> +static void __exit cam_cc_sm8550_exit(void)
> +{
> + platform_driver_unregister(&cam_cc_sm8550_driver);
> +}
> +module_exit(cam_cc_sm8550_exit);
> +
> +MODULE_DESCRIPTION("QTI CAMCC SM8550 Driver");
> +MODULE_LICENSE("GPL");
> --
> 2.40.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH V4 0/4] Add camera clock controller support for SM8550
2023-06-09 11:50 [PATCH V4 0/4] Add camera clock controller support for SM8550 Jagadeesh Kona
` (4 preceding siblings ...)
2023-06-09 12:54 ` [PATCH V4 0/4] Add camera clock controller support for SM8550 Konrad Dybcio
@ 2023-06-12 2:25 ` Bryan O'Donoghue
2023-06-13 8:37 ` Krzysztof Kozlowski
5 siblings, 1 reply; 21+ messages in thread
From: Bryan O'Donoghue @ 2023-06-12 2:25 UTC (permalink / raw)
To: Jagadeesh Kona, Andy Gross, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Vladimir Zapolskiy, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Taniya Das, Satya Priya Kakitapalli,
Imran Shaik, Ajit Pandey
On 09/06/2023 12:50, Jagadeesh Kona wrote:
> Add bindings, driver and devicetree node for camera clock controller on
> SM8550.
This is very confusing.
Your cover letter doesn't detail any changes and your individual patches
all say "no changes since v3", "no changes since v2"
If this is a RESEND then mark it as a RESEND.
Good practice is to for example add a note that says
"I looked at updating the yaml for the camcc but opted to do this in
another series" or "opted not to do this at this time" or "it doesn't
make sense because of X"
https://lore.kernel.org/linux-arm-msm/546876ba-970d-5cd5-648e-723698ca74fd@linaro.org/
Could you perhaps RESEND this V4 with a log that explains what has
changed from one version to the next.
If nothing has changed then don't bump the version prefix with RESEND..
Second thought even replying to your cover email with the changelog
would do.....
---
bod
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH V4 0/4] Add camera clock controller support for SM8550
2023-06-12 2:25 ` Bryan O'Donoghue
@ 2023-06-13 8:37 ` Krzysztof Kozlowski
2023-06-13 9:59 ` Jagadeesh Kona
0 siblings, 1 reply; 21+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-13 8:37 UTC (permalink / raw)
To: Bryan O'Donoghue, Jagadeesh Kona, Andy Gross, Konrad Dybcio,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Vladimir Zapolskiy, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Taniya Das, Satya Priya Kakitapalli,
Imran Shaik, Ajit Pandey
On 12/06/2023 04:25, Bryan O'Donoghue wrote:
> On 09/06/2023 12:50, Jagadeesh Kona wrote:
>> Add bindings, driver and devicetree node for camera clock controller on
>> SM8550.
>
> This is very confusing.
>
> Your cover letter doesn't detail any changes and your individual patches
> all say "no changes since v3", "no changes since v2"
>
> If this is a RESEND then mark it as a RESEND.
That's indeed odd. Three versions without changes...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH V4 0/4] Add camera clock controller support for SM8550
2023-06-13 8:37 ` Krzysztof Kozlowski
@ 2023-06-13 9:59 ` Jagadeesh Kona
0 siblings, 0 replies; 21+ messages in thread
From: Jagadeesh Kona @ 2023-06-13 9:59 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bryan O'Donoghue, Andy Gross,
Konrad Dybcio, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Vladimir Zapolskiy, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Taniya Das, Satya Priya Kakitapalli,
Imran Shaik, Ajit Pandey
On 6/13/2023 2:07 PM, Krzysztof Kozlowski wrote:
> On 12/06/2023 04:25, Bryan O'Donoghue wrote:
>> On 09/06/2023 12:50, Jagadeesh Kona wrote:
>>> Add bindings, driver and devicetree node for camera clock controller on
>>> SM8550.
>>
>> This is very confusing.
>>
>> Your cover letter doesn't detail any changes and your individual patches
>> all say "no changes since v3", "no changes since v2"
>>
>> If this is a RESEND then mark it as a RESEND.
>
> That's indeed odd. Three versions without changes...
>
> Best regards,
> Krzysztof
>
This is not a RESEND, actually there were changes from each version to
next version and change details were updated in respective patches. But
the patches in which changes were present were dropped in v4 based on
review comments. Will take care of updating cover letter as well with
changes across versions if we push the next series.
Please find the summary of changes across versions till v4.
Changes in v4:
- Dropped the extra patches added in v2, since the review comments on
v3 recommended an alternate solution.
Changes in v3:
- Squashed 2 extra patches added in v2 into single patch as per review
comments
- Link to v3:
https://patchwork.kernel.org/project/linux-clk/list/?series=753150
Changes in v2:
- Took care of review comments from v1
- Added 2 extra patches updating L configuration value across chipsets
to include CAL_L and RINGOSC_CAL_L fields and removed setting CAL_L
field in clk_lucid_evo_pll_configure().
- Link to v2:
https://patchwork.kernel.org/project/linux-clk/list/?series=751058
v1:
- Initial CAMCC changes for SM8550
- Link to v1:
https://patchwork.kernel.org/project/linux-clk/list/?series=749294
Thanks,
Jagadeesh
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH V4 2/4] clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550
2023-06-09 16:22 ` Dmitry Baryshkov
@ 2023-06-14 11:55 ` Jagadeesh Kona
2023-06-14 12:14 ` Dmitry Baryshkov
0 siblings, 1 reply; 21+ messages in thread
From: Jagadeesh Kona @ 2023-06-14 11:55 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Vladimir Zapolskiy, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Satya Priya Kakitapalli, Imran Shaik,
Ajit Pandey
On 6/9/2023 9:52 PM, Dmitry Baryshkov wrote:
> On Fri, 9 Jun 2023 at 14:52, Jagadeesh Kona <quic_jkona@quicinc.com> wrote:
>>
>> Add support for the camera clock controller for camera clients to be
>> able to request for camcc clocks on SM8550 platform.
>>
>> Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>> ---
>> Changes since V3:
>> - No changes
>> Changes since V2:
>> - No changes
>> Changes since V1:
>> - Sorted the PLL names in proper order
>> - Updated all PLL configurations to lower case hex
>> - Reused evo ops instead of adding new ops for ole pll
>> - Moved few clocks to separate patch to fix patch too long error
>>
>> drivers/clk/qcom/Kconfig | 7 +
>> drivers/clk/qcom/Makefile | 1 +
>> drivers/clk/qcom/camcc-sm8550.c | 3405 +++++++++++++++++++++++++++++++
>> 3 files changed, 3413 insertions(+)
>> create mode 100644 drivers/clk/qcom/camcc-sm8550.c
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 9cd1f05d436b..85efed78dc9a 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -756,6 +756,13 @@ config SM_CAMCC_8450
>> Support for the camera clock controller on SM8450 devices.
>> Say Y if you want to support camera devices and camera functionality.
>>
>> +config SM_CAMCC_8550
>> + tristate "SM8550 Camera Clock Controller"
>> + select SM_GCC_8550
>> + help
>> + Support for the camera clock controller on SM8550 devices.
>> + Say Y if you want to support camera devices and camera functionality.
>> +
>> config SM_DISPCC_6115
>> tristate "SM6115 Display Clock Controller"
>> depends on ARM64 || COMPILE_TEST
>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>> index 75d035150118..97c8cefc2fd0 100644
>> --- a/drivers/clk/qcom/Makefile
>> +++ b/drivers/clk/qcom/Makefile
>> @@ -101,6 +101,7 @@ obj-$(CONFIG_SDX_GCC_75) += gcc-sdx75.o
>> obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
>> obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
>> obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
>> +obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o
>> obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
>> obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
>> obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
>> diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c
>> new file mode 100644
>> index 000000000000..85f0c1e09b2b
>> --- /dev/null
>> +++ b/drivers/clk/qcom/camcc-sm8550.c
>> @@ -0,0 +1,3405 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/of_device.h>
>> +#include <linux/pm_runtime.h>
>> +#include <linux/regmap.h>
>> +
>> +#include <dt-bindings/clock/qcom,sm8550-camcc.h>
>> +
>> +#include "clk-alpha-pll.h"
>> +#include "clk-branch.h"
>> +#include "clk-rcg.h"
>> +#include "clk-regmap.h"
>> +#include "common.h"
>> +#include "gdsc.h"
>> +#include "reset.h"
>> +
>> +enum {
>> + DT_IFACE,
>> + DT_BI_TCXO,
>> +};
>> +
>> +enum {
>> + P_BI_TCXO,
>> + P_CAM_CC_PLL0_OUT_EVEN,
>> + P_CAM_CC_PLL0_OUT_MAIN,
>> + P_CAM_CC_PLL0_OUT_ODD,
>> + P_CAM_CC_PLL1_OUT_EVEN,
>> + P_CAM_CC_PLL2_OUT_EVEN,
>> + P_CAM_CC_PLL2_OUT_MAIN,
>> + P_CAM_CC_PLL3_OUT_EVEN,
>> + P_CAM_CC_PLL4_OUT_EVEN,
>> + P_CAM_CC_PLL5_OUT_EVEN,
>> + P_CAM_CC_PLL6_OUT_EVEN,
>> + P_CAM_CC_PLL7_OUT_EVEN,
>> + P_CAM_CC_PLL8_OUT_EVEN,
>> + P_CAM_CC_PLL9_OUT_EVEN,
>> + P_CAM_CC_PLL9_OUT_ODD,
>> + P_CAM_CC_PLL10_OUT_EVEN,
>> + P_CAM_CC_PLL11_OUT_EVEN,
>> + P_CAM_CC_PLL12_OUT_EVEN,
>> +};
>> +
>> +static const struct pll_vco lucid_ole_vco[] = {
>> + { 249600000, 2300000000, 0 },
>> +};
>> +
>> +static const struct pll_vco rivian_ole_vco[] = {
>> + { 777000000, 1285000000, 0 },
>> +};
>> +
>> +static const struct alpha_pll_config cam_cc_pll0_config = {
>> + /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
>> + .l = 0x4444003e,
>
> I'd still insist on not touching the config.l field semantics.
>
We feel it is better to update config->l field and reuse existing code
than adding separate function for lucid ole pll configure.
>> + .alpha = 0x8000,
>> + .config_ctl_val = 0x20485699,
>> + .config_ctl_hi_val = 0x00182261,
>> + .config_ctl_hi1_val = 0x82aa299c,
>> + .test_ctl_val = 0x00000000,
>> + .test_ctl_hi_val = 0x00000003,
>> + .test_ctl_hi1_val = 0x00009000,
>> + .test_ctl_hi2_val = 0x00000034,
>> + .user_ctl_val = 0x00008400,
>> + .user_ctl_hi_val = 0x00000005,
>> +};
>> +
>
> [skipped the rest, LGTM]
>
>> +
>> +static struct platform_driver cam_cc_sm8550_driver = {
>> + .probe = cam_cc_sm8550_probe,
>> + .driver = {
>> + .name = "cam_cc-sm8550",
>> + .of_match_table = cam_cc_sm8550_match_table,
>> + },
>> +};
>> +
>> +static int __init cam_cc_sm8550_init(void)
>> +{
>> + return platform_driver_register(&cam_cc_sm8550_driver);
>> +}
>> +subsys_initcall(cam_cc_sm8550_init);
>
> As it was pointed out, this driver is built as a module by default.
> Please perform the tesing and cleanup before sending the driver and
> use module_platform_driver.
>
We want clock drivers to be probed early in the bootup to avoid any
probe deferrals of consumer drivers. If there is any scenario where
clock drivers are built statically into kernel, then subsys_initcall()
will ensure clock drivers are probed earlier. When built as module,
subsys_initcall() will fallback to module_init() which is same as
module_platform_driver().
Thanks,
Jagadeesh
>> +
>> +static void __exit cam_cc_sm8550_exit(void)
>> +{
>> + platform_driver_unregister(&cam_cc_sm8550_driver);
>> +}
>> +module_exit(cam_cc_sm8550_exit);
>> +
>> +MODULE_DESCRIPTION("QTI CAMCC SM8550 Driver");
>> +MODULE_LICENSE("GPL");
>> --
>> 2.40.1
>>
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH V4 4/4] arm64: dts: qcom: sm8550: Add camera clock controller
2023-06-09 12:52 ` Konrad Dybcio
@ 2023-06-14 11:56 ` Jagadeesh Kona
2023-06-14 12:15 ` Dmitry Baryshkov
0 siblings, 1 reply; 21+ messages in thread
From: Jagadeesh Kona @ 2023-06-14 11:56 UTC (permalink / raw)
To: Konrad Dybcio, Andy Gross, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Vladimir Zapolskiy, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Taniya Das, Satya Priya Kakitapalli,
Imran Shaik, Ajit Pandey
On 6/9/2023 6:22 PM, Konrad Dybcio wrote:
>
>
> On 9.06.2023 13:50, Jagadeesh Kona wrote:
>> Add device node for camera clock controller on Qualcomm
>> SM8550 platform.
>>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>> ---
>> Changes since V3:
>> - No changes
>> Changes since V2:
>> - No changes
>> Changes since V1:
>> - Padded non-zero address part to 8 hex digits
>>
>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +++++++++++++++
>> 1 file changed, 15 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> index 75cd374943eb..4d2d610fc66a 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> @@ -5,6 +5,7 @@
>>
>> #include <dt-bindings/clock/qcom,rpmh.h>
>> #include <dt-bindings/clock/qcom,sm8450-videocc.h>
>> +#include <dt-bindings/clock/qcom,sm8550-camcc.h>
>> #include <dt-bindings/clock/qcom,sm8550-gcc.h>
>> #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
>> #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
>> @@ -2419,6 +2420,20 @@ videocc: clock-controller@aaf0000 {
>> #power-domain-cells = <1>;
>> };
>>
>> + camcc: clock-controller@ade0000 {
>> + compatible = "qcom,sm8550-camcc";
>> + reg = <0 0x0ade0000 0 0x20000>;
>> + clocks = <&gcc GCC_CAMERA_AHB_CLK>,
>> + <&bi_tcxo_div2>,
>> + <&bi_tcxo_ao_div2>,
>> + <&sleep_clk>;
>> + power-domains = <&rpmhpd SM8550_MMCX>;
> I see that both MMCX ("mmcx.lvl") and MXC ("mxc.lvl") (and MX, FWIW)
> are consumed on msm-5.15, with the latter one powering camcc PLLs..
>
> How are they related? Is that resolved internally or does it need
> manual intervention?
>
> Konrad
These are just different voltage rails, camcc clocks are powered by MMCX
rail and camcc pll's are powered by MXC rail. Consumer drivers need to
take care of voting on these rails properly based on the frequency of
clocks requested.
Thanks,
Jagadeesh
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> +
>> mdss: display-subsystem@ae00000 {
>> compatible = "qcom,sm8550-mdss";
>> reg = <0 0x0ae00000 0 0x1000>;
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH V4 0/4] Add camera clock controller support for SM8550
2023-06-09 12:54 ` [PATCH V4 0/4] Add camera clock controller support for SM8550 Konrad Dybcio
@ 2023-06-14 11:57 ` Jagadeesh Kona
2023-06-14 12:17 ` Dmitry Baryshkov
0 siblings, 1 reply; 21+ messages in thread
From: Jagadeesh Kona @ 2023-06-14 11:57 UTC (permalink / raw)
To: Konrad Dybcio, Andy Gross, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Bjorn Andersson, Vladimir Zapolskiy, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Taniya Das, Satya Priya Kakitapalli,
Imran Shaik, Ajit Pandey
On 6/9/2023 6:24 PM, Konrad Dybcio wrote:
>
>
> On 9.06.2023 13:50, Jagadeesh Kona wrote:
>> Add bindings, driver and devicetree node for camera clock controller on
>> SM8550.
>>
>> Jagadeesh Kona (4):
>> dt-bindings: clock: qcom: Add SM8550 camera clock controller
>> clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550
>> clk: qcom: camcc-sm8550: Add support for qdss, sleep and xo clocks
>> arm64: dts: qcom: sm8550: Add camera clock controller
> What's the final verdict on RINGOSC_L etc.?
>
> Konrad
We would like to pass RINGOSC_CAL_L field directly in config->l value
itself and reuse existing code rather than adding a separate function
for lucid ole pll configure.
Thanks,
Jagadeesh
>>
>> .../bindings/clock/qcom,sm8450-camcc.yaml | 8 +-
>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +
>> drivers/clk/qcom/Kconfig | 7 +
>> drivers/clk/qcom/Makefile | 1 +
>> drivers/clk/qcom/camcc-sm8550.c | 3585 +++++++++++++++++
>> include/dt-bindings/clock/qcom,sm8550-camcc.h | 187 +
>> 6 files changed, 3801 insertions(+), 2 deletions(-)
>> create mode 100644 drivers/clk/qcom/camcc-sm8550.c
>> create mode 100644 include/dt-bindings/clock/qcom,sm8550-camcc.h
>>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH V4 2/4] clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550
2023-06-14 11:55 ` Jagadeesh Kona
@ 2023-06-14 12:14 ` Dmitry Baryshkov
2023-06-23 16:36 ` Jagadeesh Kona
0 siblings, 1 reply; 21+ messages in thread
From: Dmitry Baryshkov @ 2023-06-14 12:14 UTC (permalink / raw)
To: Jagadeesh Kona
Cc: Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Vladimir Zapolskiy, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Satya Priya Kakitapalli, Imran Shaik,
Ajit Pandey
On Wed, 14 Jun 2023 at 14:55, Jagadeesh Kona <quic_jkona@quicinc.com> wrote:
>
>
>
> On 6/9/2023 9:52 PM, Dmitry Baryshkov wrote:
> > On Fri, 9 Jun 2023 at 14:52, Jagadeesh Kona <quic_jkona@quicinc.com> wrote:
> >>
> >> Add support for the camera clock controller for camera clients to be
> >> able to request for camcc clocks on SM8550 platform.
> >>
> >> Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> >> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
> >> ---
> >> Changes since V3:
> >> - No changes
> >> Changes since V2:
> >> - No changes
> >> Changes since V1:
> >> - Sorted the PLL names in proper order
> >> - Updated all PLL configurations to lower case hex
> >> - Reused evo ops instead of adding new ops for ole pll
> >> - Moved few clocks to separate patch to fix patch too long error
> >>
> >> drivers/clk/qcom/Kconfig | 7 +
> >> drivers/clk/qcom/Makefile | 1 +
> >> drivers/clk/qcom/camcc-sm8550.c | 3405 +++++++++++++++++++++++++++++++
> >> 3 files changed, 3413 insertions(+)
> >> create mode 100644 drivers/clk/qcom/camcc-sm8550.c
> >>
> >> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> >> index 9cd1f05d436b..85efed78dc9a 100644
> >> --- a/drivers/clk/qcom/Kconfig
> >> +++ b/drivers/clk/qcom/Kconfig
> >> @@ -756,6 +756,13 @@ config SM_CAMCC_8450
> >> Support for the camera clock controller on SM8450 devices.
> >> Say Y if you want to support camera devices and camera functionality.
> >>
> >> +config SM_CAMCC_8550
> >> + tristate "SM8550 Camera Clock Controller"
> >> + select SM_GCC_8550
> >> + help
> >> + Support for the camera clock controller on SM8550 devices.
> >> + Say Y if you want to support camera devices and camera functionality.
> >> +
> >> config SM_DISPCC_6115
> >> tristate "SM6115 Display Clock Controller"
> >> depends on ARM64 || COMPILE_TEST
> >> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> >> index 75d035150118..97c8cefc2fd0 100644
> >> --- a/drivers/clk/qcom/Makefile
> >> +++ b/drivers/clk/qcom/Makefile
> >> @@ -101,6 +101,7 @@ obj-$(CONFIG_SDX_GCC_75) += gcc-sdx75.o
> >> obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
> >> obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
> >> obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
> >> +obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o
> >> obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
> >> obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
> >> obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
> >> diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c
> >> new file mode 100644
> >> index 000000000000..85f0c1e09b2b
> >> --- /dev/null
> >> +++ b/drivers/clk/qcom/camcc-sm8550.c
> >> @@ -0,0 +1,3405 @@
> >> +// SPDX-License-Identifier: GPL-2.0-only
> >> +/*
> >> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> >> + */
> >> +
> >> +#include <linux/clk-provider.h>
> >> +#include <linux/module.h>
> >> +#include <linux/of_device.h>
> >> +#include <linux/pm_runtime.h>
> >> +#include <linux/regmap.h>
> >> +
> >> +#include <dt-bindings/clock/qcom,sm8550-camcc.h>
> >> +
> >> +#include "clk-alpha-pll.h"
> >> +#include "clk-branch.h"
> >> +#include "clk-rcg.h"
> >> +#include "clk-regmap.h"
> >> +#include "common.h"
> >> +#include "gdsc.h"
> >> +#include "reset.h"
> >> +
> >> +enum {
> >> + DT_IFACE,
> >> + DT_BI_TCXO,
> >> +};
> >> +
> >> +enum {
> >> + P_BI_TCXO,
> >> + P_CAM_CC_PLL0_OUT_EVEN,
> >> + P_CAM_CC_PLL0_OUT_MAIN,
> >> + P_CAM_CC_PLL0_OUT_ODD,
> >> + P_CAM_CC_PLL1_OUT_EVEN,
> >> + P_CAM_CC_PLL2_OUT_EVEN,
> >> + P_CAM_CC_PLL2_OUT_MAIN,
> >> + P_CAM_CC_PLL3_OUT_EVEN,
> >> + P_CAM_CC_PLL4_OUT_EVEN,
> >> + P_CAM_CC_PLL5_OUT_EVEN,
> >> + P_CAM_CC_PLL6_OUT_EVEN,
> >> + P_CAM_CC_PLL7_OUT_EVEN,
> >> + P_CAM_CC_PLL8_OUT_EVEN,
> >> + P_CAM_CC_PLL9_OUT_EVEN,
> >> + P_CAM_CC_PLL9_OUT_ODD,
> >> + P_CAM_CC_PLL10_OUT_EVEN,
> >> + P_CAM_CC_PLL11_OUT_EVEN,
> >> + P_CAM_CC_PLL12_OUT_EVEN,
> >> +};
> >> +
> >> +static const struct pll_vco lucid_ole_vco[] = {
> >> + { 249600000, 2300000000, 0 },
> >> +};
> >> +
> >> +static const struct pll_vco rivian_ole_vco[] = {
> >> + { 777000000, 1285000000, 0 },
> >> +};
> >> +
> >> +static const struct alpha_pll_config cam_cc_pll0_config = {
> >> + /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
> >> + .l = 0x4444003e,
> >
> > I'd still insist on not touching the config.l field semantics.
> >
>
> We feel it is better to update config->l field and reuse existing code
> than adding separate function for lucid ole pll configure.
As you probably got it, I'm not convinced that it is a better
approach. You are feeding additional data in a single configuration
field and passing constant data as variadic one.
>
> >> + .alpha = 0x8000,
> >> + .config_ctl_val = 0x20485699,
> >> + .config_ctl_hi_val = 0x00182261,
> >> + .config_ctl_hi1_val = 0x82aa299c,
> >> + .test_ctl_val = 0x00000000,
> >> + .test_ctl_hi_val = 0x00000003,
> >> + .test_ctl_hi1_val = 0x00009000,
> >> + .test_ctl_hi2_val = 0x00000034,
> >> + .user_ctl_val = 0x00008400,
> >> + .user_ctl_hi_val = 0x00000005,
> >> +};
> >> +
> >
> > [skipped the rest, LGTM]
> >
> >> +
> >> +static struct platform_driver cam_cc_sm8550_driver = {
> >> + .probe = cam_cc_sm8550_probe,
> >> + .driver = {
> >> + .name = "cam_cc-sm8550",
> >> + .of_match_table = cam_cc_sm8550_match_table,
> >> + },
> >> +};
> >> +
> >> +static int __init cam_cc_sm8550_init(void)
> >> +{
> >> + return platform_driver_register(&cam_cc_sm8550_driver);
> >> +}
> >> +subsys_initcall(cam_cc_sm8550_init);
> >
> > As it was pointed out, this driver is built as a module by default.
> > Please perform the tesing and cleanup before sending the driver and
> > use module_platform_driver.
> >
>
> We want clock drivers to be probed early in the bootup to avoid any
> probe deferrals of consumer drivers. If there is any scenario where
> clock drivers are built statically into kernel, then subsys_initcall()
> will ensure clock drivers are probed earlier. When built as module,
> subsys_initcall() will fallback to module_init() which is same as
> module_platform_driver().
Consumer driver probe deferrals are nowadays significantly prevented
by using devlink rather than depending on the initialisation level.
And I think both GKI and defconfig build camcc as modules.
>
> Thanks,
> Jagadeesh
>
> >> +
> >> +static void __exit cam_cc_sm8550_exit(void)
> >> +{
> >> + platform_driver_unregister(&cam_cc_sm8550_driver);
> >> +}
> >> +module_exit(cam_cc_sm8550_exit);
> >> +
> >> +MODULE_DESCRIPTION("QTI CAMCC SM8550 Driver");
> >> +MODULE_LICENSE("GPL");
> >> --
> >> 2.40.1
> >>
> >
> >
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH V4 4/4] arm64: dts: qcom: sm8550: Add camera clock controller
2023-06-14 11:56 ` Jagadeesh Kona
@ 2023-06-14 12:15 ` Dmitry Baryshkov
2023-06-23 16:45 ` Jagadeesh Kona
0 siblings, 1 reply; 21+ messages in thread
From: Dmitry Baryshkov @ 2023-06-14 12:15 UTC (permalink / raw)
To: Jagadeesh Kona
Cc: Konrad Dybcio, Andy Gross, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Vladimir Zapolskiy, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Satya Priya Kakitapalli, Imran Shaik,
Ajit Pandey
On Wed, 14 Jun 2023 at 14:56, Jagadeesh Kona <quic_jkona@quicinc.com> wrote:
>
>
>
> On 6/9/2023 6:22 PM, Konrad Dybcio wrote:
> >
> >
> > On 9.06.2023 13:50, Jagadeesh Kona wrote:
> >> Add device node for camera clock controller on Qualcomm
> >> SM8550 platform.
> >>
> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> >> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
> >> ---
> >> Changes since V3:
> >> - No changes
> >> Changes since V2:
> >> - No changes
> >> Changes since V1:
> >> - Padded non-zero address part to 8 hex digits
> >>
> >> arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +++++++++++++++
> >> 1 file changed, 15 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> >> index 75cd374943eb..4d2d610fc66a 100644
> >> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> >> @@ -5,6 +5,7 @@
> >>
> >> #include <dt-bindings/clock/qcom,rpmh.h>
> >> #include <dt-bindings/clock/qcom,sm8450-videocc.h>
> >> +#include <dt-bindings/clock/qcom,sm8550-camcc.h>
> >> #include <dt-bindings/clock/qcom,sm8550-gcc.h>
> >> #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
> >> #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
> >> @@ -2419,6 +2420,20 @@ videocc: clock-controller@aaf0000 {
> >> #power-domain-cells = <1>;
> >> };
> >>
> >> + camcc: clock-controller@ade0000 {
> >> + compatible = "qcom,sm8550-camcc";
> >> + reg = <0 0x0ade0000 0 0x20000>;
> >> + clocks = <&gcc GCC_CAMERA_AHB_CLK>,
> >> + <&bi_tcxo_div2>,
> >> + <&bi_tcxo_ao_div2>,
> >> + <&sleep_clk>;
> >> + power-domains = <&rpmhpd SM8550_MMCX>;
> > I see that both MMCX ("mmcx.lvl") and MXC ("mxc.lvl") (and MX, FWIW)
> > are consumed on msm-5.15, with the latter one powering camcc PLLs..
> >
> > How are they related? Is that resolved internally or does it need
> > manual intervention?
> >
> > Konrad
>
> These are just different voltage rails, camcc clocks are powered by MMCX
> rail and camcc pll's are powered by MXC rail. Consumer drivers need to
> take care of voting on these rails properly based on the frequency of
> clocks requested.
Which rail powers registers of the camcc? Which rail is required to
read PLL registers?
>
> Thanks,
> Jagadeesh
>
> >> + required-opps = <&rpmhpd_opp_low_svs>;
> >> + #clock-cells = <1>;
> >> + #reset-cells = <1>;
> >> + #power-domain-cells = <1>;
> >> + };
> >> +
> >> mdss: display-subsystem@ae00000 {
> >> compatible = "qcom,sm8550-mdss";
> >> reg = <0 0x0ae00000 0 0x1000>;
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH V4 0/4] Add camera clock controller support for SM8550
2023-06-14 11:57 ` Jagadeesh Kona
@ 2023-06-14 12:17 ` Dmitry Baryshkov
2023-06-23 16:37 ` Jagadeesh Kona
0 siblings, 1 reply; 21+ messages in thread
From: Dmitry Baryshkov @ 2023-06-14 12:17 UTC (permalink / raw)
To: Jagadeesh Kona
Cc: Konrad Dybcio, Andy Gross, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Vladimir Zapolskiy, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Satya Priya Kakitapalli, Imran Shaik,
Ajit Pandey
On Wed, 14 Jun 2023 at 14:58, Jagadeesh Kona <quic_jkona@quicinc.com> wrote:
>
>
>
> On 6/9/2023 6:24 PM, Konrad Dybcio wrote:
> >
> >
> > On 9.06.2023 13:50, Jagadeesh Kona wrote:
> >> Add bindings, driver and devicetree node for camera clock controller on
> >> SM8550.
> >>
> >> Jagadeesh Kona (4):
> >> dt-bindings: clock: qcom: Add SM8550 camera clock controller
> >> clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550
> >> clk: qcom: camcc-sm8550: Add support for qdss, sleep and xo clocks
> >> arm64: dts: qcom: sm8550: Add camera clock controller
> > What's the final verdict on RINGOSC_L etc.?
> >
> > Konrad
>
> We would like to pass RINGOSC_CAL_L field directly in config->l value
> itself and reuse existing code rather than adding a separate function
> for lucid ole pll configure.
As I wrote in another email, it doesn't sound like a good approach.
>
> Thanks,
> Jagadeesh
>
> >>
> >> .../bindings/clock/qcom,sm8450-camcc.yaml | 8 +-
> >> arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +
> >> drivers/clk/qcom/Kconfig | 7 +
> >> drivers/clk/qcom/Makefile | 1 +
> >> drivers/clk/qcom/camcc-sm8550.c | 3585 +++++++++++++++++
> >> include/dt-bindings/clock/qcom,sm8550-camcc.h | 187 +
> >> 6 files changed, 3801 insertions(+), 2 deletions(-)
> >> create mode 100644 drivers/clk/qcom/camcc-sm8550.c
> >> create mode 100644 include/dt-bindings/clock/qcom,sm8550-camcc.h
> >>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH V4 2/4] clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550
2023-06-14 12:14 ` Dmitry Baryshkov
@ 2023-06-23 16:36 ` Jagadeesh Kona
0 siblings, 0 replies; 21+ messages in thread
From: Jagadeesh Kona @ 2023-06-23 16:36 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Vladimir Zapolskiy, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Satya Priya Kakitapalli, Imran Shaik,
Ajit Pandey
On 6/14/2023 5:44 PM, Dmitry Baryshkov wrote:
> On Wed, 14 Jun 2023 at 14:55, Jagadeesh Kona <quic_jkona@quicinc.com> wrote:
>>
>>
>>
>> On 6/9/2023 9:52 PM, Dmitry Baryshkov wrote:
>>> On Fri, 9 Jun 2023 at 14:52, Jagadeesh Kona <quic_jkona@quicinc.com> wrote:
>>>>
>>>> Add support for the camera clock controller for camera clients to be
>>>> able to request for camcc clocks on SM8550 platform.
>>>>
>>>> Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
>>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>>>> ---
>>>> Changes since V3:
>>>> - No changes
>>>> Changes since V2:
>>>> - No changes
>>>> Changes since V1:
>>>> - Sorted the PLL names in proper order
>>>> - Updated all PLL configurations to lower case hex
>>>> - Reused evo ops instead of adding new ops for ole pll
>>>> - Moved few clocks to separate patch to fix patch too long error
>>>>
>>>> drivers/clk/qcom/Kconfig | 7 +
>>>> drivers/clk/qcom/Makefile | 1 +
>>>> drivers/clk/qcom/camcc-sm8550.c | 3405 +++++++++++++++++++++++++++++++
>>>> 3 files changed, 3413 insertions(+)
>>>> create mode 100644 drivers/clk/qcom/camcc-sm8550.c
>>>>
>>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>>>> index 9cd1f05d436b..85efed78dc9a 100644
>>>> --- a/drivers/clk/qcom/Kconfig
>>>> +++ b/drivers/clk/qcom/Kconfig
>>>> @@ -756,6 +756,13 @@ config SM_CAMCC_8450
>>>> Support for the camera clock controller on SM8450 devices.
>>>> Say Y if you want to support camera devices and camera functionality.
>>>>
>>>> +config SM_CAMCC_8550
>>>> + tristate "SM8550 Camera Clock Controller"
>>>> + select SM_GCC_8550
>>>> + help
>>>> + Support for the camera clock controller on SM8550 devices.
>>>> + Say Y if you want to support camera devices and camera functionality.
>>>> +
>>>> config SM_DISPCC_6115
>>>> tristate "SM6115 Display Clock Controller"
>>>> depends on ARM64 || COMPILE_TEST
>>>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>>>> index 75d035150118..97c8cefc2fd0 100644
>>>> --- a/drivers/clk/qcom/Makefile
>>>> +++ b/drivers/clk/qcom/Makefile
>>>> @@ -101,6 +101,7 @@ obj-$(CONFIG_SDX_GCC_75) += gcc-sdx75.o
>>>> obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
>>>> obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
>>>> obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
>>>> +obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o
>>>> obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
>>>> obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
>>>> obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
>>>> diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c
>>>> new file mode 100644
>>>> index 000000000000..85f0c1e09b2b
>>>> --- /dev/null
>>>> +++ b/drivers/clk/qcom/camcc-sm8550.c
>>>> @@ -0,0 +1,3405 @@
>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>> +/*
>>>> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>>>> + */
>>>> +
>>>> +#include <linux/clk-provider.h>
>>>> +#include <linux/module.h>
>>>> +#include <linux/of_device.h>
>>>> +#include <linux/pm_runtime.h>
>>>> +#include <linux/regmap.h>
>>>> +
>>>> +#include <dt-bindings/clock/qcom,sm8550-camcc.h>
>>>> +
>>>> +#include "clk-alpha-pll.h"
>>>> +#include "clk-branch.h"
>>>> +#include "clk-rcg.h"
>>>> +#include "clk-regmap.h"
>>>> +#include "common.h"
>>>> +#include "gdsc.h"
>>>> +#include "reset.h"
>>>> +
>>>> +enum {
>>>> + DT_IFACE,
>>>> + DT_BI_TCXO,
>>>> +};
>>>> +
>>>> +enum {
>>>> + P_BI_TCXO,
>>>> + P_CAM_CC_PLL0_OUT_EVEN,
>>>> + P_CAM_CC_PLL0_OUT_MAIN,
>>>> + P_CAM_CC_PLL0_OUT_ODD,
>>>> + P_CAM_CC_PLL1_OUT_EVEN,
>>>> + P_CAM_CC_PLL2_OUT_EVEN,
>>>> + P_CAM_CC_PLL2_OUT_MAIN,
>>>> + P_CAM_CC_PLL3_OUT_EVEN,
>>>> + P_CAM_CC_PLL4_OUT_EVEN,
>>>> + P_CAM_CC_PLL5_OUT_EVEN,
>>>> + P_CAM_CC_PLL6_OUT_EVEN,
>>>> + P_CAM_CC_PLL7_OUT_EVEN,
>>>> + P_CAM_CC_PLL8_OUT_EVEN,
>>>> + P_CAM_CC_PLL9_OUT_EVEN,
>>>> + P_CAM_CC_PLL9_OUT_ODD,
>>>> + P_CAM_CC_PLL10_OUT_EVEN,
>>>> + P_CAM_CC_PLL11_OUT_EVEN,
>>>> + P_CAM_CC_PLL12_OUT_EVEN,
>>>> +};
>>>> +
>>>> +static const struct pll_vco lucid_ole_vco[] = {
>>>> + { 249600000, 2300000000, 0 },
>>>> +};
>>>> +
>>>> +static const struct pll_vco rivian_ole_vco[] = {
>>>> + { 777000000, 1285000000, 0 },
>>>> +};
>>>> +
>>>> +static const struct alpha_pll_config cam_cc_pll0_config = {
>>>> + /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
>>>> + .l = 0x4444003e,
>>>
>>> I'd still insist on not touching the config.l field semantics.
>>>
>>
>> We feel it is better to update config->l field and reuse existing code
>> than adding separate function for lucid ole pll configure.
>
> As you probably got it, I'm not convinced that it is a better
> approach. You are feeding additional data in a single configuration
> field and passing constant data as variadic one.
>
Will avoid this approach and will add separate lucid ole pll configure
function in next series.
>>
>>>> + .alpha = 0x8000,
>>>> + .config_ctl_val = 0x20485699,
>>>> + .config_ctl_hi_val = 0x00182261,
>>>> + .config_ctl_hi1_val = 0x82aa299c,
>>>> + .test_ctl_val = 0x00000000,
>>>> + .test_ctl_hi_val = 0x00000003,
>>>> + .test_ctl_hi1_val = 0x00009000,
>>>> + .test_ctl_hi2_val = 0x00000034,
>>>> + .user_ctl_val = 0x00008400,
>>>> + .user_ctl_hi_val = 0x00000005,
>>>> +};
>>>> +
>>>
>>> [skipped the rest, LGTM]
>>>
>>>> +
>>>> +static struct platform_driver cam_cc_sm8550_driver = {
>>>> + .probe = cam_cc_sm8550_probe,
>>>> + .driver = {
>>>> + .name = "cam_cc-sm8550",
>>>> + .of_match_table = cam_cc_sm8550_match_table,
>>>> + },
>>>> +};
>>>> +
>>>> +static int __init cam_cc_sm8550_init(void)
>>>> +{
>>>> + return platform_driver_register(&cam_cc_sm8550_driver);
>>>> +}
>>>> +subsys_initcall(cam_cc_sm8550_init);
>>>
>>> As it was pointed out, this driver is built as a module by default.
>>> Please perform the tesing and cleanup before sending the driver and
>>> use module_platform_driver.
>>>
>>
>> We want clock drivers to be probed early in the bootup to avoid any
>> probe deferrals of consumer drivers. If there is any scenario where
>> clock drivers are built statically into kernel, then subsys_initcall()
>> will ensure clock drivers are probed earlier. When built as module,
>> subsys_initcall() will fallback to module_init() which is same as
>> module_platform_driver().
>
> Consumer driver probe deferrals are nowadays significantly prevented
> by using devlink rather than depending on the initialisation level.
> And I think both GKI and defconfig build camcc as modules.
>
Will use module_platform_driver() in next series.
Thanks,
Jagadeesh
>>
>> Thanks,
>> Jagadeesh
>>
>>>> +
>>>> +static void __exit cam_cc_sm8550_exit(void)
>>>> +{
>>>> + platform_driver_unregister(&cam_cc_sm8550_driver);
>>>> +}
>>>> +module_exit(cam_cc_sm8550_exit);
>>>> +
>>>> +MODULE_DESCRIPTION("QTI CAMCC SM8550 Driver");
>>>> +MODULE_LICENSE("GPL");
>>>> --
>>>> 2.40.1
>>>>
>>>
>>>
>
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH V4 0/4] Add camera clock controller support for SM8550
2023-06-14 12:17 ` Dmitry Baryshkov
@ 2023-06-23 16:37 ` Jagadeesh Kona
0 siblings, 0 replies; 21+ messages in thread
From: Jagadeesh Kona @ 2023-06-23 16:37 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, Andy Gross, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Vladimir Zapolskiy, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Satya Priya Kakitapalli, Imran Shaik,
Ajit Pandey
On 6/14/2023 5:47 PM, Dmitry Baryshkov wrote:
> On Wed, 14 Jun 2023 at 14:58, Jagadeesh Kona <quic_jkona@quicinc.com> wrote:
>>
>>
>>
>> On 6/9/2023 6:24 PM, Konrad Dybcio wrote:
>>>
>>>
>>> On 9.06.2023 13:50, Jagadeesh Kona wrote:
>>>> Add bindings, driver and devicetree node for camera clock controller on
>>>> SM8550.
>>>>
>>>> Jagadeesh Kona (4):
>>>> dt-bindings: clock: qcom: Add SM8550 camera clock controller
>>>> clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550
>>>> clk: qcom: camcc-sm8550: Add support for qdss, sleep and xo clocks
>>>> arm64: dts: qcom: sm8550: Add camera clock controller
>>> What's the final verdict on RINGOSC_L etc.?
>>>
>>> Konrad
>>
>> We would like to pass RINGOSC_CAL_L field directly in config->l value
>> itself and reuse existing code rather than adding a separate function
>> for lucid ole pll configure.
>
> As I wrote in another email, it doesn't sound like a good approach.
>
Will avoid this approach and use separate clk_lucid_ole_pll_configure()
to configure lucid ole PLL's in next series.
Thanks,
Jagadeesh
>>
>> Thanks,
>> Jagadeesh
>>
>>>>
>>>> .../bindings/clock/qcom,sm8450-camcc.yaml | 8 +-
>>>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +
>>>> drivers/clk/qcom/Kconfig | 7 +
>>>> drivers/clk/qcom/Makefile | 1 +
>>>> drivers/clk/qcom/camcc-sm8550.c | 3585 +++++++++++++++++
>>>> include/dt-bindings/clock/qcom,sm8550-camcc.h | 187 +
>>>> 6 files changed, 3801 insertions(+), 2 deletions(-)
>>>> create mode 100644 drivers/clk/qcom/camcc-sm8550.c
>>>> create mode 100644 include/dt-bindings/clock/qcom,sm8550-camcc.h
>>>>
>
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH V4 4/4] arm64: dts: qcom: sm8550: Add camera clock controller
2023-06-14 12:15 ` Dmitry Baryshkov
@ 2023-06-23 16:45 ` Jagadeesh Kona
2023-06-23 16:47 ` Konrad Dybcio
0 siblings, 1 reply; 21+ messages in thread
From: Jagadeesh Kona @ 2023-06-23 16:45 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, Andy Gross, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Vladimir Zapolskiy, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Satya Priya Kakitapalli, Imran Shaik,
Ajit Pandey
On 6/14/2023 5:45 PM, Dmitry Baryshkov wrote:
> On Wed, 14 Jun 2023 at 14:56, Jagadeesh Kona <quic_jkona@quicinc.com> wrote:
>>
>>
>>
>> On 6/9/2023 6:22 PM, Konrad Dybcio wrote:
>>>
>>>
>>> On 9.06.2023 13:50, Jagadeesh Kona wrote:
>>>> Add device node for camera clock controller on Qualcomm
>>>> SM8550 platform.
>>>>
>>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>>>> ---
>>>> Changes since V3:
>>>> - No changes
>>>> Changes since V2:
>>>> - No changes
>>>> Changes since V1:
>>>> - Padded non-zero address part to 8 hex digits
>>>>
>>>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +++++++++++++++
>>>> 1 file changed, 15 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>>>> index 75cd374943eb..4d2d610fc66a 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>>>> @@ -5,6 +5,7 @@
>>>>
>>>> #include <dt-bindings/clock/qcom,rpmh.h>
>>>> #include <dt-bindings/clock/qcom,sm8450-videocc.h>
>>>> +#include <dt-bindings/clock/qcom,sm8550-camcc.h>
>>>> #include <dt-bindings/clock/qcom,sm8550-gcc.h>
>>>> #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
>>>> #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
>>>> @@ -2419,6 +2420,20 @@ videocc: clock-controller@aaf0000 {
>>>> #power-domain-cells = <1>;
>>>> };
>>>>
>>>> + camcc: clock-controller@ade0000 {
>>>> + compatible = "qcom,sm8550-camcc";
>>>> + reg = <0 0x0ade0000 0 0x20000>;
>>>> + clocks = <&gcc GCC_CAMERA_AHB_CLK>,
>>>> + <&bi_tcxo_div2>,
>>>> + <&bi_tcxo_ao_div2>,
>>>> + <&sleep_clk>;
>>>> + power-domains = <&rpmhpd SM8550_MMCX>;
>>> I see that both MMCX ("mmcx.lvl") and MXC ("mxc.lvl") (and MX, FWIW)
>>> are consumed on msm-5.15, with the latter one powering camcc PLLs..
>>>
>>> How are they related? Is that resolved internally or does it need
>>> manual intervention?
>>>
>>> Konrad
>>
>> These are just different voltage rails, camcc clocks are powered by MMCX
>> rail and camcc pll's are powered by MXC rail. Consumer drivers need to
>> take care of voting on these rails properly based on the frequency of
>> clocks requested.
>
> Which rail powers registers of the camcc? Which rail is required to
> read PLL registers?
>
MMCX rail is required to access camcc registers, both MMCX and MXC are
required to read PLL registers. MXC rail should be left ON from
bootloaders during bootup and hence does not require explicit voting.
Thanks,
Jagadeesh
>>
>> Thanks,
>> Jagadeesh
>>
>>>> + required-opps = <&rpmhpd_opp_low_svs>;
>>>> + #clock-cells = <1>;
>>>> + #reset-cells = <1>;
>>>> + #power-domain-cells = <1>;
>>>> + };
>>>> +
>>>> mdss: display-subsystem@ae00000 {
>>>> compatible = "qcom,sm8550-mdss";
>>>> reg = <0 0x0ae00000 0 0x1000>;
>
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH V4 4/4] arm64: dts: qcom: sm8550: Add camera clock controller
2023-06-23 16:45 ` Jagadeesh Kona
@ 2023-06-23 16:47 ` Konrad Dybcio
0 siblings, 0 replies; 21+ messages in thread
From: Konrad Dybcio @ 2023-06-23 16:47 UTC (permalink / raw)
To: Jagadeesh Kona, Dmitry Baryshkov
Cc: Andy Gross, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Vladimir Zapolskiy, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Satya Priya Kakitapalli, Imran Shaik,
Ajit Pandey
On 23.06.2023 18:45, Jagadeesh Kona wrote:
>
>
> On 6/14/2023 5:45 PM, Dmitry Baryshkov wrote:
>> On Wed, 14 Jun 2023 at 14:56, Jagadeesh Kona <quic_jkona@quicinc.com> wrote:
>>>
>>>
>>>
>>> On 6/9/2023 6:22 PM, Konrad Dybcio wrote:
>>>>
>>>>
>>>> On 9.06.2023 13:50, Jagadeesh Kona wrote:
>>>>> Add device node for camera clock controller on Qualcomm
>>>>> SM8550 platform.
>>>>>
>>>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>>>>> ---
>>>>> Changes since V3:
>>>>> - No changes
>>>>> Changes since V2:
>>>>> - No changes
>>>>> Changes since V1:
>>>>> - Padded non-zero address part to 8 hex digits
>>>>>
>>>>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +++++++++++++++
>>>>> 1 file changed, 15 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>>>>> index 75cd374943eb..4d2d610fc66a 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
>>>>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>>>>> @@ -5,6 +5,7 @@
>>>>>
>>>>> #include <dt-bindings/clock/qcom,rpmh.h>
>>>>> #include <dt-bindings/clock/qcom,sm8450-videocc.h>
>>>>> +#include <dt-bindings/clock/qcom,sm8550-camcc.h>
>>>>> #include <dt-bindings/clock/qcom,sm8550-gcc.h>
>>>>> #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
>>>>> #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
>>>>> @@ -2419,6 +2420,20 @@ videocc: clock-controller@aaf0000 {
>>>>> #power-domain-cells = <1>;
>>>>> };
>>>>>
>>>>> + camcc: clock-controller@ade0000 {
>>>>> + compatible = "qcom,sm8550-camcc";
>>>>> + reg = <0 0x0ade0000 0 0x20000>;
>>>>> + clocks = <&gcc GCC_CAMERA_AHB_CLK>,
>>>>> + <&bi_tcxo_div2>,
>>>>> + <&bi_tcxo_ao_div2>,
>>>>> + <&sleep_clk>;
>>>>> + power-domains = <&rpmhpd SM8550_MMCX>;
>>>> I see that both MMCX ("mmcx.lvl") and MXC ("mxc.lvl") (and MX, FWIW)
>>>> are consumed on msm-5.15, with the latter one powering camcc PLLs..
>>>>
>>>> How are they related? Is that resolved internally or does it need
>>>> manual intervention?
>>>>
>>>> Konrad
>>>
>>> These are just different voltage rails, camcc clocks are powered by MMCX
>>> rail and camcc pll's are powered by MXC rail. Consumer drivers need to
>>> take care of voting on these rails properly based on the frequency of
>>> clocks requested.
>>
>> Which rail powers registers of the camcc? Which rail is required to
>> read PLL registers?
>>
> MMCX rail is required to access camcc registers, both MMCX and MXC are required to read PLL registers. MXC rail should be left ON from bootloaders during bootup and hence does not require explicit voting.
That's a bad approach. We have a sync_state callback in rpmhpd that kills
unused-from-linux-POV power rails, so Linux should be made aware of any
and all requirements there.
Konrad
>
> Thanks,
> Jagadeesh
>
>>>
>>> Thanks,
>>> Jagadeesh
>>>
>>>>> + required-opps = <&rpmhpd_opp_low_svs>;
>>>>> + #clock-cells = <1>;
>>>>> + #reset-cells = <1>;
>>>>> + #power-domain-cells = <1>;
>>>>> + };
>>>>> +
>>>>> mdss: display-subsystem@ae00000 {
>>>>> compatible = "qcom,sm8550-mdss";
>>>>> reg = <0 0x0ae00000 0 0x1000>;
>>
>>
>>
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2023-06-23 16:47 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-09 11:50 [PATCH V4 0/4] Add camera clock controller support for SM8550 Jagadeesh Kona
2023-06-09 11:50 ` [PATCH V4 1/4] dt-bindings: clock: qcom: Add SM8550 camera clock controller Jagadeesh Kona
2023-06-09 11:50 ` [PATCH V4 2/4] clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550 Jagadeesh Kona
2023-06-09 16:22 ` Dmitry Baryshkov
2023-06-14 11:55 ` Jagadeesh Kona
2023-06-14 12:14 ` Dmitry Baryshkov
2023-06-23 16:36 ` Jagadeesh Kona
2023-06-09 11:50 ` [PATCH V4 3/4] clk: qcom: camcc-sm8550: Add support for qdss, sleep and xo clocks Jagadeesh Kona
2023-06-09 11:50 ` [PATCH V4 4/4] arm64: dts: qcom: sm8550: Add camera clock controller Jagadeesh Kona
2023-06-09 12:52 ` Konrad Dybcio
2023-06-14 11:56 ` Jagadeesh Kona
2023-06-14 12:15 ` Dmitry Baryshkov
2023-06-23 16:45 ` Jagadeesh Kona
2023-06-23 16:47 ` Konrad Dybcio
2023-06-09 12:54 ` [PATCH V4 0/4] Add camera clock controller support for SM8550 Konrad Dybcio
2023-06-14 11:57 ` Jagadeesh Kona
2023-06-14 12:17 ` Dmitry Baryshkov
2023-06-23 16:37 ` Jagadeesh Kona
2023-06-12 2:25 ` Bryan O'Donoghue
2023-06-13 8:37 ` Krzysztof Kozlowski
2023-06-13 9:59 ` Jagadeesh Kona
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).