Hi, Please pull the following changes for the next release. Thanks! Maxime The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b: Linus 5.3-rc1 (2019-07-21 14:05:38 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git refs/tags/sunxi-clk-for-5.4-1 for you to fetch changes up to 65818ad0815f3a2ba6a41327cce8b600ee04be32: clk: sunxi-ng: h6: Allow I2S to change parent rate (2019-08-21 17:20:31 +0800) ---------------------------------------------------------------- Allwinner clock changes for 5.4 A few patches to enable the V3 SoC and fix the i2s clock for the H6. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXV/4KAAKCRDj7w1vZxhR xZxLAP4rYe6+3IudHSM+x7cqAJrtfOFFS+IBOYeNckIY0Hy8XgD/e6mGyYDk7dr8 VCmWuG8nD2u9XAVaxo07ouiOwzEpBgw= =D+Jq -----END PGP SIGNATURE----- ---------------------------------------------------------------- Icenowy Zheng (4): clk: sunxi-ng: v3s: add the missing PLL_DDR1 dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks clk: sunxi-ng: v3s: add Allwinner V3 support Jernej Skrabec (1): clk: sunxi-ng: h6: Allow I2S to change parent rate Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml | 1 +- drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 8 +- drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 250 ++++++- drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 6 +- include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 +- include/dt-bindings/reset/sun8i-v3s-ccu.h | 3 +- 6 files changed, 260 insertions(+), 12 deletions(-) -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com