From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: Dmitry Osipenko <digetx@gmail.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <mperttunen@nvidia.com>,
<gregkh@linuxfoundation.org>, <sboyd@kernel.org>,
<tglx@linutronix.de>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>
Cc: <allison@lohutok.net>, <pdeschrijver@nvidia.com>,
<pgaikwad@nvidia.com>, <mturquette@baylibre.com>,
<horms+renesas@verge.net.au>, <Jisheng.Zhang@synaptics.com>,
<krzk@kernel.org>, <arnd@arndb.de>, <spujar@nvidia.com>,
<josephl@nvidia.com>, <vidyas@nvidia.com>,
<daniel.lezcano@linaro.org>, <mmaddireddy@nvidia.com>,
<markz@nvidia.com>, <devicetree@vger.kernel.org>,
<linux-clk@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <lgirdwood@gmail.com>,
<broonie@kernel.org>, <perex@perex.cz>, <tiwai@suse.com>,
<alexios.zavras@intel.com>, <alsa-devel@alsa-project.org>
Subject: Re: [PATCH v3 08/15] ASoC: tegra: Add audio mclk control through clk_out_1 and extern1
Date: Sat, 7 Dec 2019 11:20:55 -0800 [thread overview]
Message-ID: <2eeceabe-b5f0-6f9e-ff8c-4ac6167b7cc3@nvidia.com> (raw)
In-Reply-To: <0ce2e83b-800c-da1e-7a3c-3cf1427cfe20@gmail.com>
On 12/7/19 6:58 AM, Dmitry Osipenko wrote:
> 06.12.2019 05:48, Sowjanya Komatineni пишет:
>> Current ASoC driver uses extern1 as cdev1 clock from Tegra30 onwards
>> through device tree.
>>
>> Actual audio mclk is clk_out_1 and to use PLLA for mclk rate control,
>> need to clk_out_1_mux parent to extern1 and extern1 parent to PLLA_OUT0.
>>
>> Currently Tegra clock driver init sets the parents and enables both
>> clk_out_1 and extern1 clocks. But these clocks parent and enables should
>> be controlled by ASoC driver.
>>
>> Clock parents can be specified in device tree using assigned-clocks
>> and assigned-clock-parents.
>>
>> To enable audio mclk, both clk_out_1 and extern1 clocks need to be
>> enabled.
>>
>> This patch configures parents for clk_out_1 and extern1 clocks if device
>> tree does not specify clock parents inorder to support old device tree
>> and controls mclk using both clk_out_1 and extern1 clocks.
>>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>> sound/soc/tegra/tegra_asoc_utils.c | 66 ++++++++++++++++++++++++++++++++++++++
>> sound/soc/tegra/tegra_asoc_utils.h | 1 +
>> 2 files changed, 67 insertions(+)
>>
>> diff --git a/sound/soc/tegra/tegra_asoc_utils.c b/sound/soc/tegra/tegra_asoc_utils.c
>> index 536a578e9512..8e3a3740df7c 100644
>> --- a/sound/soc/tegra/tegra_asoc_utils.c
>> +++ b/sound/soc/tegra/tegra_asoc_utils.c
>> @@ -60,6 +60,7 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
>> data->set_mclk = 0;
>>
>> clk_disable_unprepare(data->clk_cdev1);
>> + clk_disable_unprepare(data->clk_extern1);
>> clk_disable_unprepare(data->clk_pll_a_out0);
>> clk_disable_unprepare(data->clk_pll_a);
>>
>> @@ -89,6 +90,14 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
>> return err;
>> }
>>
>> + if (!IS_ERR_OR_NULL(data->clk_extern1)) {
>> + err = clk_prepare_enable(data->clk_extern1);
>> + if (err) {
>> + dev_err(data->dev, "Can't enable extern1: %d\n", err);
>> + return err;
>> + }
>> + }
>> +
>> err = clk_prepare_enable(data->clk_cdev1);
>> if (err) {
>> dev_err(data->dev, "Can't enable cdev1: %d\n", err);
>> @@ -109,6 +118,7 @@ int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data)
>> int err;
>>
>> clk_disable_unprepare(data->clk_cdev1);
>> + clk_disable_unprepare(data->clk_extern1);
>> clk_disable_unprepare(data->clk_pll_a_out0);
>> clk_disable_unprepare(data->clk_pll_a);
>>
>> @@ -142,6 +152,14 @@ int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data)
>> return err;
>> }
>>
>> + if (!IS_ERR_OR_NULL(data->clk_extern1)) {
>> + err = clk_prepare_enable(data->clk_extern1);
>> + if (err) {
>> + dev_err(data->dev, "Can't enable extern1: %d\n", err);
>> + return err;
>> + }
>> + }
> Why this is needed given that clk_extern1 is either a child of MCLK or
> MCLK itself (on T20)? The child clocks are enabled when the parent is
> enabled.
For T30 and later, clk_extern1 is one of the source for clk_out_1_mux.
clk_extern1 is in CAR and it has its own gate and mux.
As audio mclk related clocks (clk_out_1, clk_out_1_mux, and extern1) are
moved into ASoC driver from clock driver
need to enable extern1 gate as well along with clk_out1 for T30 through
T210.
Just FYI, extern1 enable here happens only when data->clk_extern1 is
available which is for T30 onwards.
>> err = clk_prepare_enable(data->clk_cdev1);
>> if (err) {
>> dev_err(data->dev, "Can't enable cdev1: %d\n", err);
>> @@ -158,6 +176,7 @@ EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_ac97_rate);
>> int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
>> struct device *dev)
>> {
>> + struct clk *clk_out_1_mux;
>> int ret;
>>
>> data->dev = dev;
>> @@ -196,6 +215,51 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
>> goto err_put_pll_a_out0;
>> }
> In a previous patch you added fallback to EXTPERIPH when clk_get(MCLK)
> fails. This will work perfectly fine for the older kernels which have
> all clocks in the same single CaR driver, but this may not work that
> great for the newer kernels because PMC driver isn't registered early
> during boot and thus it is possible to get a legit -EPROBE_DEFER which
> shouldn't be ignored. In other words, you need to add into this patch a
> check for the error code returned by clk_get(MCLK) and fallback only for
> -EINVAL.
yeah right, will add check in next version.
>> + /*
>> + * If clock parents are not set in DT, configure here to use clk_out_1
>> + * as mclk and extern1 as parent for Tegra30 and higher.
>> + */
>> + if (!of_find_property(dev->of_node, "assigned-clock-parents", NULL) &&
>> + data->soc > TEGRA_ASOC_UTILS_SOC_TEGRA20) {
>> + data->clk_extern1 = clk_get_sys("clk_out_1", "extern1");
>> + if (IS_ERR(data->clk_extern1)) {
>> + dev_err(data->dev, "Can't retrieve clk extern1\n");
>> + ret = PTR_ERR(data->clk_extern1);
>> + goto err_put_cdev1;
>> + }
>> +
>> + ret = clk_set_parent(data->clk_extern1, data->clk_pll_a_out0);
>> + if (ret < 0) {
>> + dev_err(data->dev,
>> + "Set parent failed for clk extern1: %d\n",
>> + ret);
>> + goto err_put_cdev1;
>> + }
>> +
>> + clk_out_1_mux = clk_get_sys(NULL, "clk_out_1_mux");
> Note1: clk_get(dev, "clk_out_1_mux") should work here by letting clk
> core to fall back to the clk_get_sys() by itself. Either way should be good.
>
> Note2: devm_clk_get() could be used everywhere here. Maybe it won't hurt
> to convert tegra_asoc_utils to use managed resources to keep code a bit
> cleaner. It should be a separate patch.
OK Will add patch to use devm_clk_get() in tegra_asoc_utils_init and
will use same for these patches
>> + if (IS_ERR(clk_out_1_mux)) {
>> + dev_err(data->dev, "Can't retrieve clk clk_out_1_mux\n");
>> + ret = PTR_ERR(clk_out_1_mux);
>> + goto err_put_cdev1;
>> + }
>> +
>> + ret = clk_set_parent(clk_out_1_mux, data->clk_extern1);
>> + if (ret < 0) {
>> + dev_err(data->dev,
>> + "Set parent failed for clk_out_1_mux: %d\n",
>> + ret);
>> + clk_put(clk_out_1_mux);
>> + goto err_put_cdev1;
>> + }
> clk_put(clk_cdev1);
>
>> + data->clk_cdev1 = clk_get_sys(NULL, "clk_out_1");
>> + if (IS_ERR(data->clk_cdev1)) {
>> + dev_err(data->dev, "Can't retrieve clk clk_out_1\n");
>> + ret = PTR_ERR(data->clk_cdev1);
>> + goto err_put_cdev1;
> goto err_put_pll_a_out0;
>
>> + }
>> + }
>> +
>> ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100);
>> if (ret)
>> goto err_put_cdev1;
>> @@ -215,6 +279,8 @@ EXPORT_SYMBOL_GPL(tegra_asoc_utils_init);
>>
>> void tegra_asoc_utils_fini(struct tegra_asoc_utils_data *data)
>> {
>> + if (!IS_ERR_OR_NULL(data->clk_extern1))
>> + clk_put(data->clk_extern1);
>> clk_put(data->clk_cdev1);
>> clk_put(data->clk_pll_a_out0);
>> clk_put(data->clk_pll_a);
>> diff --git a/sound/soc/tegra/tegra_asoc_utils.h b/sound/soc/tegra/tegra_asoc_utils.h
>> index 0c13818dee75..5f2b96478caf 100644
>> --- a/sound/soc/tegra/tegra_asoc_utils.h
>> +++ b/sound/soc/tegra/tegra_asoc_utils.h
>> @@ -25,6 +25,7 @@ struct tegra_asoc_utils_data {
>> struct clk *clk_pll_a;
>> struct clk *clk_pll_a_out0;
>> struct clk *clk_cdev1;
>> + struct clk *clk_extern1;
>> int set_baseclock;
>> int set_mclk;
>> };
>>
next prev parent reply other threads:[~2019-12-07 19:21 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-06 2:48 [PATCH v3 00/15] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
2019-12-06 2:48 ` [PATCH v3 01/15] dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings Sowjanya Komatineni
2019-12-06 18:58 ` Michał Mirosław
2019-12-06 2:48 ` [PATCH v3 02/15] dt-bindings: tegra: Convert Tegra PMC bindings to YAML Sowjanya Komatineni
2019-12-06 2:48 ` [PATCH v3 03/15] soc: tegra: Add Tegra PMC clock registrations into PMC driver Sowjanya Komatineni
2019-12-07 14:28 ` Dmitry Osipenko
2019-12-07 15:47 ` Dmitry Osipenko
2019-12-07 15:53 ` Dmitry Osipenko
2019-12-07 16:00 ` Dmitry Osipenko
2019-12-07 19:59 ` Sowjanya Komatineni
2019-12-07 21:36 ` Sowjanya Komatineni
2019-12-09 20:12 ` Dmitry Osipenko
2019-12-09 20:46 ` Sowjanya Komatineni
2019-12-09 23:03 ` Sowjanya Komatineni
2019-12-10 16:53 ` Sowjanya Komatineni
2019-12-10 17:41 ` Dmitry Osipenko
2019-12-11 1:06 ` Sowjanya Komatineni
2019-12-11 18:50 ` Sowjanya Komatineni
2019-12-12 1:39 ` Dmitry Osipenko
2019-12-12 3:45 ` Sowjanya Komatineni
2019-12-12 3:54 ` Sowjanya Komatineni
2019-12-12 22:13 ` Dmitry Osipenko
2019-12-11 15:10 ` Peter De Schrijver
2019-12-12 1:43 ` Dmitry Osipenko
2019-12-16 12:20 ` Peter De Schrijver
2019-12-16 14:23 ` Dmitry Osipenko
2019-12-16 15:11 ` Peter De Schrijver
2019-12-16 15:24 ` Peter De Schrijver
2019-12-16 15:49 ` Dmitry Osipenko
2019-12-10 17:41 ` Dmitry Osipenko
[not found] ` <22a2f8bd-561d-f4c6-4eef-bb61095c53b2@nvidia.com>
2019-12-10 18:30 ` Dmitry Osipenko
2019-12-10 19:18 ` Sowjanya Komatineni
2019-12-10 20:31 ` Dmitry Osipenko
2019-12-06 2:48 ` [PATCH v3 04/15] dt-bindings: soc: tegra-pmc: Add id for Tegra PMC blink control Sowjanya Komatineni
2019-12-06 2:48 ` [PATCH v3 05/15] soc: pmc: Add blink output clock registration to Tegra PMC Sowjanya Komatineni
2019-12-06 2:48 ` [PATCH v3 06/15] clk: tegra: Remove tegra_pmc_clk_init along with clk ids Sowjanya Komatineni
2019-12-07 14:33 ` Dmitry Osipenko
2019-12-07 14:43 ` Dmitry Osipenko
2019-12-07 15:04 ` Dmitry Osipenko
2019-12-07 19:35 ` Sowjanya Komatineni
2019-12-07 23:24 ` Dmitry Osipenko
2019-12-06 2:48 ` [PATCH v3 07/15] dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings Sowjanya Komatineni
2019-12-06 2:48 ` [PATCH v3 08/15] ASoC: tegra: Add audio mclk control through clk_out_1 and extern1 Sowjanya Komatineni
2019-12-07 14:58 ` Dmitry Osipenko
2019-12-07 19:20 ` Sowjanya Komatineni [this message]
2019-12-09 20:06 ` Dmitry Osipenko
2019-12-09 23:05 ` Sowjanya Komatineni
2019-12-09 23:12 ` Dmitry Osipenko
2019-12-10 0:54 ` Sowjanya Komatineni
2019-12-17 1:29 ` Sowjanya Komatineni
2019-12-17 15:36 ` Dmitry Osipenko
2019-12-17 16:12 ` Sowjanya Komatineni
2019-12-17 16:16 ` Dmitry Osipenko
2019-12-17 16:39 ` Sowjanya Komatineni
2019-12-17 16:46 ` Dmitry Osipenko
2019-12-06 2:48 ` [PATCH v3 09/15] ASoC: tegra: Add fallback for audio mclk Sowjanya Komatineni
2019-12-06 17:49 ` Sowjanya Komatineni
2019-12-06 17:56 ` Greg KH
2019-12-09 16:40 ` Mark Brown
2019-12-09 20:31 ` Dmitry Osipenko
2019-12-09 20:47 ` Mark Brown
2019-12-10 18:24 ` Dmitry Osipenko
2019-12-10 18:59 ` Mark Brown
2019-12-12 2:17 ` Dmitry Osipenko
2019-12-06 2:48 ` [PATCH v3 10/15] clk: tegra: Remove extern1 and cdev1 from clocks inittable Sowjanya Komatineni
2019-12-06 2:48 ` [PATCH v3 11/15] ARM: dts: tegra: Add clock-cells property to pmc Sowjanya Komatineni
2019-12-07 14:26 ` [PATCH v3 00/15] Move PMC clocks into Tegra PMC driver Dmitry Osipenko
2019-12-07 19:22 ` Sowjanya Komatineni
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