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Fri, 4 Jan 2019 18:30:37 +0900 (KST) Received: from epsmgms2p2new.samsung.com (unknown [182.195.42.143]) by epcas2p4.samsung.com (KnoxPortal) with ESMTP id 20190104093036epcas2p4d68eac64fa40e3f5e8da6e26dddcee30~2m0OPHlxN2893128931epcas2p4N; Fri, 4 Jan 2019 09:30:36 +0000 (GMT) X-AuditID: b6c32a46-b2dff70000000fdc-84-5c2f27bd6077 Received: from epmmp2 ( [203.254.227.17]) by epsmgms2p2new.samsung.com (Symantec Messaging Gateway) with SMTP id 20.74.03627.CB72F2C5; Fri, 4 Jan 2019 18:30:36 +0900 (KST) Received: from [106.116.147.40] by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0PKS00966VQXV730@mmp2.samsung.com>; Fri, 04 Jan 2019 18:30:36 +0900 (KST) Subject: Re: Informing common clock framework driver of externally-derived base clock frequency To: Jonny Hall , linux-clk@vger.kernel.org Cc: Stephen Boyd , Michael Turquette From: Sylwester Nawrocki Message-id: <32a08ee4-3989-3785-88d6-7d215147eba3@samsung.com> Date: Fri, 04 Jan 2019 10:30:33 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-version: 1.0 In-reply-to: Content-type: text/plain; charset="utf-8" Content-language: en-GB Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrIIsWRmVeSWpSXmKPExsWy7bCmqe5edf0Yg+ffVS16di5ktfjYc4/V 4uIpV4t/1zayOLB4vL/Ryu4x79F3Jo9NqzrZPD5vkgtgieKySUnNySxLLdK3S+DKOLVZruAi Z8Wv3wtZGxjvsXcxcnJICJhITHz2iLWLkYtDSGAHo0RbYy+U851RYtHFjawwVZ/udjJDJDYw Svx6eg+q6j6jxJIHF4AcDg5hgUSJXXOYQEwRASeJF9/4QHqZBYIkXj5pZAOx2QQMJXqP9jGC 2LwCdhLb9/9nBrFZBFQlrkxtB7NFBSIkOu6vZoOoEZT4MfkeC4jNKRAsMWfTdBaImZoSL75M grLFJY7dv8kIYctLbF7zFuxOCYE1bBIzNsM84CIx/extZghbWOLV8S1Q70tLPFu1kRHCrpbY tb0bqrmDUaLlwnaoBmuJw8cvskJs4JPoOPyXHeRJCQFeiY42IYgSD4lpOw9DA2gJo8SFl63s ExhlZyF5YhaSw2chOXwWksMXMLKsYhRLLSjOTU8tNiow0itOzC0uzUvXS87P3cQITghabjsY l5zzOcQowMGoxMMbwacXI8SaWFZcmXuIUYKDWUmEN5FJP0aINyWxsiq1KD++qDQntfgQozQH i5I470PpudFCAumJJanZqakFqUUwWSYOTqkGRla9a7sVWW5xpG/lfbE69FuQ8fxehwmBEm3r VqxsTi3XaD5ef+2QUkLK6/KLOZeqL+yO31OV0Ma5m+mn9deLp4W2ym1J9J9kF1X1O3WzRsSn xWWPHhTzZuVui4iwCfs383TQ99JD2z0NL+tzCH84+OLyif6+6bvWfPD2U9165HHqPQ0VHXYJ VSWW4oxEQy3mouJEAEJjpD8EAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCLMWRmVeSWpSXmKPExsVy+t9jQd096voxBkemSVn07FzIavGx5x6r xcVTrhb/rm1kcWDxeH+jld1j3qPvTB6bVnWyeXzeJBfAEsVlk5Kak1mWWqRvl8CVcWqzXMFF zopfvxeyNjDeY+9i5OSQEDCR+HS3k7mLkYtDSGAdo8T9OytYIJyHjBKTe56wgVQJCyRKvO59 CNTBwSEi4CTx4hsfRM0yRomnnV/BapgFAiQOPN/ACGKzCRhK9B7tA7N5Bewktu//zwxiswio SlyZ2g5miwpESJx9uQ6qRlDix+R7LCA2p0CwxInOtSwgu5gF1CWmTMmFGC8ucez+TUYIW15i 85q3zBMYBWYh6Z6F0DELSccsJB0LGFlWMUqmFhTnpucWGxUY5aWW6xUn5haX5qXrJefnbmIE hvW2w1r9OxgfL4k/xCjAwajEwxvBpxcjxJpYVlyZe4hRgoNZSYQ3kUk/Rog3JbGyKrUoP76o NCe1+BCjNAeLkjgvf/6xSCGB9MSS1OzU1ILUIpgsEwenVAMjA0/7vXdTfX/f8prxvqosTEdM NDD9utm6PTftQ7TMJLKmrI/K25lzL3Nm0pJ7nya1u11tLHkhZMi4+//2GvdZ1ZUHtl3TL372 TubTwj8Su+y5iwr82xLZDW5U5PvXXXayYFK15n3EMb+qyfz66vzJipyzWZJ+LOm4XSutHfV5 kv3tkgkfDCKVWIozEg21mIuKEwELUWRmZwIAAA== X-CMS-MailID: 20190104093036epcas2p4d68eac64fa40e3f5e8da6e26dddcee30 X-Msg-Generator: CA CMS-TYPE: 102P X-CMS-RootMailID: 20190104023702epcas4p4e6b225121db059cb6ed167581c303e92 References: Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hi, Cc: CCF maintainers On 1/4/19 03:35, Jonny Hall wrote: [...] > ... However, in my application, the input frequency of > the si5342 is not known in advance, is derived from an external > source, and can change during runtime. The si5342 will need to be > (re)configured during operation with the frequency of this root clock > source in order to properly lock onto it and generate the correct > output frequencies -- it cannot independently determine the input > frequency, only "locked" / "unlocked" state. The application software > (other drivers and usermode application code) will know the input > clock rate. I've though of a couple ways to do this: > > -Implement the root clock source as an "imaginary" divider where the > set_rate call actually configures the input dividers of the si5342. > This approach seems to abuse the common clock framework, as I'm not > actually *setting* the rate, I'm *informing* the driver of a rate that > was determined independently. It sounds like registering a clk notifier on the si5342 root source clock might be a way to go, wouldn't that work for you? For an example you could have a look at drivers/clk/sunxi-ng/ccu_mux.c. -- Regards, Sylwester