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Thu, 19 Dec 2019 11:19:32 +0900 (KST) Received: from [10.113.221.102] (unknown [10.113.221.102]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20191219021931epsmtip2a52e5262ee375c57737099344ac1dbff~hpEeUt61l0670006700epsmtip2k; Thu, 19 Dec 2019 02:19:31 +0000 (GMT) Subject: Re: [PATCH v2] clk: samsung: exynos5420: Keep top G3D clocks enabled To: Marek Szyprowski , linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Marian Mihailescu , Stephen Boyd From: Chanwoo Choi Organization: Samsung Electronics Message-ID: <3e7016c8-7c1b-3046-9a53-416ec78046a9@samsung.com> Date: Thu, 19 Dec 2019 11:26:05 +0900 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:59.0) Gecko/20100101 Thunderbird/59.0 MIME-Version: 1.0 In-Reply-To: <20191216131407.17225-1-m.szyprowski@samsung.com> Content-Language: en-US Content-Transfer-Encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA01Sa0hTYRjm2zk7O1arr2n6NsLm6UaGutPcOoaK3Y2ipCsEsg56mLIrO9PK oCwtbWVXlFpXK4m0sMRMi5qsqByVSRiWLaILXaCLReUFrG1HyX/P9zzP+73v830vTahqKDWd b3MJThtvYahRZNOdmdoE/av+bG3p+zHc1aP1cq69/YqC69n3Ss4dbb8t4y7fDSi4+qo+OTf4 7CrJlb3/RGTQmS2egCKzoXYPlbm/sRZl/myIzSI3mFPzBD5XcGoEW449N99mSmOWrTYuMOoN WjaBTeHmMBobbxXSmIXLsxIW51uCYzCaQt5SEKSyeFFkktJTnfYCl6DJs4uuNEZw5FocKY5E kbeKBTZTYo7dOpfVamfrg8aN5ryyymLScX7G5gs7uhXFaGecG0XQgJPB7e6TudEoWoWbEdxr 9VMhQYV/IKj7PlkSfiN4/OQkNVzR2tpBSMItBA/8txXS4RuCl+dayJArEq8Ed0lA7kY0HYXt 4PmyJuQhcDcC/95uFPJQOB68H7vCt47DcdDZ+zbMK3E6XLzlDfMkngYfqjrlITwBr4O2ptIh z3hoO/Yu3Csi6C/tGQz7CRwDL96dlkl4Mlz/ciI8KeA/FBz2dJFShIXQeaNCIeFI+Hy/cQir 4dOB3UN4K1xsu0tJxeUIGr1P5JKgA2/NEVkoGYFnQv2NJImOg5aBk0hqPBa+/toXDg9YCeW7 VZJlCjx9HZBJeCKcK9tDHUSMZ0Qcz4gInhERPP+bnUFkLYoWHKLVJIisQzfytxtQeEXj5zSj K4+X+xCmETNG2buoP1sl5wvFLVYfAppgopTd5X3ZKmUuv6VIcNqNzgKLIPqQPvjahwj1hBx7 cOFtLiOrn63T6bhk1qBnWSZGSfd2ZKuwiXcJZkFwCM7hOhkdoS5GJkNi9Cy/79Jg79/FNW8q 5unco5uX9KQ+zMhPRt4M2jx1Fa/fsGCb79SpP3X0jkLN9b3M9kqi/WBTZPXqvyfwdN/Zscdf f045FltXIj5ffzPwaH/0oaVRuoF0f8m1BxUxDrP6ZvUuer1/TaVrbWHfpklFK/oTrEmG+Ybq H1+NEzu6GFLM49l4winy/wDFIJghuAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIIsWRmVeSWpSXmKPExsWy7bCSvK7JvV+xBt/3sVpsnLGe1eL8+Q3s Fh977rFazDi/j8li7ZG77Bbrp/1ktfh3bSOLRfvTl8wOHB47Z91l99i0qpPNo2/LKkaPz5vk AliiuGxSUnMyy1KL9O0SuDLapzawFCxRr1jeeJu9gbFJsYuRk0NCwETiwIGLzF2MXBxCArsZ JR71XWCGSEhKTLt4FMjmALKFJQ4fLoaoecsocejSXnaQGmEBX4l/HaeYQGwRgXyJGXd6GUGK mAXuMkq0X4BwhAQmMkpM73rDAlLFJqAlsf/FDTYQm19AUeLqj8eMIDavgJ3Eyr37weIsAqoS z6ddZQWxRQXCJHYuecwEUSMocXLmE7A5nED1LR//gdUzC6hL/Jl3iRnCFpe49WQ+E4QtL7H9 7RzmCYzCs5C0z0LSMgtJyywkLQsYWVYxSqYWFOem5xYbFhjlpZbrFSfmFpfmpesl5+duYgRH lJbWDsYTJ+IPMQpwMCrx8P5w/RUrxJpYVlyZe4hRgoNZSYT3dsfPWCHelMTKqtSi/Pii0pzU 4kOM0hwsSuK88vnHIoUE0hNLUrNTUwtSi2CyTBycUg2Mq5xk0pevVhCbu/bVjbO3FnOuk7W0 mVty6qDuVf6LUTXLPRpNZWZXH++azxt+tuXgiu9ThTZxut9LUHt401hF4NhWv0/2xydNDAwI l/X4J/Eu4n338+0lLC0r7849I6T45PzDq+7zVJ/yXTC1m/Oyt0iro3B+zpmr+5zvXPgdXP37 7rvji45d2arEUpyRaKjFXFScCACwlqrwpAIAAA== X-CMS-MailID: 20191219021932epcas1p1e4d340dfa8a04323ee417730e7aba2e2 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: SVC_REQ_APPROVE CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20191216131423eucas1p2162d6bf0a870357be9f0ab308641015b References: <20191216131407.17225-1-m.szyprowski@samsung.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 12/16/19 10:14 PM, Marek Szyprowski wrote: > In Exynos542x/5800 SoCs, the G3D leaf clocks are located in the G3D power > domain. This is similar to the other hardware modules and their power > domains. However there is one thing specific to G3D clocks hierarchy. > Unlike other hardware modules, the G3D clocks hierarchy doesn't have any > gate clock between the TOP part of the hierarchy and the part located in > the power domain and some SoC internal busses are sourced directly from > the TOP muxes. The consequence of this design if the fact that the TOP > part of the hierarchy has to be enabled permanently to ensure proper > operation of the SoC power related components (G3D power domain and > Exynos Power Management Unit for system suspend/resume). > > This patch adds an explicit call to clk_prepare_enable() on the last MUX > in the TOP part of G3D clock hierarchy to keep it enabled permanently to > ensure that the internal busses get their clock regardless of the main > G3D clock enablement status. > > This fixes following imprecise abort issue observed on Odroid XU3/XU4 > after enabling Panfrost driver by commit 1a5a85c56402 "ARM: dts: exynos: > Add Mali/GPU node on Exynos5420 and enable it on Odroid XU3/4"): > > panfrost 11800000.gpu: clock rate = 400000000 > panfrost 11800000.gpu: failed to get regulator: -517 > panfrost 11800000.gpu: regulator init failed -517 > Power domain G3D disable failed > ... > panfrost 11800000.gpu: clock rate = 400000000 > 8<--- cut here --- > Unhandled fault: imprecise external abort (0x1406) at 0x00000000 > pgd = (ptrval) > [00000000] *pgd=00000000 > Internal error: : 1406 [#1] PREEMPT SMP ARM > Modules linked in: > CPU: 7 PID: 53 Comm: kworker/7:1 Not tainted 5.4.0-rc8-next-20191119-00032-g56f1001191a6 #6923 > Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) > Workqueue: events deferred_probe_work_func > PC is at panfrost_gpu_soft_reset+0x94/0x110 > LR is at ___might_sleep+0x128/0x2dc > ... > [] (panfrost_gpu_soft_reset) from [] (panfrost_gpu_init+0x10/0x67c) > [] (panfrost_gpu_init) from [] (panfrost_device_init+0x158/0x2cc) > [] (panfrost_device_init) from [] (panfrost_probe+0x80/0x178) > [] (panfrost_probe) from [] (platform_drv_probe+0x48/0x9c) > [] (platform_drv_probe) from [] (really_probe+0x1c4/0x474) > [] (really_probe) from [] (driver_probe_device+0x78/0x1bc) > [] (driver_probe_device) from [] (bus_for_each_drv+0x74/0xb8) > [] (bus_for_each_drv) from [] (__device_attach+0xd4/0x16c) > [] (__device_attach) from [] (bus_probe_device+0x88/0x90) > [] (bus_probe_device) from [] (deferred_probe_work_func+0x4c/0xd0) > [] (deferred_probe_work_func) from [] (process_one_work+0x300/0x864) > [] (process_one_work) from [] (worker_thread+0x58/0x5a0) > [] (worker_thread) from [] (kthread+0x12c/0x160) > [] (kthread) from [] (ret_from_fork+0x14/0x20) > Exception stack(0xee03dfb0 to 0xee03dff8) > ... > Code: e594300c e5933020 e3130c01 1a00000f (ebefff50). > ---[ end trace badde2b74a65a540 ]--- > > In the above case, the Panfrost driver disables G3D clocks after failure > of getting the needed regulator and return with -EPROVE_DEFER code. This > causes G3D power domain disable failure and then, during second probe > an imprecise abort is triggered due to undefined power domain state. > > Fixes: 45f10dabb56b ("clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path") > Fixes: c9f7567aff31 ("clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU") > Signed-off-by: Marek Szyprowski > --- > drivers/clk/samsung/clk-exynos5420.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c > index 3a991ca1ee36..c9e5a1fb6653 100644 > --- a/drivers/clk/samsung/clk-exynos5420.c > +++ b/drivers/clk/samsung/clk-exynos5420.c > @@ -12,6 +12,7 @@ > #include > #include > #include > +#include > > #include "clk.h" > #include "clk-cpu.h" > @@ -1646,6 +1647,13 @@ static void __init exynos5x_clk_init(struct device_node *np, > exynos5x_subcmus); > } > > + /* > + * Keep top part of G3D clock path enabled permanently to ensure > + * that the internal busses get their clock regardless of the > + * main G3D clock enablement status. > + */ > + clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d")); > + > samsung_clk_of_add_provider(np, ctx); > } > > I tested it by checking the enable count of 'mout_sw_aclk_g3d'. Acked-by: Chanwoo Choi -- Best Regards, Chanwoo Choi Samsung Electronics