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([2a01:e0a:982:cbb0:b25a:b26e:71f3:870c]) by smtp.gmail.com with ESMTPSA id f23-20020a1c6a17000000b003eddc6aa5fasm10574507wmc.39.2023.06.26.06.36.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Jun 2023 06:36:25 -0700 (PDT) Message-ID: <41e6d93a-8899-e792-0859-d26360ef5dab@linaro.org> Date: Mon, 26 Jun 2023 15:36:23 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 From: neil.armstrong@linaro.org Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH v1 6/6] arm64: dts: meson: a1: add eMMC controller and its pins Content-Language: en-US To: Martin Blumenstingl , Dmitry Rokosov Cc: jbrunet@baylibre.com, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, khilman@baylibre.com, conor+dt@kernel.org, kernel@sberdevices.ru, sdfw_system_team@sberdevices.ru, rockosov@gmail.com, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jan Dakinevich References: <20230607201641.20982-1-ddrokosov@sberdevices.ru> <20230607201641.20982-7-ddrokosov@sberdevices.ru> Organization: Linaro Developer Services In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hi, On 25/06/2023 23:11, Martin Blumenstingl wrote: > On Wed, Jun 7, 2023 at 10:16 PM Dmitry Rokosov wrote: >> >> From: Jan Dakinevich >> >> The definition is inspired by a similar one for AXG SoC family. >> 'sdio_pins' and 'sdio_clk_gate_pins' pinctrls are supposed to be used as >> "default" and "clk-gate" in board-specific device trees. > Let's wait for Neil's response on the other patch for the question > about pin mux settings > >> 'meson-gx' driver during initialization sets clock to safe low-frequency >> value (400kHz). However, both source clocks ("clkin0" and "clkin1") are >> high-frequency by default, and using of eMMC's internal divider is not >> enough to achieve so low values. To provide low-frequency source, >> reparent "sd_emmc_sel2" clock using 'assigned-clocks' property. > Even if the pinctrl part should be postponed then I think it's worth > adding &sd_emmc Yeah it's weird to add HW definition and to not enable them, so please enable them in the board if you add them in the DTSI. Neil