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From: "Tanwar, Rahul" <rahul.tanwar@linux.intel.com>
To: Stephen Boyd <sboyd@kernel.org>,
	linux-clk@vger.kernel.org, mark.rutland@arm.com,
	mturquette@baylibre.com, robh+dt@kernel.org, robh@kernel.org
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	andriy.shevchenko@intel.com, qi-ming.wu@intel.com,
	yixin.zhu@linux.intel.com, cheol.yong.kim@intel.com
Subject: Re: [PATCH v4 2/2] dt-bindings: clk: intel: Add bindings document & header file for CGU
Date: Wed, 5 Feb 2020 17:10:20 +0800	[thread overview]
Message-ID: <556c2277-885c-f6be-60b3-564187618ca6@linux.intel.com> (raw)
In-Reply-To: <20200131022541.3853C2067C@mail.kernel.org>


Hi Stephen,

Thanks for taking time out to review.

On 31/1/2020 10:25 AM, Stephen Boyd wrote:
> Quoting Rahul Tanwar (2020-01-30 01:04:03)
>> Clock generation unit(CGU) is a clock controller IP of Intel's Lightning
>> Mountain(LGM) SoC. Add DT bindings include file and document for CGU clock
>> controller driver of LGM.
>>
>> Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
>> ---
>>
>> +
>> +/* LJPLL4 */
>> +#define LGM_CLK_PCIE           45
>> +#define LGM_CLK_SATA           LGM_CLK_PCIE
> What is with the aliases?

Aliases are just for code readability when more than one peripherals
share the same clock.

Regards,
Rahul



      reply	other threads:[~2020-02-05  9:10 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-30  9:04 [PATCH v4 0/2] clk: intel: Add a new driver for a new clock controller IP Rahul Tanwar
2020-01-30  9:04 ` [PATCH v4 1/2] clk: intel: Add CGU clock driver for a new SoC Rahul Tanwar
2020-01-31  2:24   ` Stephen Boyd
2020-02-13  8:04     ` Tanwar, Rahul
2020-01-30  9:04 ` [PATCH v4 2/2] dt-bindings: clk: intel: Add bindings document & header file for CGU Rahul Tanwar
2020-01-31  2:25   ` Stephen Boyd
2020-02-05  9:10     ` Tanwar, Rahul [this message]

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