From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: Dmitry Osipenko <digetx@gmail.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <frankc@nvidia.com>, <hverkuil@xs4all.nl>,
<helen.koike@collabora.com>
Cc: <sboyd@kernel.org>, <linux-media@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [RFC PATCH v5 6/9] media: tegra: Add Tegra210 Video input driver
Date: Tue, 24 Mar 2020 18:08:52 -0700 [thread overview]
Message-ID: <5695fc27-6839-dda3-9d06-77ef36ecfd43@nvidia.com> (raw)
In-Reply-To: <8f44e42d-2008-fe53-f4fb-b57502da91a8@gmail.com>
On 3/24/20 5:34 PM, Dmitry Osipenko wrote:
> External email: Use caution opening links or attachments
>
>
> 23.03.2020 20:52, Sowjanya Komatineni пишет:
>> +static void tegra_channel_vi_soft_reset(struct tegra_vi_channel *chan)
>> +{
>> + /* disable clock gating to enable continuous clock */
>> + tegra_vi_write(chan, TEGRA_VI_CFG_CG_CTRL, 0);
>> + /*
>> + * Soft reset memory client interface, pixel format logic, sensor
>> + * control logic, and a shadow copy logic to bring VI to clean state.
>> + */
>> + vi_csi_write(chan, TEGRA_VI_CSI_SW_RESET, 0xf);
>> + usleep_range(100, 200);
>> + vi_csi_write(chan, TEGRA_VI_CSI_SW_RESET, 0x0);
> Is it safe to reset MCCIF without blocking and flushing memory requests
> at first?
Yes to bring VI to clean state on errors its recommended by HW design team.
next prev parent reply other threads:[~2020-03-25 1:08 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-23 17:52 [RFC PATCH v5 0/9] Add Tegra driver for video capture Sowjanya Komatineni
2020-03-23 17:52 ` [RFC PATCH v5 1/9] arm64: tegra: Fix sor powergate clocks and reset Sowjanya Komatineni
2020-03-23 17:52 ` [RFC PATCH v5 2/9] arm64: tegra: Add reset-cells to mc Sowjanya Komatineni
2020-03-23 17:52 ` [RFC PATCH v5 3/9] dt-bindings: clock: tegra: Add clk id for CSI TPG clock Sowjanya Komatineni
2020-03-23 17:52 ` [RFC PATCH v5 4/9] clk: tegra: Add Tegra210 CSI TPG clock gate Sowjanya Komatineni
2020-03-23 17:52 ` [RFC PATCH v5 5/9] dt-binding: tegra: Add VI and CSI bindings Sowjanya Komatineni
2020-03-24 19:20 ` Dmitry Osipenko
2020-03-24 21:16 ` Sowjanya Komatineni
2020-03-23 17:52 ` [RFC PATCH v5 6/9] media: tegra: Add Tegra210 Video input driver Sowjanya Komatineni
2020-03-25 0:34 ` Dmitry Osipenko
2020-03-25 1:08 ` Sowjanya Komatineni [this message]
2020-03-25 1:15 ` Sowjanya Komatineni
2020-03-25 19:43 ` Dmitry Osipenko
[not found] ` <20200325110358.GB853@valkosipuli.retiisi.org.uk>
2020-03-25 11:09 ` Hans Verkuil
[not found] ` <a219aeb2-3d00-016e-eed9-503a9fbd0d13@nvidia.com>
2020-03-26 14:48 ` Sakari Ailus
2020-03-26 17:04 ` Sowjanya Komatineni
2020-03-30 10:59 ` Hans Verkuil
2020-03-31 10:32 ` Sakari Ailus
2020-03-31 10:56 ` Hans Verkuil
2020-03-31 11:10 ` Sakari Ailus
2020-03-31 11:27 ` Hans Verkuil
2020-03-31 11:52 ` Laurent Pinchart
2020-03-31 16:40 ` Sowjanya Komatineni
2020-03-31 18:33 ` Sowjanya Komatineni
2020-04-01 16:36 ` Sowjanya Komatineni
2020-04-01 16:58 ` Laurent Pinchart
2020-04-01 18:24 ` Sowjanya Komatineni
2020-04-03 7:36 ` Sowjanya Komatineni
2020-03-23 17:52 ` [RFC PATCH v5 7/9] MAINTAINERS: Add Tegra Video driver section Sowjanya Komatineni
2020-03-23 17:52 ` [RFC PATCH v5 8/9] dt-bindings: reset: Add ID for Tegra210 VI reset Sowjanya Komatineni
2020-03-23 17:52 ` [RFC PATCH v5 9/9] arm64: tegra: Add Tegra VI CSI support in device tree Sowjanya Komatineni
2020-03-24 19:19 ` Dmitry Osipenko
2020-03-24 21:04 ` Sowjanya Komatineni
2020-03-24 22:48 ` Dmitry Osipenko
2020-03-25 0:01 ` Sowjanya Komatineni
2020-03-25 0:22 ` Dmitry Osipenko
2020-03-30 10:04 ` [RFC PATCH v5 0/9] Add Tegra driver for video capture Hans Verkuil
2020-03-30 11:02 ` Hans Verkuil
2020-03-30 16:16 ` Sowjanya Komatineni
2020-04-03 5:45 ` Sowjanya Komatineni
2020-04-03 7:19 ` Hans Verkuil
2020-04-03 7:31 ` Sowjanya Komatineni
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