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Mon, 11 Feb 2019 10:21:17 +0000 (GMT) Subject: Re: [PATCH v3 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC To: cwchoi00@gmail.com Cc: Chanwoo Choi , devicetree , linux-kernel , Linux PM list , linux-samsung-soc , Bartlomiej Zolnierkiewicz , Krzysztof Kozlowski , Kukjin Kim , Kyungmin Park , Marek Szyprowski , Sylwester Nawrocki , MyungJoo Ham , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-arm-kernel From: Lukasz Luba Message-ID: <59a5e9bc-a5de-9f98-5710-4cd48cb5b239@partner.samsung.com> Date: Mon, 11 Feb 2019 11:21:16 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US Content-Transfer-Encoding: 8bit X-Brightmail-Tracker: H4sIAAAAAAAAA01SaUhUURj1zps377mMXEfNj0lKBm0lNwJvC1KhMUVE0Y+ihHrlcynHbJ5a lpAmpZktirhMhoaVNhXlaKWDmrkNWm6Vtm80FJpj5kKWoTk+Jf+de8757vkOfCyleEMr2cjo WF4bzUWpZHbSB82/O1YUbuFCfLuNDCnLu0uTlyPfaPK1aTkpbGynycUv3ynS0XGPIW2n+hli +NJDk58ZH2jy3FggI8PnGxHJ66iVkDuN7xnS1RpM3iaXykhDfypNJnrKpOuc1D9enWbUVbr3 jNqgPytTl187qb5QoUfqYcOCbbLddmtD+ajIeF7rE7jPLqK33z9mXHWsu9giSUIG93RkywJe Cf352VQ6smMVuBTB+FgNsgoKPIKgp9VTFIYR3M+7xcxO6C0PaVEoQZBRfEMiPiwI3hWfo6wu Z7wDrjS/llmxC54HD3PMyGqi8CMajL19U+MsK8PeUKk/YvXI8UbILKyYTpBiL8gtvimxYle8 CxrODyDR4wQt+WapFdvi7VBnLp3mKewGb8yFEhEvhJT7l6f7AE5mIbusfmbtIDAm3ZKK2Bn6 TBUzvDtMVonDgAVoS9PLRJwIqS2VM5410GDqmt6ZwkvhrtEnHTFT9HqoWWclATvCK4uTuIAj ZD3IpURaDmlnFOIXS6Aio3MmZh6U3M5hLiGVbk4t3ZwqujlVdP9Ti5BUj9z4OEETzgt+0fxR b4HTCHHR4d4HDmsMaOrinkyYhirR6LP99QizSOUgH+T2hShoLl5I0NQjYCmVi3z/Ji5EIQ/l Eo7z2sN7tXFRvFCP5rNSlZv8hM2nPQoczsXyh3g+htfOqhLWVpmEXBZX2zsN3PgccPXM2Iux gA2JHuWqZ6vKOX/LhdrXi1IXf0xWHlBybb6bbbwO5po1muT8waUlXp8dOhsG0of9jio8U+qq R9P0QmNAe7Bbnun6n1QPX4/HLdtdBv56B6Ktul/2YZlDpCri+dOCpsoiiJ90NQ29Wx2kHKva meXYlB+mkgoRnN8ySitw/wBcWbGwbQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrIIsWRmVeSWpSXmKPExsVy+t/xu7rzfBJjDG6uF7TYOGM9q8X1L89Z LZ4d1baYf+Qcq0X/49fMFufPb2C3ONv0ht1i0+NrrBYfe+6xWlzeNYfN4nPvEUaLGef3MVms PXKX3eLiKVeL240r2CwOv2lntfh3bSOLg6DH+xut7B47Z91l99i0qpPNY/OSeo++LasYPT5v kgtgi9KzKcovLUlVyMgvLrFVija0MNIztLTQMzKx1DM0No+1MjJV0rezSUnNySxLLdK3S9DL ePnGqOC3UsXVxW+ZGhg3yXQxcnJICJhIrHq7nbWLkYtDSGApo8SbDd3sEAkxiUn7tkPZwhJ/ rnWxQRS9ZpS4frSFGSQhLBAs8aX1HSOILQLUsH3aE0aQImaBo6wS1zpvQY2dwSwx+/hCIIeD g01AT2LHqkKQBl4BN4mJ87eAbWARUJWYvnglE4gtKhAh8fHpPiaIGkGJkzOfsIDYnAKBEgee rABbxixgJjFv80NmCFtc4taT+UwQtrxE89bZzBMYhWYhaZ+FpGUWkpZZSFoWMLKsYhRJLS3O Tc8tNtQrTswtLs1L10vOz93ECIzubcd+bt7BeGlj8CFGAQ5GJR7eD4kJMUKsiWXFlbmHGCU4 mJVEeJM8E2OEeFMSK6tSi/Lji0pzUosPMZoCPTeRWUo0OR+YePJK4g1NDc0tLA3Njc2NzSyU xHnPG1RGCQmkJ5akZqemFqQWwfQxcXBKNTBO21+yLGnPPpYDM35mKd8VP84lnnv54o9d9xcw 5n14nckj3Boidm/T5htRU+Wt25untLcc/nw0Szvr14asJz9EP96fP1EmzqHszW9v3yQbT7+t Ej9u9O2clzPr+Mw/Z98xlN9oYNcwMPHvj8786fbR+NWmt2eYdaraTP+snTdfPHCGOe+y85vW KrEUZyQaajEXFScCAMIXbYoEAwAA X-CMS-MailID: 20190211102118eucas1p10b2314a2e0cd705d33b4c38fb0689e0f X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20190131085007eucas1p2f16107042b8ce5638811840618bcf017 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190131085007eucas1p2f16107042b8ce5638811840618bcf017 References: <1548924594-19084-1-git-send-email-l.luba@partner.samsung.com> <1548924594-19084-4-git-send-email-l.luba@partner.samsung.com> <0ca15b4c-ddaa-1be5-35be-e76b008b28a8@partner.samsung.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hi Chanwoo, On 2/3/19 8:54 AM, Chanwoo Choi wrote: > Hi Lukasz, > > 2019년 2월 1일 (금) 오후 11:22, Lukasz Luba 님이 작성: > >> >> Hi Chanwoo, >> >> On 2/1/19 9:44 AM, Chanwoo Choi wrote: >>> Hi, >>> >>> On 19. 1. 31. 오후 5:49, Lukasz Luba wrote: >>>> Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory >>>> Controller frequencies for driver's DRAM timings. >>>> >>>> CC: Sylwester Nawrocki >>>> CC: Chanwoo Choi >>>> CC: Michael Turquette >>>> CC: Stephen Boyd >>>> CC: Kukjin Kim >>>> CC: Krzysztof Kozlowski >>>> CC: linux-samsung-soc@vger.kernel.org >>>> CC: linux-clk@vger.kernel.org >>>> CC: linux-arm-kernel@lists.infradead.org >>>> CC: linux-kernel@vger.kernel.org >>>> Signed-off-by: Lukasz Luba >>>> --- >>>> drivers/clk/samsung/clk-exynos5420.c | 15 ++++++++++++++- >>>> 1 file changed, 14 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c >>>> index 3e87421..8bf9579 100644 >>>> --- a/drivers/clk/samsung/clk-exynos5420.c >>>> +++ b/drivers/clk/samsung/clk-exynos5420.c >>>> @@ -1325,6 +1325,19 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini >>>> PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), >>>> }; >>>> >>>> +static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = { >>>> + PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1), >>>> + PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1), >>>> + PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1), >>>> + PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1), >>>> + PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2), >>>> + PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2), >>>> + PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3), >>>> + PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3), >>>> + PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3), >>>> + PLL_35XX_RATE(24 * MHZ, 138000000, 184, 2, 4), >>> >>> Except for 825Mhz, I can't find the target frequency >>> on Exynos5422 TRM document. Usually, Exynos TRM specified >>> the supported stable clocks. It means that undefined clocks >>> are not stable as I knew. Where do you find them? >>> >>> When I calculated the PLL frequency with PMS value, it is correct. >>> But, just we need to check the reference of undefined clocks on TRM >>> in order to guarantee the stable operation. >> They values live in vendor code for Android. >> I have tested the DMC & DDR with these ratios in stress scenarios >> for a few days and it was stable. > > If possible, please share the url of original vendor code. Here is the vendor code for the BPLL values: https://github.com/hardkernel/linux/blob/odroidxu3-3.10.y-android/drivers/clk/samsung/clk-exynos5422.c#L2026 Regards, Lukasz > >> >>> >>> Remove 933/138Mhz because exynos5433-dmc.c doesn't use 933Mhz and 138Mhz >>> and also Exynos5422 TRM doesn't define 933/138Mhz on pll table. >> OK, I will remove them. >>> >>>> +}; >>>> + >>>> static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { >>>> PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), >>>> PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), >>>> @@ -1467,7 +1480,7 @@ static void __init exynos5x_clk_init(struct device_node *np, >>>> exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; >>>> exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; >>>> exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; >>>> - exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; >>>> + exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table; >>> >>> Exynos5422 used the same PLL table for apll, kpll, bpll and so on. >>> You don't need to make the separate pll table. Just add new entries >>> to exynos5420_pll2550x_24mhz_tbl table. >> OK, I will extend the exynos5420_pll2550x_24mhz_tbl table. >> >> In v4 patch set, it will be fixed. >> >> Regards, >> Lukasz >>> >>>> } >>>> >>>> samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), >>>> >>> > > > > -- > Best Regards, > Chanwoo Choi > Samsung Electronics > >