From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: Dmitry Osipenko <digetx@gmail.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <tglx@linutronix.de>,
<jason@lakedaemon.net>, <marc.zyngier@arm.com>,
<linus.walleij@linaro.org>, <stefan@agner.ch>,
<mark.rutland@arm.com>
Cc: <pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,
<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,
<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,
<josephl@nvidia.com>, <talho@nvidia.com>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<mperttunen@nvidia.com>, <spatra@nvidia.com>,
<robh+dt@kernel.org>, <devicetree@vger.kernel.org>,
<rjw@rjwysocki.net>, <viresh.kumar@linaro.org>,
<linux-pm@vger.kernel.org>
Subject: Re: [PATCH v8 19/21] soc/tegra: pmc: Configure deep sleep control settings
Date: Fri, 9 Aug 2019 10:24:27 -0700 [thread overview]
Message-ID: <60ea494a-9960-b7fc-3afb-8c17feec9fda@nvidia.com> (raw)
In-Reply-To: <275f3685-bc53-38ff-c778-cf2ea588e5a5@nvidia.com>
On 8/9/19 9:23 AM, Sowjanya Komatineni wrote:
>
> On 8/9/19 6:23 AM, Dmitry Osipenko wrote:
>> 09.08.2019 2:46, Sowjanya Komatineni пишет:
>>> Tegra210 and prior Tegra chips have deep sleep entry and wakeup related
>>> timings which are platform specific that should be configured before
>>> entering into deep sleep.
>>>
>>> Below are the timing specific configurations for deep sleep entry and
>>> wakeup.
>>> - Core rail power-on stabilization timer
>>> - OSC clock stabilization timer after SOC rail power is stabilized.
>>> - Core power off time is the minimum wake delay to keep the system
>>> in deep sleep state irrespective of any quick wake event.
>>>
>>> These values depends on the discharge time of regulators and turn OFF
>>> time of the PMIC to allow the complete system to finish entering into
>>> deep sleep state.
>>>
>>> These values vary based on the platform design and are specified
>>> through the device tree.
>>>
>>> This patch has implementation to configure these timings which are must
>>> to have for proper deep sleep and wakeup operations.
>>>
>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>> ---
>>> drivers/soc/tegra/pmc.c | 13 ++++++++++++-
>>> 1 file changed, 12 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>> index e013ada7e4e9..9a78d8417367 100644
>>> --- a/drivers/soc/tegra/pmc.c
>>> +++ b/drivers/soc/tegra/pmc.c
>>> @@ -88,6 +88,8 @@
>>> #define PMC_CPUPWRGOOD_TIMER 0xc8
>>> #define PMC_CPUPWROFF_TIMER 0xcc
>>> +#define PMC_COREPWRGOOD_TIMER 0x3c
>>> +#define PMC_COREPWROFF_TIMER 0xe0
>>> #define PMC_PWR_DET_VALUE 0xe4
>>> @@ -2277,7 +2279,7 @@ static const struct tegra_pmc_regs
>>> tegra20_pmc_regs = {
>>> static void tegra20_pmc_init(struct tegra_pmc *pmc)
>>> {
>>> - u32 value;
>>> + u32 value, osc, pmu, off;
>>> /* Always enable CPU power request */
>>> value = tegra_pmc_readl(pmc, PMC_CNTRL);
>>> @@ -2303,6 +2305,15 @@ static void tegra20_pmc_init(struct tegra_pmc
>>> *pmc)
>>> value = tegra_pmc_readl(pmc, PMC_CNTRL);
>>> value |= PMC_CNTRL_SYSCLK_OE;
>>> tegra_pmc_writel(pmc, value, PMC_CNTRL);
>>> +
>>> + osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
>>> + pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
>>> + off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
>>> + if (osc && pmu)
>>> + tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
>>> + PMC_COREPWRGOOD_TIMER);
>>> + if (off)
>>> + tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
>> The osc/pmu/off values are undefined if they are not defined in
>> device-tree. I suppose this
>> need to be corrected in tegra_pmc_parse_dt() if the values really
>> matter even if LP0 suspend
>> isn't supported in device-tree.
>>
>> And I'm also not sure what's wrong with setting 0 for the timers.
>>
> These settings are for SC7 only and will not have any impact in normal
> state.
POR value for these timing registers is not 0 and has default timings
based on chip design and on top of that based on platform HW components
charge/discharge timings there's a need to increase these timings so
support for programming these thru DT is needed and these values have
effect only in LP0.
>>> }
>>> static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
>>>
next prev parent reply other threads:[~2019-08-09 17:24 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-08 23:46 [PATCH v8 00/21] SC7 entry and exit support for Tegra210 Sowjanya Komatineni
2019-08-08 23:46 ` [PATCH v8 01/21] pinctrl: tegra: Fix write barrier placement in pmx_writel Sowjanya Komatineni
2019-08-09 11:38 ` Dmitry Osipenko
2019-08-12 9:20 ` Thierry Reding
2019-08-14 8:32 ` Linus Walleij
2019-08-08 23:46 ` [PATCH v8 02/21] pinctrl: tegra: Add write barrier after all pinctrl register writes Sowjanya Komatineni
2019-08-09 11:39 ` Dmitry Osipenko
2019-08-12 9:20 ` Thierry Reding
2019-08-14 8:33 ` Linus Walleij
2019-08-08 23:46 ` [PATCH v8 03/21] clk: tegra: divider: Save and restore divider rate Sowjanya Komatineni
2019-08-12 9:21 ` Thierry Reding
2019-08-08 23:46 ` [PATCH v8 04/21] clk: tegra: pllout: Save and restore pllout context Sowjanya Komatineni
2019-08-11 18:04 ` Dmitry Osipenko
2019-08-08 23:46 ` [PATCH v8 05/21] clk: tegra: pll: Save and restore pll context Sowjanya Komatineni
2019-08-09 11:33 ` Dmitry Osipenko
2019-08-09 17:39 ` Sowjanya Komatineni
2019-08-09 17:50 ` Dmitry Osipenko
2019-08-09 18:50 ` Sowjanya Komatineni
2019-08-11 17:24 ` Dmitry Osipenko
2019-08-09 12:46 ` Dmitry Osipenko
2019-08-08 23:46 ` [PATCH v8 06/21] clk: tegra: Support for OSC context save and restore Sowjanya Komatineni
2019-08-08 23:46 ` [PATCH v8 07/21] clk: Add API to get index of the clock parent Sowjanya Komatineni
2019-08-09 11:49 ` Dmitry Osipenko
2019-08-12 9:47 ` Thierry Reding
2019-08-08 23:46 ` [PATCH v8 08/21] clk: tegra: periph: Add restore_context support Sowjanya Komatineni
2019-08-09 11:55 ` Dmitry Osipenko
2019-08-09 12:20 ` Dmitry Osipenko
2019-08-09 16:55 ` Sowjanya Komatineni
2019-08-12 9:50 ` Thierry Reding
2019-08-08 23:46 ` [PATCH v8 09/21] clk: tegra: clk-super: Fix to enable PLLP branches to CPU Sowjanya Komatineni
2019-08-09 12:11 ` Dmitry Osipenko
2019-08-12 9:53 ` Thierry Reding
2019-08-08 23:46 ` [PATCH v8 10/21] clk: tegra: clk-super: Add restore-context support Sowjanya Komatineni
2019-08-09 12:17 ` Dmitry Osipenko
2019-08-09 17:08 ` Sowjanya Komatineni
2019-08-11 17:29 ` Dmitry Osipenko
2019-08-12 9:55 ` Thierry Reding
2019-08-08 23:46 ` [PATCH v8 11/21] clk: tegra: clk-dfll: Add suspend and resume support Sowjanya Komatineni
2019-08-09 12:23 ` Dmitry Osipenko
2019-08-09 16:39 ` Sowjanya Komatineni
2019-08-09 18:00 ` Dmitry Osipenko
2019-08-09 18:33 ` Sowjanya Komatineni
2019-08-09 18:52 ` Dmitry Osipenko
2019-08-12 10:01 ` Thierry Reding
2019-08-08 23:46 ` [PATCH v8 12/21] cpufreq: tegra124: " Sowjanya Komatineni
2019-08-12 10:07 ` Thierry Reding
2019-08-08 23:46 ` [PATCH v8 13/21] clk: tegra210: Use fence_udelay during PLLU init Sowjanya Komatineni
2019-08-11 18:02 ` Dmitry Osipenko
2019-08-11 19:16 ` Sowjanya Komatineni
2019-08-08 23:46 ` [PATCH v8 14/21] clk: tegra210: Add suspend and resume support Sowjanya Komatineni
2019-08-09 13:56 ` Dmitry Osipenko
2019-08-09 16:19 ` Sowjanya Komatineni
2019-08-09 18:18 ` Dmitry Osipenko
[not found] ` <cbe94f84-a17b-7e1a-811d-89db571784e1@nvidia.com>
2019-08-11 17:39 ` Dmitry Osipenko
2019-08-11 19:15 ` Sowjanya Komatineni
2019-08-12 16:25 ` Dmitry Osipenko
2019-08-12 17:28 ` Sowjanya Komatineni
2019-08-12 18:19 ` Dmitry Osipenko
2019-08-12 19:03 ` Sowjanya Komatineni
2019-08-12 20:28 ` Dmitry Osipenko
2019-08-12 10:17 ` Thierry Reding
2019-08-08 23:46 ` [PATCH v8 15/21] soc/tegra: pmc: Allow to support more tegras wake Sowjanya Komatineni
2019-08-11 17:52 ` Dmitry Osipenko
2019-08-08 23:46 ` [PATCH v8 16/21] soc/tegra: pmc: Add pmc wake support for tegra210 Sowjanya Komatineni
2019-08-09 13:28 ` Dmitry Osipenko
2019-08-08 23:46 ` [PATCH v8 17/21] arm64: tegra: Enable wake from deep sleep on RTC alarm Sowjanya Komatineni
2019-08-08 23:46 ` [PATCH v8 18/21] soc/tegra: pmc: Configure core power request polarity Sowjanya Komatineni
2019-08-09 13:13 ` Dmitry Osipenko
2019-08-08 23:46 ` [PATCH v8 19/21] soc/tegra: pmc: Configure deep sleep control settings Sowjanya Komatineni
2019-08-09 13:23 ` Dmitry Osipenko
2019-08-09 16:23 ` Sowjanya Komatineni
2019-08-09 17:24 ` Sowjanya Komatineni [this message]
2019-08-09 18:22 ` Dmitry Osipenko
2019-08-08 23:46 ` [PATCH v8 20/21] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Sowjanya Komatineni
2019-08-08 23:47 ` [PATCH v8 21/21] arm64: dts: tegra210-p3450: Jetson Nano " Sowjanya Komatineni
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