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From: Joseph Lo <josephl@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Rob Herring <robh@kernel.org>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	Jonathan Hunter <jonathanh@nvidia.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<linux-tegra@vger.kernel.org>, <linux-clk@vger.kernel.org>,
	<devicetree@vger.kernel.org>
Subject: Re: [PATCH V4 01/20] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator
Date: Fri, 11 Jan 2019 16:14:31 +0800
Message-ID: <74087bd9-1cc4-9897-9ded-81eaa9ca434b@nvidia.com> (raw)
In-Reply-To: <142f619f-9939-0d87-9fe7-2e72efa027a0@nvidia.com>

On 1/8/19 8:35 AM, Joseph Lo wrote:
> On 1/4/19 11:06 AM, Joseph Lo wrote:
>> From: Peter De Schrijver <pdeschrijver@nvidia.com>
>>
>> Add new properties to configure the DFLL PWM regulator support.
>>
>> Cc: devicetree@vger.kernel.org
>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>> Signed-off-by: Joseph Lo <josephl@nvidia.com>
>> Acked-by: Jon Hunter <jonathanh@nvidia.com>
>> ---
>> *V4:
>>   - s/nvidia,pwm-period/nvidia,pwm-period-nanoseconds/
>> *V3:
>>   - no change
>> *V2:
>>   - update the binding strings and descriptions for
>>   nvidia,pwm-tristate-microvolts
>>   nvidia,pwm-min-microvolts
>>   nvidia,pwm-voltage-step-microvolts
>> ---
> 
> Hi Rob,
> 
> Could you help me to review this patch again?

Gentle ping.

Thanks,
Joseph

> 
> Thanks,
> Joseph
> 
>>   .../bindings/clock/nvidia,tegra124-dfll.txt   | 79 ++++++++++++++++++-
>>   1 file changed, 77 insertions(+), 2 deletions(-)
>>
>> diff --git 
>> a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt 
>> b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
>> index dff236f524a7..5558bb5fcf2c 100644
>> --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
>> +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
>> @@ -8,7 +8,6 @@ the fast CPU cluster. It consists of a free-running 
>> voltage controlled
>>   oscillator connected to the CPU voltage rail (VDD_CPU), and a closed 
>> loop
>>   control module that will automatically adjust the VDD_CPU voltage by
>>   communicating with an off-chip PMIC either via an I2C bus or via PWM 
>> signals.
>> -Currently only the I2C mode is supported by these bindings.
>>   Required properties:
>>   - compatible : should be "nvidia,tegra124-dfll"
>> @@ -45,10 +44,31 @@ Required properties for the control loop parameters:
>>   Optional properties for the control loop parameters:
>>   - nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE 
>> in the TRM.
>> +Optional properties for mode selection:
>> +- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C.
>> +
>>   Required properties for I2C mode:
>>   - nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.
>> -Example:
>> +Required properties for PWM mode:
>> +- nvidia,pwm-period-nanoseconds: period of PWM square wave in 
>> nanoseconds.
>> +- nvidia,pwm-tristate-microvolts: Regulator voltage in micro volts 
>> when PWM
>> +  control is disabled and the PWM output is tristated. Note that this 
>> voltage is
>> +  configured in hardware, typically via a resistor divider.
>> +- nvidia,pwm-min-microvolts: Regulator voltage in micro volts when 
>> PWM control
>> +  is enabled and PWM output is low. Hence, this is the minimum output 
>> voltage
>> +  that the regulator supports when PWM control is enabled.
>> +- nvidia,pwm-voltage-step-microvolts: Voltage increase in micro volts
>> +  corresponding to a 1/33th increase in duty cycle. Eg the voltage 
>> for 2/33th
>> +  duty cycle would be: nvidia,pwm-min-microvolts +
>> +  nvidia,pwm-voltage-step-microvolts * 2.
>> +- pinctrl-0: I/O pad configuration when PWM control is enabled.
>> +- pinctrl-1: I/O pad configuration when PWM control is disabled.
>> +- pinctrl-names: must include the following entries:
>> +  - dvfs_pwm_enable: I/O pad configuration when PWM control is enabled.
>> +  - dvfs_pwm_disable: I/O pad configuration when PWM control is 
>> disabled.
>> +
>> +Example for I2C:
>>   clock@70110000 {
>>           compatible = "nvidia,tegra124-dfll";
>> @@ -76,3 +96,58 @@ clock@70110000 {
>>           nvidia,i2c-fs-rate = <400000>;
>>   };
>> +
>> +Example for PWM:
>> +
>> +clock@70110000 {
>> +    compatible = "nvidia,tegra124-dfll";
>> +    reg = <0 0x70110000 0 0x100>, /* DFLL control */
>> +          <0 0x70110000 0 0x100>, /* I2C output control */
>> +          <0 0x70110100 0 0x100>, /* Integrated I2C controller */
>> +          <0 0x70110200 0 0x100>; /* Look-up table RAM */
>> +    interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>> +    clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
>> +             <&tegra_car TEGRA210_CLK_DFLL_REF>,
>> +         <&tegra_car TEGRA124_CLK_I2C5>;;
>> +    clock-names = "soc", "ref", "i2c";
>> +    resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
>> +    reset-names = "dvco";
>> +    #clock-cells = <0>;
>> +    clock-output-names = "dfllCPU_out";
>> +
>> +    nvidia,sample-rate = <25000>;
>> +    nvidia,droop-ctrl = <0x00000f00>;
>> +    nvidia,force-mode = <1>;
>> +    nvidia,cf = <6>;
>> +    nvidia,ci = <0>;
>> +    nvidia,cg = <2>;
>> +
>> +    nvidia,pwm-min-microvolts = <708000>; /* 708mV */
>> +    nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
>> +    nvidia,pwm-to-pmic;
>> +    nvidia,pwm-tristate-microvolts = <1000000>;
>> +    nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */
>> +
>> +    pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
>> +    pinctrl-0 = <&dvfs_pwm_active_state>;
>> +    pinctrl-1 = <&dvfs_pwm_inactive_state>;
>> +};
>> +
>> +/* pinmux nodes added for completeness. Binding doc can be found in:
>> + * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
>> + */
>> +
>> +pinmux: pinmux@700008d4 {
>> +    dvfs_pwm_active_state: dvfs_pwm_active {
>> +        dvfs_pwm_pbb1 {
>> +            nvidia,pins = "dvfs_pwm_pbb1";
>> +            nvidia,tristate = <TEGRA_PIN_DISABLE>;
>> +        };
>> +    };
>> +    dvfs_pwm_inactive_state: dvfs_pwm_inactive {
>> +        dvfs_pwm_pbb1 {
>> +            nvidia,pins = "dvfs_pwm_pbb1";
>> +            nvidia,tristate = <TEGRA_PIN_ENABLE>;
>> +        };
>> +    };
>> +};
>>

  reply index

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-04  3:06 [PATCH V4 00/20] Tegra210 DFLL support Joseph Lo
2019-01-04  3:06 ` [PATCH V4 01/20] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Joseph Lo
2019-01-08  0:35   ` Joseph Lo
2019-01-11  8:14     ` Joseph Lo [this message]
2019-01-11 19:32   ` Rob Herring
2019-01-04  3:06 ` [PATCH V4 02/20] dt-bindings: clock: tegra124-dfll: add Tegra210 support Joseph Lo
2019-01-04  3:06 ` [PATCH V4 03/20] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Joseph Lo
2019-01-04  3:06 ` [PATCH V4 04/20] dt-bindings: cpufreq: tegra124: remove cpu_lp clock " Joseph Lo
2019-01-04  3:06 ` [PATCH V4 05/20] clk: tegra: dfll: registration for multiple SoCs Joseph Lo
2019-01-04  3:06 ` [PATCH V4 06/20] clk: tegra: dfll: CVB calculation alignment with the regulator Joseph Lo
2019-01-04  3:06 ` [PATCH V4 07/20] clk: tegra: dfll: support PWM regulator control Joseph Lo
2019-01-04  3:06 ` [PATCH V4 08/20] clk: tegra: dfll: round down voltages based on alignment Joseph Lo
2019-01-04  3:06 ` [PATCH V4 09/20] clk: tegra: dfll: add CVB tables for Tegra210 Joseph Lo
2019-01-04  3:06 ` [PATCH V4 10/20] clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 Joseph Lo
2019-01-08  0:33   ` Joseph Lo
2019-01-09 18:39   ` Stephen Boyd
2019-01-04  3:06 ` [PATCH V4 11/20] cpufreq: tegra124: do not handle the CPU rail Joseph Lo
2019-01-04  3:06 ` [PATCH V4 12/20] cpufreq: tegra124: extend to support Tegra210 Joseph Lo
2019-01-04  3:06 ` [PATCH V4 13/20] cpufreq: dt-platdev: add Tegra210 to blacklist Joseph Lo
2019-01-04  3:06 ` [PATCH V4 14/20] arm64: dts: tegra210: add DFLL clock Joseph Lo
2019-01-04  3:06 ` [PATCH V4 15/20] arm64: dts: tegra210: add CPU clocks Joseph Lo
2019-01-04  3:06 ` [PATCH V4 16/20] arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support Joseph Lo
2019-01-04  3:06 ` [PATCH V4 17/20] arm64: dts: tegra210-p2371-2180: enable DFLL clock Joseph Lo
2019-01-04  3:07 ` [PATCH V4 18/20] arm64: dts: tegra210-smaug: add CPU power rail regulator Joseph Lo
2019-01-04  3:07 ` [PATCH V4 19/20] arm64: dts: tegra210-smaug: enable DFLL clock Joseph Lo
2019-01-04  3:07 ` [PATCH V4 20/20] arm64: defconfig: Enable MAX8973 regulator Joseph Lo
2019-01-25 13:46 ` [PATCH V4 00/20] Tegra210 DFLL support Thierry Reding
2019-01-28  1:43   ` Joseph Lo
2019-01-28  7:54     ` Thierry Reding
2019-02-01  2:49       ` Joseph Lo
2019-02-05 22:27         ` Stephen Boyd

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