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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 2gk0H2JIo5UNB7mcOIeCku8GrOOeFlXRMdWvBXiBb8oiswogjViXnoYav2HEsD6BEfVWWKX6IVdARVXzAMIqQCPqVCUU76128+gpPxuKKQ4cCrS85nRR5ySP+ug5ccGj9UGZ3/AEuNsWlXxumlvLVjymngzcCfrUfvG+k42MD/oMQnSGszIvNjq9/6Z0EJertmgIMt0wjd9ARYWnATVljtt7QFx4zqekwzncBqw2cCpWE35jxjB7JX4HRf/giKEDurEabsRFYV0VUaV/RaHZeHGsNJKERdHMDfEa0SJfZcTB0eKG7cnLL92MHux3mY5FVRZUH0tHYkFMvYuGy0vZDXgnNmTvhTXhxas1ycQZo8sf/ITI9YncjUyrVRpLr8LqucaUsatklpWJIq8+t3KWosBqIC2NcM4g98jtDeDyF40= Content-Type: text/plain; charset="us-ascii" Content-ID: <477B960D9DD82945B0702742F249D8A4@eurprd04.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6b7aa3fc-6dc7-4d73-c9c3-08d752300ad4 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Oct 2019 11:57:39.1602 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 8d8NKBsX1soKolYdxtke+UY42/CrXBbSv9rWZ+zNHN/HWQUjcQFPW+i7jSUpN9Ulxrm/p1ZA9tQorzIUEujOeA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB7136 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On imx8mm there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each with their own gate. Only one of these gates (the one "dividing" by one) is currently defined and it's incorrectly set as the parent of all the fixed-factor dividers. Add the other 8 gates to the clock tree between sys_pll1/2_bypass and the fixed dividers. Signed-off-by: Leonard Crestez --- drivers/clk/imx/clk-imx8mm.c | 57 ++++++++++++++++-------- include/dt-bindings/clock/imx8mm-clock.h | 19 +++++++- 2 files changed, 56 insertions(+), 20 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 04876ec66127..bbd212eb904e 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -358,33 +358,52 @@ static int imx8mm_clocks_probe(struct platform_device= *pdev) clks[IMX8MM_VIDEO_PLL1_OUT] =3D imx_clk_gate("video_pll1_out", "video_pll= 1_bypass", base + 0x28, 13); clks[IMX8MM_DRAM_PLL_OUT] =3D imx_clk_gate("dram_pll_out", "dram_pll_bypa= ss", base + 0x50, 13); clks[IMX8MM_GPU_PLL_OUT] =3D imx_clk_gate("gpu_pll_out", "gpu_pll_bypass"= , base + 0x64, 11); clks[IMX8MM_VPU_PLL_OUT] =3D imx_clk_gate("vpu_pll_out", "vpu_pll_bypass"= , base + 0x74, 11); clks[IMX8MM_ARM_PLL_OUT] =3D imx_clk_gate("arm_pll_out", "arm_pll_bypass"= , base + 0x84, 11); - clks[IMX8MM_SYS_PLL1_OUT] =3D imx_clk_gate("sys_pll1_out", "sys_pll1_bypa= ss", base + 0x94, 11); - clks[IMX8MM_SYS_PLL2_OUT] =3D imx_clk_gate("sys_pll2_out", "sys_pll2_bypa= ss", base + 0x104, 11); clks[IMX8MM_SYS_PLL3_OUT] =3D imx_clk_gate("sys_pll3_out", "sys_pll3_bypa= ss", base + 0x114, 11); =20 - /* SYS PLL fixed output */ - clks[IMX8MM_SYS_PLL1_40M] =3D imx_clk_fixed_factor("sys_pll1_40m", "sys_p= ll1_out", 1, 20); - clks[IMX8MM_SYS_PLL1_80M] =3D imx_clk_fixed_factor("sys_pll1_80m", "sys_p= ll1_out", 1, 10); - clks[IMX8MM_SYS_PLL1_100M] =3D imx_clk_fixed_factor("sys_pll1_100m", "sys= _pll1_out", 1, 8); - clks[IMX8MM_SYS_PLL1_133M] =3D imx_clk_fixed_factor("sys_pll1_133m", "sys= _pll1_out", 1, 6); - clks[IMX8MM_SYS_PLL1_160M] =3D imx_clk_fixed_factor("sys_pll1_160m", "sys= _pll1_out", 1, 5); - clks[IMX8MM_SYS_PLL1_200M] =3D imx_clk_fixed_factor("sys_pll1_200m", "sys= _pll1_out", 1, 4); - clks[IMX8MM_SYS_PLL1_266M] =3D imx_clk_fixed_factor("sys_pll1_266m", "sys= _pll1_out", 1, 3); - clks[IMX8MM_SYS_PLL1_400M] =3D imx_clk_fixed_factor("sys_pll1_400m", "sys= _pll1_out", 1, 2); + /* SYS PLL1 fixed output */ + clks[IMX8MM_SYS_PLL1_40M_CG] =3D imx_clk_gate("sys_pll1_40m_cg", "sys_pll= 1_bypass", base + 0x94, 27); + clks[IMX8MM_SYS_PLL1_80M_CG] =3D imx_clk_gate("sys_pll1_80m_cg", "sys_pll= 1_bypass", base + 0x94, 25); + clks[IMX8MM_SYS_PLL1_100M_CG] =3D imx_clk_gate("sys_pll1_100m_cg", "sys_p= ll1_bypass", base + 0x94, 23); + clks[IMX8MM_SYS_PLL1_133M_CG] =3D imx_clk_gate("sys_pll1_133m_cg", "sys_p= ll1_bypass", base + 0x94, 21); + clks[IMX8MM_SYS_PLL1_160M_CG] =3D imx_clk_gate("sys_pll1_160m_cg", "sys_p= ll1_bypass", base + 0x94, 19); + clks[IMX8MM_SYS_PLL1_200M_CG] =3D imx_clk_gate("sys_pll1_200m_cg", "sys_p= ll1_bypass", base + 0x94, 17); + clks[IMX8MM_SYS_PLL1_266M_CG] =3D imx_clk_gate("sys_pll1_266m_cg", "sys_p= ll1_bypass", base + 0x94, 15); + clks[IMX8MM_SYS_PLL1_400M_CG] =3D imx_clk_gate("sys_pll1_400m_cg", "sys_p= ll1_bypass", base + 0x94, 13); + clks[IMX8MM_SYS_PLL1_OUT] =3D imx_clk_gate("sys_pll1_out", "sys_pll1_bypa= ss", base + 0x94, 11); + + clks[IMX8MM_SYS_PLL1_40M] =3D imx_clk_fixed_factor("sys_pll1_40m", "sys_p= ll1_40m_cg", 1, 20); + clks[IMX8MM_SYS_PLL1_80M] =3D imx_clk_fixed_factor("sys_pll1_80m", "sys_p= ll1_80m_cg", 1, 10); + clks[IMX8MM_SYS_PLL1_100M] =3D imx_clk_fixed_factor("sys_pll1_100m", "sys= _pll1_100m_cg", 1, 8); + clks[IMX8MM_SYS_PLL1_133M] =3D imx_clk_fixed_factor("sys_pll1_133m", "sys= _pll1_133m_cg", 1, 6); + clks[IMX8MM_SYS_PLL1_160M] =3D imx_clk_fixed_factor("sys_pll1_160m", "sys= _pll1_160m_cg", 1, 5); + clks[IMX8MM_SYS_PLL1_200M] =3D imx_clk_fixed_factor("sys_pll1_200m", "sys= _pll1_200m_cg", 1, 4); + clks[IMX8MM_SYS_PLL1_266M] =3D imx_clk_fixed_factor("sys_pll1_266m", "sys= _pll1_266m_cg", 1, 3); + clks[IMX8MM_SYS_PLL1_400M] =3D imx_clk_fixed_factor("sys_pll1_400m", "sys= _pll1_400m_cg", 1, 2); clks[IMX8MM_SYS_PLL1_800M] =3D imx_clk_fixed_factor("sys_pll1_800m", "sys= _pll1_out", 1, 1); =20 - clks[IMX8MM_SYS_PLL2_50M] =3D imx_clk_fixed_factor("sys_pll2_50m", "sys_p= ll2_out", 1, 20); - clks[IMX8MM_SYS_PLL2_100M] =3D imx_clk_fixed_factor("sys_pll2_100m", "sys= _pll2_out", 1, 10); - clks[IMX8MM_SYS_PLL2_125M] =3D imx_clk_fixed_factor("sys_pll2_125m", "sys= _pll2_out", 1, 8); - clks[IMX8MM_SYS_PLL2_166M] =3D imx_clk_fixed_factor("sys_pll2_166m", "sys= _pll2_out", 1, 6); - clks[IMX8MM_SYS_PLL2_200M] =3D imx_clk_fixed_factor("sys_pll2_200m", "sys= _pll2_out", 1, 5); - clks[IMX8MM_SYS_PLL2_250M] =3D imx_clk_fixed_factor("sys_pll2_250m", "sys= _pll2_out", 1, 4); - clks[IMX8MM_SYS_PLL2_333M] =3D imx_clk_fixed_factor("sys_pll2_333m", "sys= _pll2_out", 1, 3); - clks[IMX8MM_SYS_PLL2_500M] =3D imx_clk_fixed_factor("sys_pll2_500m", "sys= _pll2_out", 1, 2); + /* SYS PLL2 fixed output */ + clks[IMX8MM_SYS_PLL2_50M_CG] =3D imx_clk_gate("sys_pll2_50m_cg", "sys_pll= 2_bypass", base + 0x104, 27); + clks[IMX8MM_SYS_PLL2_100M_CG] =3D imx_clk_gate("sys_pll2_100m_cg", "sys_p= ll2_bypass", base + 0x104, 25); + clks[IMX8MM_SYS_PLL2_125M_CG] =3D imx_clk_gate("sys_pll2_125m_cg", "sys_p= ll2_bypass", base + 0x104, 23); + clks[IMX8MM_SYS_PLL2_166M_CG] =3D imx_clk_gate("sys_pll2_166m_cg", "sys_p= ll2_bypass", base + 0x104, 21); + clks[IMX8MM_SYS_PLL2_200M_CG] =3D imx_clk_gate("sys_pll2_200m_cg", "sys_p= ll2_bypass", base + 0x104, 19); + clks[IMX8MM_SYS_PLL2_250M_CG] =3D imx_clk_gate("sys_pll2_250m_cg", "sys_p= ll2_bypass", base + 0x104, 17); + clks[IMX8MM_SYS_PLL2_333M_CG] =3D imx_clk_gate("sys_pll2_333m_cg", "sys_p= ll2_bypass", base + 0x104, 15); + clks[IMX8MM_SYS_PLL2_500M_CG] =3D imx_clk_gate("sys_pll2_500m_cg", "sys_p= ll2_bypass", base + 0x104, 13); + clks[IMX8MM_SYS_PLL2_OUT] =3D imx_clk_gate("sys_pll2_out", "sys_pll2_bypa= ss", base + 0x104, 11); + + clks[IMX8MM_SYS_PLL2_50M] =3D imx_clk_fixed_factor("sys_pll2_50m", "sys_p= ll2_50m_cg", 1, 20); + clks[IMX8MM_SYS_PLL2_100M] =3D imx_clk_fixed_factor("sys_pll2_100m", "sys= _pll2_100m_cg", 1, 10); + clks[IMX8MM_SYS_PLL2_125M] =3D imx_clk_fixed_factor("sys_pll2_125m", "sys= _pll2_125m_cg", 1, 8); + clks[IMX8MM_SYS_PLL2_166M] =3D imx_clk_fixed_factor("sys_pll2_166m", "sys= _pll2_166m_cg", 1, 6); + clks[IMX8MM_SYS_PLL2_200M] =3D imx_clk_fixed_factor("sys_pll2_200m", "sys= _pll2_200m_cg", 1, 5); + clks[IMX8MM_SYS_PLL2_250M] =3D imx_clk_fixed_factor("sys_pll2_250m", "sys= _pll2_250m_cg", 1, 4); + clks[IMX8MM_SYS_PLL2_333M] =3D imx_clk_fixed_factor("sys_pll2_333m", "sys= _pll2_333m_cg", 1, 3); + clks[IMX8MM_SYS_PLL2_500M] =3D imx_clk_fixed_factor("sys_pll2_500m", "sys= _pll2_500m_cg", 1, 2); clks[IMX8MM_SYS_PLL2_1000M] =3D imx_clk_fixed_factor("sys_pll2_1000m", "s= ys_pll2_out", 1, 1); =20 np =3D dev->of_node; base =3D devm_platform_ioremap_resource(pdev, 0); if (WARN_ON(IS_ERR(base))) diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings= /clock/imx8mm-clock.h index 07e6c686f3ef..edeece2289f0 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -246,8 +246,25 @@ #define IMX8MM_CLK_GPIO5_ROOT 227 =20 #define IMX8MM_CLK_SNVS_ROOT 228 #define IMX8MM_CLK_GIC 229 =20 -#define IMX8MM_CLK_END 230 +#define IMX8MM_SYS_PLL1_40M_CG 230 +#define IMX8MM_SYS_PLL1_80M_CG 231 +#define IMX8MM_SYS_PLL1_100M_CG 232 +#define IMX8MM_SYS_PLL1_133M_CG 233 +#define IMX8MM_SYS_PLL1_160M_CG 234 +#define IMX8MM_SYS_PLL1_200M_CG 235 +#define IMX8MM_SYS_PLL1_266M_CG 236 +#define IMX8MM_SYS_PLL1_400M_CG 237 +#define IMX8MM_SYS_PLL2_50M_CG 238 +#define IMX8MM_SYS_PLL2_100M_CG 239 +#define IMX8MM_SYS_PLL2_125M_CG 240 +#define IMX8MM_SYS_PLL2_166M_CG 241 +#define IMX8MM_SYS_PLL2_200M_CG 242 +#define IMX8MM_SYS_PLL2_250M_CG 243 +#define IMX8MM_SYS_PLL2_333M_CG 244 +#define IMX8MM_SYS_PLL2_500M_CG 245 + +#define IMX8MM_CLK_END 246 =20 #endif --=20 2.17.1