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From: Randy Dunlap <rdunlap@infradead.org>
To: Anson Huang <Anson.Huang@nxp.com>,
	mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org,
	s.hauer@pengutronix.de, kernel@pengutronix.de,
	festevam@gmail.com, aisheng.dong@nxp.com, arnd@arndb.de,
	peng.fan@nxp.com, abel.vesa@nxp.com, fugang.duan@nxp.com,
	daniel.baluta@nxp.com, yuehaibing@huawei.com,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Cc: Linux-imx@nxp.com
Subject: Re: [PATCH V7 1/6] clk: imx6sl: Use BIT(x) to avoid shifting signed 32-bit value by 31 bits
Date: Wed, 29 Jul 2020 08:49:21 -0700
Message-ID: <86ae1d4e-27c9-07e4-73be-37d490cb0063@infradead.org> (raw)
In-Reply-To: <1596034117-24246-2-git-send-email-Anson.Huang@nxp.com>

On 7/29/20 7:48 AM, Anson Huang wrote:
> Use readl_relaxed() instead of __raw_readl(), and use BIT(x)
> instead of (1 << X) to fix below build warning reported by kernel
> test robot:
> 
> drivers/clk/imx/clk-imx6sl.c:149:49: warning: Shifting signed 32-bit
> value by 31 bits is undefined behaviour [shiftTooManyBitsSigned]
>      while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK))
> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> Reported-by: kernel test robot <lkp@intel.com>
> ---
> Changes since V6:
> 	- improve the subject.
> ---
>  drivers/clk/imx/clk-imx6sl.c | 15 ++++++++-------
>  1 file changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c
> index 0f647d1..e69dba1 100644
> --- a/drivers/clk/imx/clk-imx6sl.c
> +++ b/drivers/clk/imx/clk-imx6sl.c
> @@ -3,6 +3,7 @@
>   * Copyright 2013-2014 Freescale Semiconductor, Inc.
>   */
>  
> +#include <linux/bitfield.h>

Hi,
I think you want
#include <linux/bits.h>

for BIT() usage.

>  #include <linux/clk.h>
>  #include <linux/clkdev.h>
>  #include <linux/err.h>
> @@ -14,19 +15,19 @@
>  #include "clk.h"
>  
>  #define CCSR			0xc
> -#define BM_CCSR_PLL1_SW_CLK_SEL	(1 << 2)
> +#define BM_CCSR_PLL1_SW_CLK_SEL	BIT(2)
>  #define CACRR			0x10
>  #define CDHIPR			0x48
> -#define BM_CDHIPR_ARM_PODF_BUSY	(1 << 16)
> +#define BM_CDHIPR_ARM_PODF_BUSY	BIT(16)
>  #define ARM_WAIT_DIV_396M	2
>  #define ARM_WAIT_DIV_792M	4
>  #define ARM_WAIT_DIV_996M	6
>  
>  #define PLL_ARM			0x0
> -#define BM_PLL_ARM_DIV_SELECT	(0x7f << 0)
> -#define BM_PLL_ARM_POWERDOWN	(1 << 12)
> -#define BM_PLL_ARM_ENABLE	(1 << 13)
> -#define BM_PLL_ARM_LOCK		(1 << 31)
> +#define BM_PLL_ARM_DIV_SELECT	0x7f
> +#define BM_PLL_ARM_POWERDOWN	BIT(12)
> +#define BM_PLL_ARM_ENABLE	BIT(13)
> +#define BM_PLL_ARM_LOCK		BIT(31)
>  #define PLL_ARM_DIV_792M	66
>  
>  static const char *step_sels[]		= { "osc", "pll2_pfd2", };


thanks.
-- 
~Randy


  reply index

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-29 14:48 [PATCH V7 0/6] Support building i.MX ARMv8 platforms clock driver as module Anson Huang
2020-07-29 14:48 ` [PATCH V7 1/6] clk: imx6sl: Use BIT(x) to avoid shifting signed 32-bit value by 31 bits Anson Huang
2020-07-29 15:49   ` Randy Dunlap [this message]
2020-07-29 23:51     ` Anson Huang
2020-07-30  0:30       ` Randy Dunlap
2020-07-30  1:14         ` Anson Huang
2020-07-30  7:25           ` Arnd Bergmann
2020-07-29 14:48 ` [PATCH V7 2/6] clk: composite: Export clk_hw_register_composite() Anson Huang
2020-07-29 14:48 ` [PATCH V7 3/6] clk: imx: Support building i.MX common clock driver as module Anson Huang
2020-07-29 14:48 ` [PATCH V7 4/6] clk: imx: Add clock configuration for ARMv7 platforms Anson Huang
2020-07-29 14:48 ` [PATCH V7 5/6] clk: imx8m: Support module build Anson Huang
2020-07-29 14:48 ` [PATCH V7 6/6] clk: imx8qxp: Support building i.MX8QXP clock driver as module Anson Huang
2020-07-29 15:26 ` [PATCH V7 0/6] Support building i.MX ARMv8 platforms " Shawn Guo
2020-08-01  0:04   ` Stephen Boyd

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