From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: Dmitry Osipenko <digetx@gmail.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <tglx@linutronix.de>,
<jason@lakedaemon.net>, <marc.zyngier@arm.com>,
<linus.walleij@linaro.org>, <stefan@agner.ch>,
<mark.rutland@arm.com>
Cc: <pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,
<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,
<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,
<josephl@nvidia.com>, <talho@nvidia.com>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<mperttunen@nvidia.com>, <spatra@nvidia.com>,
<robh+dt@kernel.org>, <devicetree@vger.kernel.org>
Subject: Re: [PATCH V6 14/21] clk: tegra210: Add suspend and resume support
Date: Sun, 21 Jul 2019 15:45:07 -0700 [thread overview]
Message-ID: <88da46d2-b90d-f57e-7611-b8653b56bdf6@nvidia.com> (raw)
In-Reply-To: <e683b417-66fb-38dc-c16b-dab616583a88@gmail.com>
On 7/21/19 2:38 PM, Dmitry Osipenko wrote:
> 21.07.2019 22:40, Sowjanya Komatineni пишет:
>> This patch adds support for clk: tegra210: suspend-resume.
>>
>> All the CAR controller settings are lost on suspend when core
>> power goes off.
>>
>> This patch has implementation for saving and restoring all PLLs
>> and clocks context during system suspend and resume to have the
>> clocks back to same state for normal operation.
>>
>> Acked-by: Thierry Reding <treding@nvidia.com>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>> drivers/clk/tegra/clk-tegra210.c | 68 ++++++++++++++++++++++++++++++++++++++--
>> drivers/clk/tegra/clk.c | 14 +++++++++
>> drivers/clk/tegra/clk.h | 1 +
>> 3 files changed, 80 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>> index 55a88c0824a5..68271873acc1 100644
>> --- a/drivers/clk/tegra/clk-tegra210.c
>> +++ b/drivers/clk/tegra/clk-tegra210.c
>> @@ -9,6 +9,7 @@
>> #include <linux/clkdev.h>
>> #include <linux/of.h>
>> #include <linux/of_address.h>
>> +#include <linux/syscore_ops.h>
>> #include <linux/delay.h>
>> #include <linux/export.h>
>> #include <linux/mutex.h>
>> @@ -220,11 +221,15 @@
>> #define CLK_M_DIVISOR_SHIFT 2
>> #define CLK_M_DIVISOR_MASK 0x3
>>
>> +#define CLK_MASK_ARM 0x44
>> +#define MISC_CLK_ENB 0x48
>> +
>> #define RST_DFLL_DVCO 0x2f4
>> #define DVFS_DFLL_RESET_SHIFT 0
>>
>> #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
>> #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
>> +#define CPU_SOFTRST_CTRL 0x380
>>
>> #define LVL2_CLK_GATE_OVRA 0xf8
>> #define LVL2_CLK_GATE_OVRC 0x3a0
>> @@ -2825,6 +2830,7 @@ static int tegra210_enable_pllu(void)
>> struct tegra_clk_pll_freq_table *fentry;
>> struct tegra_clk_pll pllu;
>> u32 reg;
>> + int ret;
>>
>> for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) {
>> if (fentry->input_rate == pll_ref_freq)
>> @@ -2853,9 +2859,8 @@ static int tegra210_enable_pllu(void)
>> reg |= PLL_ENABLE;
>> writel(reg, clk_base + PLLU_BASE);
>>
>> - readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg,
>> - reg & PLL_BASE_LOCK, 2, 1000);
>> - if (!(reg & PLL_BASE_LOCK)) {
>> + ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK);
>> + if (ret) {
> Why this is needed? Was there a bug?
>
during resume pllu init is needed and to use same terga210_init_pllu,
poll_timeout_atomic can't be used as its ony for atomic context.
So changed to use wait_for_mask which should work in both cases.
>> pr_err("Timed out waiting for PLL_U to lock\n");
>> return -ETIMEDOUT;
>> }
>> @@ -3288,6 +3293,56 @@ static void tegra210_disable_cpu_clock(u32 cpu)
>> }
>>
>> #ifdef CONFIG_PM_SLEEP
>> +#define car_readl(_base, _off) readl_relaxed(clk_base + (_base) + ((_off) * 4))
>> +#define car_writel(_val, _base, _off) \
>> + writel_relaxed(_val, clk_base + (_base) + ((_off) * 4))
>> +
>> +static u32 spare_reg_ctx, misc_clk_enb_ctx, clk_msk_arm_ctx;
>> +static u32 cpu_softrst_ctx[3];
>> +
>> +static int tegra210_clk_suspend(void)
>> +{
>> + unsigned int i;
>> +
>> + clk_save_context();
>> +
>> + /*
>> + * save the bootloader configured clock registers SPARE_REG0,
>> + * MISC_CLK_ENB, CLK_MASK_ARM, CPU_SOFTRST_CTRL
> Nit: Start all multi-line comments with a capital letter and put dot in
> the end of sentence.
>
>> + */
>> + spare_reg_ctx = readl_relaxed(clk_base + SPARE_REG0);
>> + misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB);
>> + clk_msk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM);
>> +
>> + for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)
>> + cpu_softrst_ctx[i] = car_readl(CPU_SOFTRST_CTRL, i);
>> +
>> + return 0;
>> +}
>> +
>> +static void tegra210_clk_resume(void)
>> +{
>> + unsigned int i;
>> +
>> + tegra_clk_osc_resume(clk_base);
>> +
>> + /*
>> + * restore the bootloader configured clock registers SPARE_REG0,
>> + * MISC_CLK_ENB, CLK_MASK_ARM, CPU_SOFTRST_CTRL from saved context.
> Same here.
>
>> + */
>> + writel_relaxed(spare_reg_ctx, clk_base + SPARE_REG0);
>> + writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB);
>> + writel_relaxed(clk_msk_arm_ctx, clk_base + CLK_MASK_ARM);
>> +
>> + for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)
>> + car_writel(cpu_softrst_ctx[i], CPU_SOFTRST_CTRL, i);
>> +
>> + fence_udelay(5, clk_base);
>> +
>> + tegra210_init_pllu();
>> + clk_restore_context();
>> +}
>> +
>> static void tegra210_cpu_clock_suspend(void)
>> {
>> /* switch coresite to clk_m, save off original source */
>> @@ -3303,6 +3358,11 @@ static void tegra210_cpu_clock_resume(void)
>> }
>> #endif
>>
>> +static struct syscore_ops tegra_clk_syscore_ops = {
>> + .suspend = tegra210_clk_suspend,
>> + .resume = tegra210_clk_resume,
>> +};
>> +
>> static struct tegra_cpu_car_ops tegra210_cpu_car_ops = {
>> .wait_for_reset = tegra210_wait_cpu_in_reset,
>> .disable_clock = tegra210_disable_cpu_clock,
>> @@ -3587,5 +3647,7 @@ static void __init tegra210_clock_init(struct device_node *np)
>> tegra210_mbist_clk_init();
>>
>> tegra_cpu_car_ops = &tegra210_cpu_car_ops;
>> +
>> + register_syscore_ops(&tegra_clk_syscore_ops);
>> }
>> CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init);
>> diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
>> index 573e3c967ae1..eb08047fd02f 100644
>> --- a/drivers/clk/tegra/clk.c
>> +++ b/drivers/clk/tegra/clk.c
>> @@ -23,6 +23,7 @@
>> #define CLK_OUT_ENB_W 0x364
>> #define CLK_OUT_ENB_X 0x280
>> #define CLK_OUT_ENB_Y 0x298
>> +#define CLK_ENB_PLLP_OUT_CPU BIT(31)
>> #define CLK_OUT_ENB_SET_L 0x320
>> #define CLK_OUT_ENB_CLR_L 0x324
>> #define CLK_OUT_ENB_SET_H 0x328
>> @@ -199,6 +200,19 @@ const struct tegra_clk_periph_regs *get_reg_bank(int clkid)
>> }
>> }
>>
>> +void tegra_clk_set_pllp_out_cpu(bool enable)
>> +{
>> + u32 val;
>> +
>> + val = readl_relaxed(clk_base + CLK_OUT_ENB_Y);
>> + if (enable)
>> + val |= CLK_ENB_PLLP_OUT_CPU;
>> + else
>> + val &= ~CLK_ENB_PLLP_OUT_CPU;
>> +
>> + writel_relaxed(val, clk_base + CLK_OUT_ENB_Y);
>> +}
>> +
>> struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)
>> {
>> clk_base = regs;
>> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
>> index 562a3ee2d537..0ffa763c755b 100644
>> --- a/drivers/clk/tegra/clk.h
>> +++ b/drivers/clk/tegra/clk.h
>> @@ -863,6 +863,7 @@ int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
>> u8 frac_width, u8 flags);
>> void tegra_clk_sync_state_pll(struct clk_hw *hw);
>> void tegra_clk_osc_resume(void __iomem *clk_base);
>> +void tegra_clk_set_pllp_out_cpu(bool enable);
>>
>> /* Combined read fence with delay */
>> #define fence_udelay(delay, reg) \
>>
next prev parent reply other threads:[~2019-07-21 22:44 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-21 19:40 [PATCH V6 00/21] SC7 entry and exit support for Tegra210 Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 01/21] irqchip: tegra: Do not disable COP IRQ during suspend Sowjanya Komatineni
2019-07-21 20:24 ` Marc Zyngier
2019-07-22 9:54 ` Dmitry Osipenko
2019-07-22 10:13 ` Marc Zyngier
2019-07-22 10:57 ` Dmitry Osipenko
2019-07-22 16:21 ` Sowjanya Komatineni
2019-07-22 18:38 ` Marc Zyngier
2019-07-22 23:35 ` Dmitry Osipenko
2019-07-24 23:09 ` Sowjanya Komatineni
2019-07-26 4:48 ` Dmitry Osipenko
2019-07-25 9:55 ` Peter De Schrijver
2019-07-25 10:05 ` Dmitry Osipenko
2019-07-25 10:33 ` Peter De Schrijver
2019-07-25 10:38 ` Peter De Schrijver
2019-07-25 10:59 ` Dmitry Osipenko
2019-08-02 13:05 ` Peter De Schrijver
2019-08-02 17:35 ` Dmitry Osipenko
2019-07-21 19:40 ` [PATCH V6 02/21] pinctrl: tegra: Add suspend and resume support Sowjanya Komatineni
2019-07-21 22:03 ` Dmitry Osipenko
2019-07-21 22:09 ` Dmitry Osipenko
2019-07-21 22:48 ` Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 03/21] pinctrl: tegra210: Add Tegra210 pinctrl pm ops Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 04/21] clk: tegra: Save and restore divider rate Sowjanya Komatineni
2019-07-21 22:14 ` Dmitry Osipenko
2019-07-21 19:40 ` [PATCH V6 05/21] clk: tegra: pllout: Save and restore pllout context Sowjanya Komatineni
2019-07-21 22:18 ` Dmitry Osipenko
2019-07-21 19:40 ` [PATCH V6 06/21] clk: tegra: pll: Save and restore pll context Sowjanya Komatineni
2019-07-21 21:44 ` Dmitry Osipenko
2019-07-21 22:47 ` Sowjanya Komatineni
2019-07-21 22:21 ` Dmitry Osipenko
2019-07-22 3:22 ` Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 07/21] clk: tegra: Support for OSC context save and restore Sowjanya Komatineni
2019-07-22 10:12 ` Dmitry Osipenko
2019-07-21 19:40 ` [PATCH V6 08/21] clk: tegra: clk-periph: Add save and restore support Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 09/21] clk: tegra: clk-super: Fix to enable PLLP branches to CPU Sowjanya Komatineni
2019-07-21 21:16 ` Dmitry Osipenko
2019-07-21 22:39 ` Sowjanya Komatineni
2019-07-22 3:17 ` Sowjanya Komatineni
2019-07-22 6:32 ` Dmitry Osipenko
2019-07-22 7:12 ` Sowjanya Komatineni
2019-07-22 7:17 ` Dmitry Osipenko
2019-07-22 7:24 ` Sowjanya Komatineni
2019-07-22 7:30 ` Dmitry Osipenko
2019-07-22 7:36 ` Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 10/21] clk: tegra: clk-super: Add save and restore support Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 11/21] clk: tegra: clk-dfll: Add suspend and resume support Sowjanya Komatineni
2019-07-21 21:32 ` Dmitry Osipenko
2019-07-21 22:42 ` Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 12/21] cpufreq: tegra124: " Sowjanya Komatineni
2019-07-21 21:04 ` Dmitry Osipenko
2019-07-21 19:40 ` [PATCH V6 13/21] clk: tegra210: Use fence_udelay during PLLU init Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 14/21] clk: tegra210: Add suspend and resume support Sowjanya Komatineni
2019-07-21 21:38 ` Dmitry Osipenko
2019-07-21 22:45 ` Sowjanya Komatineni [this message]
2019-07-22 6:10 ` Dmitry Osipenko
2019-07-22 6:52 ` Sowjanya Komatineni
2019-07-22 7:09 ` Dmitry Osipenko
2019-07-22 7:12 ` Dmitry Osipenko
2019-08-02 17:51 ` Stephen Boyd
2019-08-02 20:39 ` Sowjanya Komatineni
2019-08-07 21:22 ` Stephen Boyd
2019-07-21 19:40 ` [PATCH V6 15/21] soc/tegra: pmc: Allow to support more tegras wake Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 16/21] soc/tegra: pmc: Add pmc wake support for tegra210 Sowjanya Komatineni
2019-07-23 0:58 ` Dmitry Osipenko
2019-07-23 1:08 ` Dmitry Osipenko
2019-07-23 1:41 ` Dmitry Osipenko
2019-07-23 1:52 ` Dmitry Osipenko
2019-07-23 2:10 ` Dmitry Osipenko
[not found] ` <71a88a9c-a542-557a-0eaa-3c90112dee0e@nvidia.com>
2019-07-23 3:03 ` Dmitry Osipenko
2019-07-23 3:09 ` Sowjanya Komatineni
2019-07-23 3:25 ` Dmitry Osipenko
2019-07-23 3:31 ` Sowjanya Komatineni
2019-07-23 3:43 ` Dmitry Osipenko
2019-07-23 14:27 ` Dmitry Osipenko
2019-07-23 23:39 ` Sowjanya Komatineni
2019-07-24 9:31 ` Dmitry Osipenko
2019-07-21 19:40 ` [PATCH V6 17/21] arm64: tegra: Enable wake from deep sleep on RTC alarm Sowjanya Komatineni
2019-07-26 6:30 ` Dmitry Osipenko
2019-07-21 19:40 ` [PATCH V6 18/21] soc/tegra: pmc: Configure core power request polarity Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 19/21] soc/tegra: pmc: Configure deep sleep control settings Sowjanya Komatineni
2019-07-21 19:40 ` [PATCH V6 20/21] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Sowjanya Komatineni
2019-07-21 19:41 ` [PATCH V6 21/21] arm64: dts: tegra210-p3450: Jetson nano " Sowjanya Komatineni
2019-07-21 22:25 ` Dmitry Osipenko
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=88da46d2-b90d-f57e-7611-b8653b56bdf6@nvidia.com \
--to=skomatineni@nvidia.com \
--cc=devicetree@vger.kernel.org \
--cc=digetx@gmail.com \
--cc=jason@lakedaemon.net \
--cc=jckuo@nvidia.com \
--cc=jonathanh@nvidia.com \
--cc=josephl@nvidia.com \
--cc=linus.walleij@linaro.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=marc.zyngier@arm.com \
--cc=mark.rutland@arm.com \
--cc=mperttunen@nvidia.com \
--cc=pdeschrijver@nvidia.com \
--cc=pgaikwad@nvidia.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=spatra@nvidia.com \
--cc=stefan@agner.ch \
--cc=talho@nvidia.com \
--cc=tglx@linutronix.de \
--cc=thierry.reding@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).