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From: Michael Walle <michael@walle.cc>
To: Rob Herring <robh@kernel.org>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>
Subject: Re: [PATCH 1/2] dt-bindings: clock: document the fsl-sai driver
Date: Tue, 10 Dec 2019 00:36:34 +0100	[thread overview]
Message-ID: <95bfe66ecf86baf70818d287900d87f1@walle.cc> (raw)
In-Reply-To: <e28881421014b641c37fc2cacdf6c43e@walle.cc>

Am 2019-12-06 02:23, schrieb Michael Walle:
> Am 2019-12-05 16:16, schrieb Rob Herring:
>> On Sat, Nov 23, 2019 at 12:56:21AM +0100, Michael Walle wrote:
>>> Signed-off-by: Michael Walle <michael@walle.cc>
>>> ---
>>>  .../bindings/clock/fsl,sai-clock.yaml         | 48 
>>> +++++++++++++++++++
>>>  1 file changed, 48 insertions(+)
>>>  create mode 100644 
>>> Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
>>> 
>>> diff --git 
>>> a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml 
>>> b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
>>> new file mode 100644
>>> index 000000000000..7116c8bc24d3
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
>>> @@ -0,0 +1,48 @@
>>> +# SPDX-License-Identifier: GPL-2.0
>> 
>> Dual license new bindings please: (GPL-2.0-only OR BSD-2-Clause)
> 
> sure.
> 
>> 
>>> +%YAML 1.2
>>> +---
>>> +$id: 
>>> http://devicetree.org/schemas/bindings/clock/fsl,sai-clock.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Freescale SAI bitclock-as-a-clock binding
>>> +
>>> +maintainers:
>>> +  - Michael Walle <michael@walle.cc>
>>> +
>>> +description: |
>>> +  It is possible to use the BCLK pin of a SAI module as a generic 
>>> clock
>>> +  output. Some SoC are very constrained in their pin multiplexer
>>> +  configuration. Eg. pins can only be changed groups. For example, 
>>> on the
>>> +  LS1028A SoC you can only enable SAIs in pairs. If you use only one 
>>> SAI,
>>> +  the second pins are wasted. Using this binding it is possible to 
>>> use the
>>> +  clock of the second SAI as a MCLK clock for an audio codec, for 
>>> example.
>>> +
>>> +  This is a composite of a gated clock and a divider clock.
>>> +
>>> +properties:
>>> +  compatible:
>>> +    const: fsl,vf610-sai-clock
>>> +
>>> +  reg:
>>> +    maxItems: 1
>>> +
>>> +  clocks:
>>> +    maxItems: 1
>>> +
>>> +  '#clock-cells':
>>> +    const: 0
>>> +
>>> +required:
>>> +  - compatible
>>> +  - reg
>>> +  - clocks
>>> +  - '#clock-cells'
>>> +
>> 
>> Add:
>> 
>> additionalProperties: false
> 
> ok.
> 
>>> +examples:
>>> +  - |
>>> +    mclk: clock-mclk@f130080 {
>>> +        compatible = "fsl,vf610-sai-clock";
>>> +        reg = <0x0 0xf130080 0x0 0x80>;
>> 
>> Examples are built now and this will fail because the default
>> #address-cells and #size-cells are 1.
> 
> Mh, I've run the make dt_binding_check on this. It wasn't flagged,
> but I guess thats because its interpreted as two resources.
> 
> I haven't found anything how you can change the default. Or do you
> mean I should change the example to just use one address cell and
> one size cell? But then how would that work for examples (on other
> bindings) where there should be size-cells = <0> for example.

I guess I've answered that question myself, see the v2 patch series.
https://lore.kernel.org/lkml/20191209233305.18619-1-michael@walle.cc/

Thanks for the review.

> 
>> 
>>> +        #clock-cells = <0>;
>>> +        clocks = <&parentclk>;
>>> +    };
>>> --
>>> 2.20.1
>>> 

      reply	other threads:[~2019-12-09 23:36 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-22 23:56 Michael Walle
2019-11-22 23:56 ` [PATCH 2/2] clk: fsl-sai: new driver Michael Walle
2019-12-02 21:46   ` Michael Walle
2019-12-05 15:16 ` [PATCH 1/2] dt-bindings: clock: document the fsl-sai driver Rob Herring
2019-12-06  1:23   ` Michael Walle
2019-12-09 23:36     ` Michael Walle [this message]

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