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* [PATCH v3 0/3] Mark clocks as critical for MT6797
@ 2019-01-08 12:12 matthias.bgg
  2019-01-08 12:12 ` [PATCH v3 1/3] clk: mediatek: Add MUX_FLAGS macro matthias.bgg
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: matthias.bgg @ 2019-01-08 12:12 UTC (permalink / raw)
  To: mturquette, sboyd, kevin-cw.chen, mars.cheng
  Cc: sean.wang, matthias.bgg, jasu, linux-clk, linux-kernel,
	linux-arm-kernel, linux-mediatek, Matthias Brugger

From: Matthias Brugger <mbrugger@suse.com>

Jasper send this series some month ago. As there was no reaction from
his side, I'll do a friendly take-over.
I tested the patches on my Helios X20 boards and they fix the issue.
I didn't add a Tested-by tag as I added my Signed-off-by.

Changes since v2 (https://patchwork.kernel.org/patch/10686759/):
- axi_sel is not needed, drop CLK_IS_CRITICAL for it.
- update commit message
- add Acked-by from Mars

Changes since v1:
- add a fixes tag.

---

Currently, DRAM-related clocks and the axi_sel MUX are not marked with
CLK_IS_CRITICAL for MT6797. This causes memory corruption when the
system is booted without clk_ignore_unused.

This patchset

1. Makes it possible to mark outputs of MUXes as critical by introducing
   a new macro, MUX_FLAGS,
2. Makes it possible to mark gates as critical by adding flags to
   mtk_gate, and
3. Marks axi_sel, ddrphycfg_sel, infra_dramc_f26m and infra_dramc_b_f26m
   as critical.

The addition of flags to mtk_gate also exists in the patch series "Add
basic and clock support for Mediatek MT8183 SoC" [1].  The type of
flags is unsigned int in that series, but the real type is unsigned
long, so my patch differs from that patch.

[1] https://patchwork.kernel.org/patch/10549953/

Jasper Mattsson (3):
  clk: mediatek: Add MUX_FLAGS macro
  clk: mediatek: Add flags to mtk_gate
  clk: mediatek: Mark bus and DRAM related clocks as critical

 drivers/clk/mediatek/clk-gate.c   |  4 ++-
 drivers/clk/mediatek/clk-gate.h   |  3 +-
 drivers/clk/mediatek/clk-mt6797.c | 60 ++++++++++++++++++-------------
 drivers/clk/mediatek/clk-mtk.c    |  2 +-
 drivers/clk/mediatek/clk-mtk.h    |  9 +++--
 5 files changed, 48 insertions(+), 30 deletions(-)

-- 
2.20.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v3 1/3] clk: mediatek: Add MUX_FLAGS macro
  2019-01-08 12:12 [PATCH v3 0/3] Mark clocks as critical for MT6797 matthias.bgg
@ 2019-01-08 12:12 ` matthias.bgg
  2019-01-08 12:12 ` [PATCH v3 2/3] clk: mediatek: Add flags to mtk_gate matthias.bgg
  2019-01-08 12:12 ` [PATCH v3 3/3] clk: mediatek: Mark bus and DRAM related clocks as critical matthias.bgg
  2 siblings, 0 replies; 6+ messages in thread
From: matthias.bgg @ 2019-01-08 12:12 UTC (permalink / raw)
  To: mturquette, sboyd, kevin-cw.chen, mars.cheng
  Cc: sean.wang, matthias.bgg, jasu, linux-clk, linux-kernel,
	linux-arm-kernel, linux-mediatek

From: Jasper Mattsson <jasu@njomotys.info>

This is required to mark outputs of certain MUXes as CLK_IS_CRITICAL.

Signed-off-by: Jasper Mattsson <jasu@njomotys.info>
Acked-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
 drivers/clk/mediatek/clk-mtk.h | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index f83c2bbb677e..daab6ee94788 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -111,7 +111,11 @@ struct mtk_composite {
 	MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width,	\
 		_gate, CLK_SET_RATE_PARENT)
 
-#define MUX(_id, _name, _parents, _reg, _shift, _width) {		\
+#define MUX(_id, _name, _parents, _reg, _shift, _width)			\
+	MUX_FLAGS(_id, _name, _parents, _reg,				\
+		  _shift, _width, CLK_SET_RATE_PARENT)
+
+#define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) {	\
 		.id = _id,						\
 		.name = _name,						\
 		.mux_reg = _reg,					\
@@ -121,7 +125,7 @@ struct mtk_composite {
 		.divider_shift = -1,					\
 		.parent_names = _parents,				\
 		.num_parents = ARRAY_SIZE(_parents),			\
-		.flags = CLK_SET_RATE_PARENT,				\
+		.flags = _flags,				\
 	}
 
 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg,	\
-- 
2.20.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v3 2/3] clk: mediatek: Add flags to mtk_gate
  2019-01-08 12:12 [PATCH v3 0/3] Mark clocks as critical for MT6797 matthias.bgg
  2019-01-08 12:12 ` [PATCH v3 1/3] clk: mediatek: Add MUX_FLAGS macro matthias.bgg
@ 2019-01-08 12:12 ` matthias.bgg
  2019-01-08 12:12 ` [PATCH v3 3/3] clk: mediatek: Mark bus and DRAM related clocks as critical matthias.bgg
  2 siblings, 0 replies; 6+ messages in thread
From: matthias.bgg @ 2019-01-08 12:12 UTC (permalink / raw)
  To: mturquette, sboyd, kevin-cw.chen, mars.cheng
  Cc: sean.wang, matthias.bgg, jasu, linux-clk, linux-kernel,
	linux-arm-kernel, linux-mediatek

From: Jasper Mattsson <jasu@njomotys.info>

This is required to mark gates as CLK_IS_CRITICAL.

Signed-off-by: Jasper Mattsson <jasu@njomotys.info>
Acked-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
 drivers/clk/mediatek/clk-gate.c | 4 +++-
 drivers/clk/mediatek/clk-gate.h | 3 ++-
 drivers/clk/mediatek/clk-mtk.c  | 2 +-
 drivers/clk/mediatek/clk-mtk.h  | 1 +
 4 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index 934bf0e45e26..9628d4e7690b 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -157,7 +157,8 @@ struct clk *mtk_clk_register_gate(
 		int clr_ofs,
 		int sta_ofs,
 		u8 bit,
-		const struct clk_ops *ops)
+		const struct clk_ops *ops,
+		unsigned long flags)
 {
 	struct mtk_clk_gate *cg;
 	struct clk *clk;
@@ -172,6 +173,7 @@ struct clk *mtk_clk_register_gate(
 	init.parent_names = parent_name ? &parent_name : NULL;
 	init.num_parents = parent_name ? 1 : 0;
 	init.ops = ops;
+	init.flags = flags;
 
 	cg->regmap = regmap;
 	cg->set_ofs = set_ofs;
diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
index 72ef89b3ad7b..9f766dfe1d57 100644
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -47,6 +47,7 @@ struct clk *mtk_clk_register_gate(
 		int clr_ofs,
 		int sta_ofs,
 		u8 bit,
-		const struct clk_ops *ops);
+		const struct clk_ops *ops,
+		unsigned long flags);
 
 #endif /* __DRV_CLK_GATE_H */
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 9c0ae4278a94..ef410413bb0b 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -130,7 +130,7 @@ int mtk_clk_register_gates(struct device_node *node,
 				gate->regs->set_ofs,
 				gate->regs->clr_ofs,
 				gate->regs->sta_ofs,
-				gate->shift, gate->ops);
+				gate->shift, gate->ops, gate->flags);
 
 		if (IS_ERR(clk)) {
 			pr_err("Failed to register clk %s: %ld\n",
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index daab6ee94788..987ff2855249 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -162,6 +162,7 @@ struct mtk_gate {
 	const struct mtk_gate_regs *regs;
 	int shift;
 	const struct clk_ops *ops;
+	unsigned long flags;
 };
 
 int mtk_clk_register_gates(struct device_node *node,
-- 
2.20.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v3 3/3] clk: mediatek: Mark bus and DRAM related clocks as critical
  2019-01-08 12:12 [PATCH v3 0/3] Mark clocks as critical for MT6797 matthias.bgg
  2019-01-08 12:12 ` [PATCH v3 1/3] clk: mediatek: Add MUX_FLAGS macro matthias.bgg
  2019-01-08 12:12 ` [PATCH v3 2/3] clk: mediatek: Add flags to mtk_gate matthias.bgg
@ 2019-01-08 12:12 ` matthias.bgg
  2019-02-08 13:39   ` Matthias Brugger
  2 siblings, 1 reply; 6+ messages in thread
From: matthias.bgg @ 2019-01-08 12:12 UTC (permalink / raw)
  To: mturquette, sboyd, kevin-cw.chen, mars.cheng
  Cc: sean.wang, matthias.bgg, jasu, linux-clk, linux-kernel,
	linux-arm-kernel, linux-mediatek

From: Jasper Mattsson <jasu@njomotys.info>

Currently, DRAM-related clocks are not marked with CLK_IS_CRITICAL
for MT6797. This causes memory corruption when the system is
booted without clk_ignore_unused.
This patch marks MUX ddrphycfg_sel as well as gates infra_dramc_f26m
and infra_dramc_b_f26m as CLK_IS_CRITICAL.

Signed-off-by: Jasper Mattsson <jasu@njomotys.info>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
 drivers/clk/mediatek/clk-mt6797.c | 60 ++++++++++++++++++-------------
 1 file changed, 35 insertions(+), 25 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c
index 5702bc974ed9..a6e5408e0388 100644
--- a/drivers/clk/mediatek/clk-mt6797.c
+++ b/drivers/clk/mediatek/clk-mt6797.c
@@ -331,8 +331,8 @@ static const struct mtk_composite top_muxes[] = {
 	    ulposc_axi_ck_mux_parents, 0x0040, 2, 1),
 	MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
 	    0x0040, 0, 2),
-	MUX(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
-	    0x0040, 16, 2),
+	MUX_FLAGS(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
+		  0x0040, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
 	MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
 	    0x0040, 24, 2),
 	MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
@@ -424,31 +424,39 @@ static const struct mtk_gate_regs infra2_cg_regs = {
 	.sta_ofs = 0x00b0,
 };
 
-#define GATE_ICG0(_id, _name, _parent, _shift) {	\
-	.id = _id,					\
-	.name = _name,					\
-	.parent_name = _parent,				\
-	.regs = &infra0_cg_regs,			\
-	.shift = _shift,				\
-	.ops = &mtk_clk_gate_ops_setclr,		\
+#define GATE_ICG0(_id, _name, _parent, _shift) {		\
+	.id = _id,						\
+	.name = _name,						\
+	.parent_name = _parent,					\
+	.regs = &infra0_cg_regs,				\
+	.shift = _shift,					\
+	.ops = &mtk_clk_gate_ops_setclr,			\
 }
 
-#define GATE_ICG1(_id, _name, _parent, _shift) {	\
-	.id = _id,					\
-	.name = _name,					\
-	.parent_name = _parent,				\
-	.regs = &infra1_cg_regs,			\
-	.shift = _shift,				\
-	.ops = &mtk_clk_gate_ops_setclr,		\
+#define GATE_ICG1(_id, _name, _parent, _shift)			\
+	GATE_ICG1_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) {	\
+	.id = _id,						\
+	.name = _name,						\
+	.parent_name = _parent,					\
+	.regs = &infra1_cg_regs,				\
+	.shift = _shift,					\
+	.ops = &mtk_clk_gate_ops_setclr,			\
+	.flags = _flags,					\
 }
 
-#define GATE_ICG2(_id, _name, _parent, _shift) {	\
-	.id = _id,					\
-	.name = _name,					\
-	.parent_name = _parent,				\
-	.regs = &infra2_cg_regs,			\
-	.shift = _shift,				\
-	.ops = &mtk_clk_gate_ops_setclr,		\
+#define GATE_ICG2(_id, _name, _parent, _shift)			\
+	GATE_ICG2_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) {	\
+	.id = _id,						\
+	.name = _name,						\
+	.parent_name = _parent,					\
+	.regs = &infra2_cg_regs,				\
+	.shift = _shift,					\
+	.ops = &mtk_clk_gate_ops_setclr,			\
+	.flags = _flags,					\
 }
 
 static const struct mtk_gate infra_clks[] = {
@@ -505,7 +513,8 @@ static const struct mtk_gate infra_clks[] = {
 	GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
 	GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
 	GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
-	GATE_ICG1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31),
+	GATE_ICG1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
+			"clk26m", 31, CLK_IS_CRITICAL),
 	GATE_ICG2(CLK_INFRA_I2C4, "infra_i2c4", "axi_sel", 0),
 	GATE_ICG2(CLK_INFRA_I2C_APPM, "infra_i2c_appm", "axi_sel", 1),
 	GATE_ICG2(CLK_INFRA_I2C_GPUPM, "infra_i2c_gpupm", "axi_sel", 2),
@@ -516,7 +525,8 @@ static const struct mtk_gate infra_clks[] = {
 	GATE_ICG2(CLK_INFRA_I2C5, "infra_i2c5", "axi_sel", 7),
 	GATE_ICG2(CLK_INFRA_SYS_CIRQ, "infra_sys_cirq", "axi_sel", 8),
 	GATE_ICG2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 10),
-	GATE_ICG2(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m", "clk26m", 11),
+	GATE_ICG2_FLAGS(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m",
+			"clk26m", 11, CLK_IS_CRITICAL),
 	GATE_ICG2(CLK_INFRA_ANC_MD32, "infra_anc_md32", "anc_md32_sel", 12),
 	GATE_ICG2(CLK_INFRA_ANC_MD32_32K, "infra_anc_md32_32k", "clk26m", 13),
 	GATE_ICG2(CLK_INFRA_DVFS_SPM1, "infra_dvfs_spm1", "axi_sel", 15),
-- 
2.20.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH v3 3/3] clk: mediatek: Mark bus and DRAM related clocks as critical
  2019-01-08 12:12 ` [PATCH v3 3/3] clk: mediatek: Mark bus and DRAM related clocks as critical matthias.bgg
@ 2019-02-08 13:39   ` Matthias Brugger
  2019-02-13 17:09     ` Stephen Boyd
  0 siblings, 1 reply; 6+ messages in thread
From: Matthias Brugger @ 2019-02-08 13:39 UTC (permalink / raw)
  To: matthias.bgg, mturquette, sboyd, kevin-cw.chen, mars.cheng
  Cc: sean.wang, jasu, linux-clk, linux-kernel, linux-arm-kernel,
	linux-mediatek

Steven, Mike, any comments on that?

On 08/01/2019 13:12, matthias.bgg@kernel.org wrote:
> From: Jasper Mattsson <jasu@njomotys.info>
> 
> Currently, DRAM-related clocks are not marked with CLK_IS_CRITICAL
> for MT6797. This causes memory corruption when the system is
> booted without clk_ignore_unused.
> This patch marks MUX ddrphycfg_sel as well as gates infra_dramc_f26m
> and infra_dramc_b_f26m as CLK_IS_CRITICAL.
> 
> Signed-off-by: Jasper Mattsson <jasu@njomotys.info>
> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
>  drivers/clk/mediatek/clk-mt6797.c | 60 ++++++++++++++++++-------------
>  1 file changed, 35 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c
> index 5702bc974ed9..a6e5408e0388 100644
> --- a/drivers/clk/mediatek/clk-mt6797.c
> +++ b/drivers/clk/mediatek/clk-mt6797.c
> @@ -331,8 +331,8 @@ static const struct mtk_composite top_muxes[] = {
>  	    ulposc_axi_ck_mux_parents, 0x0040, 2, 1),
>  	MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
>  	    0x0040, 0, 2),
> -	MUX(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
> -	    0x0040, 16, 2),
> +	MUX_FLAGS(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
> +		  0x0040, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
>  	MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
>  	    0x0040, 24, 2),
>  	MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
> @@ -424,31 +424,39 @@ static const struct mtk_gate_regs infra2_cg_regs = {
>  	.sta_ofs = 0x00b0,
>  };
>  
> -#define GATE_ICG0(_id, _name, _parent, _shift) {	\
> -	.id = _id,					\
> -	.name = _name,					\
> -	.parent_name = _parent,				\
> -	.regs = &infra0_cg_regs,			\
> -	.shift = _shift,				\
> -	.ops = &mtk_clk_gate_ops_setclr,		\
> +#define GATE_ICG0(_id, _name, _parent, _shift) {		\
> +	.id = _id,						\
> +	.name = _name,						\
> +	.parent_name = _parent,					\
> +	.regs = &infra0_cg_regs,				\
> +	.shift = _shift,					\
> +	.ops = &mtk_clk_gate_ops_setclr,			\
>  }
>  
> -#define GATE_ICG1(_id, _name, _parent, _shift) {	\
> -	.id = _id,					\
> -	.name = _name,					\
> -	.parent_name = _parent,				\
> -	.regs = &infra1_cg_regs,			\
> -	.shift = _shift,				\
> -	.ops = &mtk_clk_gate_ops_setclr,		\
> +#define GATE_ICG1(_id, _name, _parent, _shift)			\
> +	GATE_ICG1_FLAGS(_id, _name, _parent, _shift, 0)
> +
> +#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) {	\
> +	.id = _id,						\
> +	.name = _name,						\
> +	.parent_name = _parent,					\
> +	.regs = &infra1_cg_regs,				\
> +	.shift = _shift,					\
> +	.ops = &mtk_clk_gate_ops_setclr,			\
> +	.flags = _flags,					\
>  }
>  
> -#define GATE_ICG2(_id, _name, _parent, _shift) {	\
> -	.id = _id,					\
> -	.name = _name,					\
> -	.parent_name = _parent,				\
> -	.regs = &infra2_cg_regs,			\
> -	.shift = _shift,				\
> -	.ops = &mtk_clk_gate_ops_setclr,		\
> +#define GATE_ICG2(_id, _name, _parent, _shift)			\
> +	GATE_ICG2_FLAGS(_id, _name, _parent, _shift, 0)
> +
> +#define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) {	\
> +	.id = _id,						\
> +	.name = _name,						\
> +	.parent_name = _parent,					\
> +	.regs = &infra2_cg_regs,				\
> +	.shift = _shift,					\
> +	.ops = &mtk_clk_gate_ops_setclr,			\
> +	.flags = _flags,					\
>  }
>  
>  static const struct mtk_gate infra_clks[] = {
> @@ -505,7 +513,8 @@ static const struct mtk_gate infra_clks[] = {
>  	GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
>  	GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
>  	GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
> -	GATE_ICG1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31),
> +	GATE_ICG1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
> +			"clk26m", 31, CLK_IS_CRITICAL),
>  	GATE_ICG2(CLK_INFRA_I2C4, "infra_i2c4", "axi_sel", 0),
>  	GATE_ICG2(CLK_INFRA_I2C_APPM, "infra_i2c_appm", "axi_sel", 1),
>  	GATE_ICG2(CLK_INFRA_I2C_GPUPM, "infra_i2c_gpupm", "axi_sel", 2),
> @@ -516,7 +525,8 @@ static const struct mtk_gate infra_clks[] = {
>  	GATE_ICG2(CLK_INFRA_I2C5, "infra_i2c5", "axi_sel", 7),
>  	GATE_ICG2(CLK_INFRA_SYS_CIRQ, "infra_sys_cirq", "axi_sel", 8),
>  	GATE_ICG2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 10),
> -	GATE_ICG2(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m", "clk26m", 11),
> +	GATE_ICG2_FLAGS(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m",
> +			"clk26m", 11, CLK_IS_CRITICAL),
>  	GATE_ICG2(CLK_INFRA_ANC_MD32, "infra_anc_md32", "anc_md32_sel", 12),
>  	GATE_ICG2(CLK_INFRA_ANC_MD32_32K, "infra_anc_md32_32k", "clk26m", 13),
>  	GATE_ICG2(CLK_INFRA_DVFS_SPM1, "infra_dvfs_spm1", "axi_sel", 15),
> 

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH v3 3/3] clk: mediatek: Mark bus and DRAM related clocks as critical
  2019-02-08 13:39   ` Matthias Brugger
@ 2019-02-13 17:09     ` Stephen Boyd
  0 siblings, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2019-02-13 17:09 UTC (permalink / raw)
  To: Matthias Brugger, kevin-cw.chen, mars.cheng, matthias.bgg, mturquette
  Cc: sean.wang, jasu, linux-clk, linux-kernel, linux-arm-kernel,
	linux-mediatek

Quoting Matthias Brugger (2019-02-08 05:39:02)
> Steven, Mike, any comments on that?

I was waiting for Mediatek to review. I thought I said that last time?
I suppose if they're not going to review it I'll just throw it into
clk-next and people can fix problems if they see them.

Would you mind resending one more time with a comment in the code where
CLK_IS_CRITICAL is used indicating why it's critical so that we know
what's going on without having to dig into the git history?


^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, back to index

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-08 12:12 [PATCH v3 0/3] Mark clocks as critical for MT6797 matthias.bgg
2019-01-08 12:12 ` [PATCH v3 1/3] clk: mediatek: Add MUX_FLAGS macro matthias.bgg
2019-01-08 12:12 ` [PATCH v3 2/3] clk: mediatek: Add flags to mtk_gate matthias.bgg
2019-01-08 12:12 ` [PATCH v3 3/3] clk: mediatek: Mark bus and DRAM related clocks as critical matthias.bgg
2019-02-08 13:39   ` Matthias Brugger
2019-02-13 17:09     ` Stephen Boyd

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