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Wed, 06 Jan 2021 02:25:47 -0800 (PST) MIME-Version: 1.0 References: <1608642587-15634-1-git-send-email-weiyi.lu@mediatek.com> <1608642587-15634-11-git-send-email-weiyi.lu@mediatek.com> In-Reply-To: <1608642587-15634-11-git-send-email-weiyi.lu@mediatek.com> From: Ikjoon Jang Date: Wed, 6 Jan 2021 18:25:36 +0800 Message-ID: Subject: Re: [PATCH v6 10/22] clk: mediatek: Add MT8192 basic clocks support To: Weiyi Lu Cc: Matthias Brugger , Rob Herring , Stephen Boyd , Nicolas Boichat , srv_heupstream , open list , Project_Global_Chrome_Upstream_Group@mediatek.com, "moderated list:ARM/Mediatek SoC support" , linux-clk@vger.kernel.org, "moderated list:ARM/Mediatek SoC support" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On Tue, Dec 22, 2020 at 9:14 PM Weiyi Lu wrote: > > Add MT8192 basic clock providers, include topckgen, apmixedsys, > infracfg and pericfg. > > Signed-off-by: Weiyi Lu > --- > drivers/clk/mediatek/Kconfig | 8 + > drivers/clk/mediatek/Makefile | 1 + > drivers/clk/mediatek/clk-mt8192.c | 1326 +++++++++++++++++++++++++++++++++++++ > drivers/clk/mediatek/clk-mux.h | 15 + > 4 files changed, 1350 insertions(+) > create mode 100644 drivers/clk/mediatek/clk-mt8192.c > > diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h > index f5625f4..afbc7df 100644 > --- a/drivers/clk/mediatek/clk-mux.h > +++ b/drivers/clk/mediatek/clk-mux.h > @@ -77,6 +77,21 @@ struct mtk_mux { > _width, _gate, _upd_ofs, _upd, \ > CLK_SET_RATE_PARENT) > > +#define MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ > + _upd_ofs, _upd, _flags) \ > + GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ > + 0, _upd_ofs, _upd, _flags, \ > + mtk_mux_clr_set_upd_ops) > + > +#define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ > + _upd_ofs, _upd) \ > + MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, \ > + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \ > + _width, _upd_ofs, _upd, CLK_SET_RATE_PARENT) > + conflicts, these macros are already existed in upstream. > struct clk *mtk_clk_register_mux(const struct mtk_mux *mux, > struct regmap *regmap, > spinlock_t *lock); > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek