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From: Chunyan Zhang <zhang.lyra@gmail.com>
To: Stephen Boyd <sboyd@kernel.org>
Cc: Chunyan Zhang <chunyan.zhang@unisoc.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Rob Herring <robh+dt@kernel.org>,
	linux-clk <linux-clk@vger.kernel.org>,
	DTML <devicetree@vger.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Orson Zhai <orsonzhai@gmail.com>,
	Baolin Wang <baolin.wang7@gmail.com>
Subject: Re: [PATCH 5/5] clk: sprd: add clocks support for SC9863A
Date: Sun, 17 Nov 2019 19:27:15 +0800	[thread overview]
Message-ID: <CAAfSe-twxx4PyERHXuYcoehPoNYiVaOS4hZEK0KndoM2sL_5gQ@mail.gmail.com> (raw)
In-Reply-To: <20191113221952.AD925206E3@mail.kernel.org>

Hi Stephen,

On Thu, 14 Nov 2019 at 06:19, Stephen Boyd <sboyd@kernel.org> wrote:
>

[cut]

>
> > +static const u64 itable_dpll[5] = {4, 1211000000, 1320000000, 1570000000,
> > +                                  1866000000};
> > +static SPRD_PLL_WITH_ITABLE_1K(dpll0_clk, "dpll0", "dpll0-gate", 0x0,
> > +                                  3, itable_dpll, f_dpll, 240);
> > +static SPRD_PLL_WITH_ITABLE_1K(dpll1_clk, "dpll1", "dpll1-gate", 0x18,
> > +                                  3, itable_dpll, f_dpll, 240);
> > +
> > +static CLK_FIXED_FACTOR(dpll0_933m, "dpll0-933m", "dpll0", 2, 1, 0);
> > +static CLK_FIXED_FACTOR(dpll0_622m3, "dpll0-622m3", "dpll0", 3, 1, 0);
> > +static CLK_FIXED_FACTOR(dpll1_400m, "dpll1-400m", "dpll1", 4, 1, 0);
> > +static CLK_FIXED_FACTOR(dpll1_266m7, "dpll1-266m7", "dpll1", 6, 1, 0);
> > +static CLK_FIXED_FACTOR(dpll1_123m1, "dpll1-123m1", "dpll1", 13, 1, 0);
> > +static CLK_FIXED_FACTOR(dpll1_50m, "dpll1-50m", "dpll1", 32, 1, 0);
> > +
> > +static struct sprd_clk_common *sc9863a_dpll_clks[] = {
> [...]
> > +static SPRD_COMP_CLK(core0_clk, "core0-clk", core_parents, 0xa20,
> > +                    0, 3, 8, 3, 0);
> > +static SPRD_COMP_CLK(core1_clk, "core1-clk", core_parents, 0xa24,
> > +                    0, 3, 8, 3, 0);
> > +static SPRD_COMP_CLK(core2_clk, "core2-clk", core_parents, 0xa28,
> > +                    0, 3, 8, 3, 0);
> > +static SPRD_COMP_CLK(core3_clk, "core3-clk", core_parents, 0xa2c,
> > +                    0, 3, 8, 3, 0);
> > +static SPRD_COMP_CLK(core4_clk, "core4-clk", core_parents, 0xa30,
> > +                    0, 3, 8, 3, 0);
> > +static SPRD_COMP_CLK(core5_clk, "core5-clk", core_parents, 0xa34,
> > +                    0, 3, 8, 3, 0);
> > +static SPRD_COMP_CLK(core6_clk, "core6-clk", core_parents, 0xa38,
> > +                    0, 3, 8, 3, 0);
> > +static SPRD_COMP_CLK(core7_clk, "core7-clk", core_parents, 0xa3c,
> > +                    0, 3, 8, 3, 0);
> > +static SPRD_COMP_CLK(scu_clk, "scu-clk", core_parents, 0xa40,
> > +                    0, 3, 8, 3, 0);
> > +static SPRD_DIV_CLK(ace_clk, "ace-clk", "scu-clk", 0xa44,
> > +                   8, 3, 0);
> > +static SPRD_DIV_CLK(axi_periph_clk, "axi-periph-clk", "scu-clk", 0xa48,
> > +                   8, 3, 0);
> > +static SPRD_DIV_CLK(axi_acp_clk, "axi-acp-clk", "scu-clk", 0xa4c,
> > +                   8, 3, 0);
> > +
> > +static const char * const atb_parents[] = { "ext-26m", "twpll-384m",
> > +                                           "twpll-512m", "mpll2" };
> > +static SPRD_COMP_CLK(atb_clk, "atb-clk", atb_parents, 0xa50,
> > +                    0, 2, 8, 3, 0);
> > +static SPRD_DIV_CLK(debug_apb_clk, "debug-apb-clk", "atb-clk", 0xa54,
> > +                   8, 3, 0);
> > +
> > +static const char * const gic_parents[] = { "ext-26m", "twpll-153m6",
> > +                                           "twpll-384m", "twpll-512m" };
>
> Can you use the new way of specifying clk parents instead of using these
> big string lists? That will hopefully cut down on the size of this code
> by reducing all these string lists.

Not sure if I understand correctly - do you mean that switch to use a
reference to clk_parent_data.hw in the driver instead?
like:
https://elixir.bootlin.com/linux/v5.4-rc7/source/drivers/clk/qcom/gcc-sm8150.c#L136

Since if I have to define many clk_parent_data.fw_name strings
instead, it seems not able to reduce the code size, right?

Thanks,
Chunyan

  parent reply	other threads:[~2019-11-17 11:27 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-25 11:13 [PATCH 0/5] Add clocks for Unisoc's SC9863A Chunyan Zhang
2019-10-25 11:13 ` [PATCH 1/5] clk: sprd: add gate for pll clocks Chunyan Zhang
2019-11-13 22:15   ` Stephen Boyd
2019-10-25 11:13 ` [PATCH 2/5] dt-bindings: clk: sprd: rename the common file name sprd.txt to SoC specific Chunyan Zhang
2019-10-29 21:46   ` Rob Herring
2019-10-25 11:13 ` [PATCH 3/5] dt-bindings: clk: sprd: add bindings for sc9863a clock controller Chunyan Zhang
2019-10-29 22:01   ` Rob Herring
2019-10-25 11:13 ` [PATCH 4/5] clk: sprd: Add dt-bindings include file for SC9863A Chunyan Zhang
2019-10-29 22:03   ` Rob Herring
2019-10-25 11:13 ` [PATCH 5/5] clk: sprd: add clocks support " Chunyan Zhang
2019-11-13 22:19   ` Stephen Boyd
2019-11-14  7:13     ` Chunyan Zhang
2019-11-17 11:27     ` Chunyan Zhang [this message]
2019-11-25  1:33       ` Stephen Boyd
2019-11-25  2:10         ` Chunyan Zhang
2019-11-25 16:35           ` Stephen Boyd

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