From: Linus Walleij <linus.walleij@linaro.org>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk <linux-clk@vger.kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Ulf Hansson <ulf.hansson@linaro.org>
Subject: Re: [PATCH 2/2 v3] clk: ux500: Add driver for the reset portions of PRCC
Date: Wed, 20 Oct 2021 01:58:39 +0200 [thread overview]
Message-ID: <CACRpkdbpAshdn9GTQRHVXpe7VpCAUmiEo+RdEVLzSjq7VJA=Og@mail.gmail.com> (raw)
In-Reply-To: <20210921184803.1757916-2-linus.walleij@linaro.org>
On Tue, Sep 21, 2021 at 8:50 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> The Ux500 PRCC (peripheral reset and clock controller) can also
> control reset of the IP blocks, not just clocks. As the PRCC is probed
> as a clock controller and we have other platforms implementing combined
> clock and reset controllers, follow this pattern and implement the PRCC
> rest controller as part of the clock driver.
>
> The reset controller needs to be selected from the machine as Ux500 has
> traditionally selected its mandatory subsystem prerequisites from there.
>
> Cc: Philipp Zabel <p.zabel@pengutronix.de>
> Cc: Ulf Hansson <ulf.hansson@linaro.org>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
One month has passed, can we merge this patch?
Philipp's review comments should be addressed.
Yours,
Linus Walleij
next prev parent reply other threads:[~2021-10-19 23:59 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-21 18:48 [PATCH 1/2 v3] dt-bindings: clock: u8500: Rewrite in YAML and extend Linus Walleij
2021-09-21 18:48 ` [PATCH 2/2 v3] clk: ux500: Add driver for the reset portions of PRCC Linus Walleij
2021-10-19 23:58 ` Linus Walleij [this message]
2021-10-20 10:13 ` Ulf Hansson
2021-10-27 1:04 ` Stephen Boyd
2021-10-19 23:57 ` [PATCH 1/2 v3] dt-bindings: clock: u8500: Rewrite in YAML and extend Linus Walleij
2021-10-27 1:03 ` Stephen Boyd
2021-10-27 1:04 ` Stephen Boyd
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