* [PATCH v2 0/4] clk: meson: g12a: add support for DVFS @ 2019-07-31 8:40 Neil Armstrong 2019-07-31 8:40 ` [PATCH v2 1/4] clk: core: introduce clk_hw_set_parent() Neil Armstrong ` (5 more replies) 0 siblings, 6 replies; 12+ messages in thread From: Neil Armstrong @ 2019-07-31 8:40 UTC (permalink / raw) To: sboyd, jbrunet Cc: Neil Armstrong, linux-clk, linux-kernel, linux-amlogic, linux-arm-kernel The G12A/G12B Socs embeds a specific clock tree for each CPU cluster : cpu_clk / cpub_clk | \- cpu_clk_dyn | | \- cpu_clk_premux0 | | |- cpu_clk_postmux0 | | | |- cpu_clk_dyn0_div | | | \- xtal/fclk_div2/fclk_div3 | | \- xtal/fclk_div2/fclk_div3 | \- cpu_clk_premux1 | |- cpu_clk_postmux1 | | |- cpu_clk_dyn1_div | | \- xtal/fclk_div2/fclk_div3 | \- xtal/fclk_div2/fclk_div3 \ sys_pll / sys1_pll This patchset adds notifiers on cpu_clk / cpub_clk, cpu_clk_dyn, cpu_clk_premux0 and sys_pll / sys1_pll to permit change frequency of the CPU clock in a safe way as recommended by the vendor Documentation and reference code. This patchset : - introduces needed core and meson clk changes - adds the clock notifiers Dependencies: - None This patchset is split from the v3 RFC/RFC patchset at [3] Changes from v1 at [4]: - Removed export of regmap_div ops functions - Added standalone cpu dynamic divider driver - Uses cpu dynamic divider driver in g12a clkc driver - Added missing signed-off tags - Fixed missing removal of CLKID_CPUB_CLK from internal g12a.h Changes from RFT/RFC v3 at [3]: - Rebased on clk-meson v5.4/drivers tree with Alexandre's patches - Removed the eeclk setup() callback, moved to a toplevel g12a-data struct Changes since RFT/RFC v2 at [2]: - Rebased on clk-meson v5.3/drivers trees - added Kevin's review tags Changes since RFT/RFC v1 at [1]: - Added EXPORT_SYMBOL_GPL() to clk_hw_set_parent - Added missing static to g12b_cpub_clk_mux0_div_ops and g12a_cpu_clk_mux_nb - Simplified g12a_cpu_clk_mux_notifier_cb() without switch/case - Fixed typo in "this the current path" in g12a.c - Fixed various checkpatch errors [1] https://patchwork.kernel.org/cover/11006929/ [2] https://patchwork.kernel.org/cover/11017273/ [3] https://patchwork.kernel.org/cover/11025309/ [4] https://patchwork.kernel.org/cover/11063803/ Neil Armstrong (4): clk: core: introduce clk_hw_set_parent() clk: meson: add g12a cpu dynamic divider driver clk: meson: g12a: add notifiers to handle cpu clock change clk: meson: g12a: expose CPUB clock ID for G12B drivers/clk/clk.c | 6 + drivers/clk/meson/Kconfig | 5 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/clk-cpu-dyndiv.c | 73 ++++ drivers/clk/meson/clk-cpu-dyndiv.h | 20 + drivers/clk/meson/g12a.c | 535 +++++++++++++++++++++++--- drivers/clk/meson/g12a.h | 1 - include/dt-bindings/clock/g12a-clkc.h | 1 + include/linux/clk-provider.h | 1 + 9 files changed, 588 insertions(+), 55 deletions(-) create mode 100644 drivers/clk/meson/clk-cpu-dyndiv.c create mode 100644 drivers/clk/meson/clk-cpu-dyndiv.h -- 2.22.0 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 1/4] clk: core: introduce clk_hw_set_parent() 2019-07-31 8:40 [PATCH v2 0/4] clk: meson: g12a: add support for DVFS Neil Armstrong @ 2019-07-31 8:40 ` Neil Armstrong 2019-08-06 8:28 ` Jerome Brunet 2019-07-31 8:40 ` [PATCH v2 2/4] clk: meson: add g12a cpu dynamic divider driver Neil Armstrong ` (4 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Neil Armstrong @ 2019-07-31 8:40 UTC (permalink / raw) To: sboyd, jbrunet Cc: Neil Armstrong, linux-clk, linux-kernel, linux-amlogic, linux-arm-kernel, Martin Blumenstingl Introduce the clk_hw_set_parent() provider call to change parent of a clock by using the clk_hw pointers. This eases the clock reparenting from clock rate notifiers and implementing DVFS with simpler code avoiding the boilerplates functions as __clk_lookup(clk_hw_get_name()) then clk_set_parent(). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- drivers/clk/clk.c | 6 ++++++ include/linux/clk-provider.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index c0990703ce54..c11b1781d24a 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -2487,6 +2487,12 @@ static int clk_core_set_parent_nolock(struct clk_core *core, return ret; } +int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *parent) +{ + return clk_core_set_parent_nolock(hw->core, parent->core); +} +EXPORT_SYMBOL_GPL(clk_hw_set_parent); + /** * clk_set_parent - switch the parent of a mux clk * @clk: the mux clk whose input we are switching diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 2ae7604783dd..dce5521a9bf6 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -817,6 +817,7 @@ unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index); +int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent); unsigned int __clk_get_enable_count(struct clk *clk); unsigned long clk_hw_get_rate(const struct clk_hw *hw); unsigned long __clk_get_flags(struct clk *clk); -- 2.22.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 1/4] clk: core: introduce clk_hw_set_parent() 2019-07-31 8:40 ` [PATCH v2 1/4] clk: core: introduce clk_hw_set_parent() Neil Armstrong @ 2019-08-06 8:28 ` Jerome Brunet 2019-08-08 4:47 ` Stephen Boyd 0 siblings, 1 reply; 12+ messages in thread From: Jerome Brunet @ 2019-08-06 8:28 UTC (permalink / raw) To: Neil Armstrong, sboyd Cc: Neil Armstrong, linux-clk, linux-kernel, linux-amlogic, linux-arm-kernel, Martin Blumenstingl On Wed 31 Jul 2019 at 10:40, Neil Armstrong <narmstrong@baylibre.com> wrote: > Introduce the clk_hw_set_parent() provider call to change parent of > a clock by using the clk_hw pointers. > > This eases the clock reparenting from clock rate notifiers and > implementing DVFS with simpler code avoiding the boilerplates > functions as __clk_lookup(clk_hw_get_name()) then clk_set_parent(). > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Looks ok to me but we will obviously need Stephen's ack to apply it > --- > drivers/clk/clk.c | 6 ++++++ > include/linux/clk-provider.h | 1 + > 2 files changed, 7 insertions(+) > > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c > index c0990703ce54..c11b1781d24a 100644 > --- a/drivers/clk/clk.c > +++ b/drivers/clk/clk.c > @@ -2487,6 +2487,12 @@ static int clk_core_set_parent_nolock(struct clk_core *core, > return ret; > } > > +int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *parent) > +{ > + return clk_core_set_parent_nolock(hw->core, parent->core); > +} > +EXPORT_SYMBOL_GPL(clk_hw_set_parent); > + > /** > * clk_set_parent - switch the parent of a mux clk > * @clk: the mux clk whose input we are switching > diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h > index 2ae7604783dd..dce5521a9bf6 100644 > --- a/include/linux/clk-provider.h > +++ b/include/linux/clk-provider.h > @@ -817,6 +817,7 @@ unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); > struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); > struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, > unsigned int index); > +int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent); > unsigned int __clk_get_enable_count(struct clk *clk); > unsigned long clk_hw_get_rate(const struct clk_hw *hw); > unsigned long __clk_get_flags(struct clk *clk); > -- > 2.22.0 ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 1/4] clk: core: introduce clk_hw_set_parent() 2019-08-06 8:28 ` Jerome Brunet @ 2019-08-08 4:47 ` Stephen Boyd 0 siblings, 0 replies; 12+ messages in thread From: Stephen Boyd @ 2019-08-08 4:47 UTC (permalink / raw) To: Jerome Brunet, Neil Armstrong Cc: Neil Armstrong, linux-clk, linux-kernel, linux-amlogic, linux-arm-kernel, Martin Blumenstingl Quoting Jerome Brunet (2019-08-06 01:28:19) > On Wed 31 Jul 2019 at 10:40, Neil Armstrong <narmstrong@baylibre.com> wrote: > > > Introduce the clk_hw_set_parent() provider call to change parent of > > a clock by using the clk_hw pointers. > > > > This eases the clock reparenting from clock rate notifiers and > > implementing DVFS with simpler code avoiding the boilerplates > > functions as __clk_lookup(clk_hw_get_name()) then clk_set_parent(). > > > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > > Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > > Looks ok to me but we will obviously need Stephen's ack to apply it Acked-by: Stephen Boyd <sboyd@kernel.org> > > > --- > > drivers/clk/clk.c | 6 ++++++ > > include/linux/clk-provider.h | 1 + > > 2 files changed, 7 insertions(+) > > > > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c > > index c0990703ce54..c11b1781d24a 100644 > > --- a/drivers/clk/clk.c > > +++ b/drivers/clk/clk.c > > @@ -2487,6 +2487,12 @@ static int clk_core_set_parent_nolock(struct clk_core *core, > > return ret; > > } > > > > +int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *parent) > > +{ > > + return clk_core_set_parent_nolock(hw->core, parent->core); I wonder if you really want to call all those things in clk_core_set_parent_nolock(). For example, do you want notifiers to run again and for rates to be speculated? Maybe all you want to do is overwrite some value for the clk's parent by calling into the ops for the clk and generically parse the value that's passed as the "parent" here. I ask because it may be good to avoid doing all that work and updating bookkeeping when we're deep in a notifier. If we can clearly understand what the driver wants to do from the notifier then it's simpler to change in the future to use things such as the coordinated clk rate vaporware. ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 2/4] clk: meson: add g12a cpu dynamic divider driver 2019-07-31 8:40 [PATCH v2 0/4] clk: meson: g12a: add support for DVFS Neil Armstrong 2019-07-31 8:40 ` [PATCH v2 1/4] clk: core: introduce clk_hw_set_parent() Neil Armstrong @ 2019-07-31 8:40 ` Neil Armstrong 2019-08-03 18:34 ` Martin Blumenstingl 2019-07-31 8:40 ` [PATCH v2 3/4] clk: meson: g12a: add notifiers to handle cpu clock change Neil Armstrong ` (3 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Neil Armstrong @ 2019-07-31 8:40 UTC (permalink / raw) To: jbrunet Cc: Neil Armstrong, linux-clk, linux-kernel, linux-amlogic, linux-arm-kernel Add a clock driver for the cpu dynamic divider, this divider needs to have a flag set before setting the divider value then removed while writing the new value to the register. This drivers implements this behavior and will be used essentially on the Amlogic G12A and G12B SoCs for cpu clock trees. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- drivers/clk/meson/Kconfig | 5 ++ drivers/clk/meson/Makefile | 1 + drivers/clk/meson/clk-cpu-dyndiv.c | 73 ++++++++++++++++++++++++++++++ drivers/clk/meson/clk-cpu-dyndiv.h | 20 ++++++++ 4 files changed, 99 insertions(+) create mode 100644 drivers/clk/meson/clk-cpu-dyndiv.c create mode 100644 drivers/clk/meson/clk-cpu-dyndiv.h diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 500be0b0d473..dabeb435d067 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -36,6 +36,10 @@ config COMMON_CLK_MESON_EE_CLKC tristate select COMMON_CLK_MESON_REGMAP +config COMMON_CLK_MESON_CPU_DYNDIV + tristate + select COMMON_CLK_MESON_REGMAP + config COMMON_CLK_MESON8B bool depends on ARCH_MESON @@ -98,6 +102,7 @@ config COMMON_CLK_G12A select COMMON_CLK_MESON_PLL select COMMON_CLK_MESON_AO_CLKC select COMMON_CLK_MESON_EE_CLKC + select COMMON_CLK_MESON_CPU_DYNDIV select MFD_SYSCON help Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index f09d83dc3d60..3939f218587a 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -2,6 +2,7 @@ # Amlogic clock drivers obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o +obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o diff --git a/drivers/clk/meson/clk-cpu-dyndiv.c b/drivers/clk/meson/clk-cpu-dyndiv.c new file mode 100644 index 000000000000..36976927fe82 --- /dev/null +++ b/drivers/clk/meson/clk-cpu-dyndiv.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <linux/clk-provider.h> +#include <linux/module.h> + +#include "clk-regmap.h" +#include "clk-cpu-dyndiv.h" + +static inline struct meson_clk_cpu_dyndiv_data * +meson_clk_cpu_dyndiv_data(struct clk_regmap *clk) +{ + return (struct meson_clk_cpu_dyndiv_data *)clk->data; +} + +static unsigned long meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw *hw, + unsigned long prate) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk); + + return divider_recalc_rate(hw, prate, + meson_parm_read(clk->map, &data->div), + NULL, 0, data->div.width); +} + +static long meson_clk_cpu_dyndiv_round_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *prate) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk); + + return divider_round_rate(hw, rate, prate, NULL, data->div.width, 0); +} + +static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk); + unsigned int val; + int ret; + + ret = divider_get_val(rate, parent_rate, NULL, data->div.width, 0); + if (ret < 0) + return ret; + + val = (unsigned int)ret << data->div.shift; + + /* Write the SYS_CPU_DYN_ENABLE bit before changing the divider */ + meson_parm_write(clk->map, &data->dyn, 1); + + /* Update the divider while removing the SYS_CPU_DYN_ENABLE bit */ + return regmap_update_bits(clk->map, data->div.reg_off, + SETPMASK(data->div.width, data->div.shift) | + SETPMASK(data->dyn.width, data->dyn.shift), + val); +}; + +const struct clk_ops meson_clk_cpu_dyndiv_ops = { + .recalc_rate = meson_clk_cpu_dyndiv_recalc_rate, + .round_rate = meson_clk_cpu_dyndiv_round_rate, + .set_rate = meson_clk_cpu_dyndiv_set_rate, +}; +EXPORT_SYMBOL_GPL(meson_clk_cpu_dyndiv_ops); + +MODULE_DESCRIPTION("Amlogic CPU Dynamic Clock divider"); +MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/meson/clk-cpu-dyndiv.h b/drivers/clk/meson/clk-cpu-dyndiv.h new file mode 100644 index 000000000000..f4908404792e --- /dev/null +++ b/drivers/clk/meson/clk-cpu-dyndiv.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#ifndef __MESON_CLK_CPU_DYNDIV_H +#define __MESON_CLK_CPU_DYNDIV_H + +#include <linux/clk-provider.h> +#include "parm.h" + +struct meson_clk_cpu_dyndiv_data { + struct parm div; + struct parm dyn; +}; + +extern const struct clk_ops meson_clk_cpu_dyndiv_ops; + +#endif /* __MESON_CLK_CPU_DYNDIV_H */ -- 2.22.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 2/4] clk: meson: add g12a cpu dynamic divider driver 2019-07-31 8:40 ` [PATCH v2 2/4] clk: meson: add g12a cpu dynamic divider driver Neil Armstrong @ 2019-08-03 18:34 ` Martin Blumenstingl 0 siblings, 0 replies; 12+ messages in thread From: Martin Blumenstingl @ 2019-08-03 18:34 UTC (permalink / raw) To: Neil Armstrong Cc: jbrunet, linux-kernel, linux-amlogic, linux-clk, linux-arm-kernel On Wed, Jul 31, 2019 at 10:41 AM Neil Armstrong <narmstrong@baylibre.com> wrote: > > Add a clock driver for the cpu dynamic divider, this divider needs > to have a flag set before setting the divider value then removed > while writing the new value to the register. > > This drivers implements this behavior and will be used essentially > on the Amlogic G12A and G12B SoCs for cpu clock trees. > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> personally I would add: Suggested-by: Jerome Brunet <jbrunet@baylibre.com> ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 3/4] clk: meson: g12a: add notifiers to handle cpu clock change 2019-07-31 8:40 [PATCH v2 0/4] clk: meson: g12a: add support for DVFS Neil Armstrong 2019-07-31 8:40 ` [PATCH v2 1/4] clk: core: introduce clk_hw_set_parent() Neil Armstrong 2019-07-31 8:40 ` [PATCH v2 2/4] clk: meson: add g12a cpu dynamic divider driver Neil Armstrong @ 2019-07-31 8:40 ` Neil Armstrong 2019-07-31 8:40 ` [PATCH v2 4/4] clk: meson: g12a: expose CPUB clock ID for G12B Neil Armstrong ` (2 subsequent siblings) 5 siblings, 0 replies; 12+ messages in thread From: Neil Armstrong @ 2019-07-31 8:40 UTC (permalink / raw) To: jbrunet Cc: Neil Armstrong, linux-clk, linux-kernel, linux-amlogic, linux-arm-kernel In order to implement clock switching for the CLKID_CPU_CLK and CLKID_CPUB_CLK, notifiers are added on specific points of the clock tree : cpu_clk / cpub_clk | \- cpu_clk_dyn | | \- cpu_clk_premux0 | | |- cpu_clk_postmux0 | | | |- cpu_clk_dyn0_div | | | \- xtal/fclk_div2/fclk_div3 | | \- xtal/fclk_div2/fclk_div3 | \- cpu_clk_premux1 | |- cpu_clk_postmux1 | | |- cpu_clk_dyn1_div | | \- xtal/fclk_div2/fclk_div3 | \- xtal/fclk_div2/fclk_div3 \ sys_pll / sys1_pll This for each cluster, a single one for G12A, two for G12B. Each cpu_clk_premux1 tree is marked as read-only and CLK_SET_RATE_NO_REPARENT, to be used as "parking" clock in a safe clock frequency. A notifier is added on each cpu_clk_premux0 to detech when CCF want to change the frequency of the cpu_clk_dyn tree. In this notifier, the cpu_clk_premux1 tree is configured to use the xtal clock and then the cpu_clk_dyn is switch to cpu_clk_premux1 while CCF updates the cpu_clk_premux0 tree. A notifier is added on each sys_pll/sys1_pll to detect when CCF wants to change the PLL clock source of the cpu_clk. In this notifier, the cpu_clk is switched to cpu_clk_dyn while CCF updates the sys_pll/sys1_pll frequency. A third small notifier is added on each cpu_clk / cpub_clk and cpu_clk_dyn, add a small delay at PRE_RATE_CHANGE/POST_RATE_CHANGE to let the other notofiers change propagate before changing the cpu_clk_premux0 and sys_pll clock trees. This notifier set permits switching the cpu_clk / cpub_clk without any glitches and using a safe parking clock while switching between sub-GHz clocks using the cpu_clk_dyn tree. This setup has been tested and validated on the Amlogic G12A and G12B SoCs running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations of each cluster and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- drivers/clk/meson/g12a.c | 535 +++++++++++++++++++++++++++++++++++---- 1 file changed, 481 insertions(+), 54 deletions(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index e4957fd9f91f..e6011d18a719 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -14,10 +14,12 @@ #include <linux/init.h> #include <linux/of_device.h> #include <linux/platform_device.h> +#include <linux/clk.h> #include "clk-mpll.h" #include "clk-pll.h" #include "clk-regmap.h" +#include "clk-cpu-dyndiv.h" #include "vid-pll-div.h" #include "meson-eeclk.h" #include "g12a.h" @@ -88,16 +90,9 @@ static struct clk_regmap g12a_fixed_pll = { }, }; -/* - * Internal sys pll emulation configuration parameters - */ -static const struct reg_sequence g12a_sys_init_regs[] = { - { .reg = HHI_SYS_PLL_CNTL1, .def = 0x00000000 }, - { .reg = HHI_SYS_PLL_CNTL2, .def = 0x00000000 }, - { .reg = HHI_SYS_PLL_CNTL3, .def = 0x48681c00 }, - { .reg = HHI_SYS_PLL_CNTL4, .def = 0x88770290 }, - { .reg = HHI_SYS_PLL_CNTL5, .def = 0x39272000 }, - { .reg = HHI_SYS_PLL_CNTL6, .def = 0x56540000 }, +static const struct pll_mult_range g12a_sys_pll_mult_range = { + .min = 128, + .max = 250, }; static struct clk_regmap g12a_sys_pll_dco = { @@ -127,16 +122,17 @@ static struct clk_regmap g12a_sys_pll_dco = { .shift = 29, .width = 1, }, - .init_regs = g12a_sys_init_regs, - .init_count = ARRAY_SIZE(g12a_sys_init_regs), + .range = &g12a_sys_pll_mult_range, }, .hw.init = &(struct clk_init_data){ .name = "sys_pll_dco", - .ops = &meson_clk_pll_ro_ops, + .ops = &meson_clk_pll_ops, .parent_data = &(const struct clk_parent_data) { .fw_name = "xtal", }, .num_parents = 1, + /* This clock feeds the CPU, avoid disabling it */ + .flags = CLK_IS_CRITICAL, }, }; @@ -149,11 +145,12 @@ static struct clk_regmap g12a_sys_pll = { }, .hw.init = &(struct clk_init_data){ .name = "sys_pll", - .ops = &clk_regmap_divider_ro_ops, + .ops = &clk_regmap_divider_ops, .parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll_dco.hw }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -184,14 +181,17 @@ static struct clk_regmap g12b_sys1_pll_dco = { .shift = 29, .width = 1, }, + .range = &g12a_sys_pll_mult_range, }, .hw.init = &(struct clk_init_data){ .name = "sys1_pll_dco", - .ops = &meson_clk_pll_ro_ops, + .ops = &meson_clk_pll_ops, .parent_data = &(const struct clk_parent_data) { .fw_name = "xtal", }, .num_parents = 1, + /* This clock feeds the CPU, avoid disabling it */ + .flags = CLK_IS_CRITICAL, }, }; @@ -204,11 +204,12 @@ static struct clk_regmap g12b_sys1_pll = { }, .hw.init = &(struct clk_init_data){ .name = "sys1_pll", - .ops = &clk_regmap_divider_ro_ops, + .ops = &clk_regmap_divider_ops, .parent_hws = (const struct clk_hw *[]) { &g12b_sys1_pll_dco.hw }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -345,13 +346,15 @@ static struct clk_regmap g12a_cpu_clk_premux0 = { }, .hw.init = &(struct clk_init_data){ .name = "cpu_clk_dyn0_sel", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_data = (const struct clk_parent_data []) { { .fw_name = "xtal", }, { .hw = &g12a_fclk_div2.hw }, { .hw = &g12a_fclk_div3.hw }, }, .num_parents = 3, + /* This sub-tree is used a parking clock */ + .flags = CLK_SET_RATE_NO_REPARENT, }, }; @@ -364,30 +367,40 @@ static struct clk_regmap g12a_cpu_clk_premux1 = { }, .hw.init = &(struct clk_init_data){ .name = "cpu_clk_dyn1_sel", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_data = (const struct clk_parent_data []) { { .fw_name = "xtal", }, { .hw = &g12a_fclk_div2.hw }, { .hw = &g12a_fclk_div3.hw }, }, .num_parents = 3, + /* This sub-tree is used a parking clock */ + .flags = CLK_SET_RATE_NO_REPARENT }, }; /* Datasheet names this field as "mux0_divn_tcnt" */ static struct clk_regmap g12a_cpu_clk_mux0_div = { - .data = &(struct clk_regmap_div_data){ - .offset = HHI_SYS_CPU_CLK_CNTL0, - .shift = 4, - .width = 6, + .data = &(struct meson_clk_cpu_dyndiv_data){ + .div = { + .reg_off = HHI_SYS_CPU_CLK_CNTL0, + .shift = 4, + .width = 6, + }, + .dyn = { + .reg_off = HHI_SYS_CPU_CLK_CNTL0, + .shift = 26, + .width = 1, + }, }, .hw.init = &(struct clk_init_data){ .name = "cpu_clk_dyn0_div", - .ops = &clk_regmap_divider_ro_ops, + .ops = &meson_clk_cpu_dyndiv_ops, .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk_premux0.hw }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -400,12 +413,13 @@ static struct clk_regmap g12a_cpu_clk_postmux0 = { }, .hw.init = &(struct clk_init_data){ .name = "cpu_clk_dyn0", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk_premux0.hw, &g12a_cpu_clk_mux0_div.hw, }, .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -435,12 +449,14 @@ static struct clk_regmap g12a_cpu_clk_postmux1 = { }, .hw.init = &(struct clk_init_data){ .name = "cpu_clk_dyn1", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk_premux1.hw, &g12a_cpu_clk_mux1_div.hw, }, .num_parents = 2, + /* This sub-tree is used a parking clock */ + .flags = CLK_SET_RATE_NO_REPARENT, }, }; @@ -453,12 +469,13 @@ static struct clk_regmap g12a_cpu_clk_dyn = { }, .hw.init = &(struct clk_init_data){ .name = "cpu_clk_dyn", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk_postmux0.hw, &g12a_cpu_clk_postmux1.hw, }, .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -471,12 +488,13 @@ static struct clk_regmap g12a_cpu_clk = { }, .hw.init = &(struct clk_init_data){ .name = "cpu_clk", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk_dyn.hw, &g12a_sys_pll.hw, }, .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -489,12 +507,13 @@ static struct clk_regmap g12b_cpu_clk = { }, .hw.init = &(struct clk_init_data){ .name = "cpu_clk", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk_dyn.hw, &g12b_sys1_pll.hw }, .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -507,7 +526,7 @@ static struct clk_regmap g12b_cpub_clk_premux0 = { }, .hw.init = &(struct clk_init_data){ .name = "cpub_clk_dyn0_sel", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_data = (const struct clk_parent_data []) { { .fw_name = "xtal", }, { .hw = &g12a_fclk_div2.hw }, @@ -519,18 +538,26 @@ static struct clk_regmap g12b_cpub_clk_premux0 = { /* Datasheet names this field as "mux0_divn_tcnt" */ static struct clk_regmap g12b_cpub_clk_mux0_div = { - .data = &(struct clk_regmap_div_data){ - .offset = HHI_SYS_CPUB_CLK_CNTL, - .shift = 4, - .width = 6, + .data = &(struct meson_clk_cpu_dyndiv_data){ + .div = { + .reg_off = HHI_SYS_CPUB_CLK_CNTL, + .shift = 4, + .width = 6, + }, + .dyn = { + .reg_off = HHI_SYS_CPUB_CLK_CNTL, + .shift = 26, + .width = 1, + }, }, .hw.init = &(struct clk_init_data){ .name = "cpub_clk_dyn0_div", - .ops = &clk_regmap_divider_ro_ops, + .ops = &meson_clk_cpu_dyndiv_ops, .parent_hws = (const struct clk_hw *[]) { &g12b_cpub_clk_premux0.hw }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -543,12 +570,13 @@ static struct clk_regmap g12b_cpub_clk_postmux0 = { }, .hw.init = &(struct clk_init_data){ .name = "cpub_clk_dyn0", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_hws = (const struct clk_hw *[]) { &g12b_cpub_clk_premux0.hw, &g12b_cpub_clk_mux0_div.hw }, .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -561,13 +589,15 @@ static struct clk_regmap g12b_cpub_clk_premux1 = { }, .hw.init = &(struct clk_init_data){ .name = "cpub_clk_dyn1_sel", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_data = (const struct clk_parent_data []) { { .fw_name = "xtal", }, { .hw = &g12a_fclk_div2.hw }, { .hw = &g12a_fclk_div3.hw }, }, .num_parents = 3, + /* This sub-tree is used a parking clock */ + .flags = CLK_SET_RATE_NO_REPARENT, }, }; @@ -597,12 +627,14 @@ static struct clk_regmap g12b_cpub_clk_postmux1 = { }, .hw.init = &(struct clk_init_data){ .name = "cpub_clk_dyn1", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_hws = (const struct clk_hw *[]) { &g12b_cpub_clk_premux1.hw, &g12b_cpub_clk_mux1_div.hw }, .num_parents = 2, + /* This sub-tree is used a parking clock */ + .flags = CLK_SET_RATE_NO_REPARENT, }, }; @@ -615,12 +647,13 @@ static struct clk_regmap g12b_cpub_clk_dyn = { }, .hw.init = &(struct clk_init_data){ .name = "cpub_clk_dyn", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_hws = (const struct clk_hw *[]) { &g12b_cpub_clk_postmux0.hw, &g12b_cpub_clk_postmux1.hw }, .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -633,15 +666,227 @@ static struct clk_regmap g12b_cpub_clk = { }, .hw.init = &(struct clk_init_data){ .name = "cpub_clk", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_hws = (const struct clk_hw *[]) { &g12b_cpub_clk_dyn.hw, &g12a_sys_pll.hw }, .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, }, }; +static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + if (event == POST_RATE_CHANGE || event == PRE_RATE_CHANGE) { + /* Wait for clock propagation before/after changing the mux */ + udelay(100); + return NOTIFY_OK; + } + + return NOTIFY_DONE; +} + +static struct notifier_block g12a_cpu_clk_mux_nb = { + .notifier_call = g12a_cpu_clk_mux_notifier_cb, +}; + +struct g12a_cpu_clk_postmux_nb_data { + struct notifier_block nb; + struct clk_hw *xtal; + struct clk_hw *cpu_clk_dyn; + struct clk_hw *cpu_clk_postmux0; + struct clk_hw *cpu_clk_postmux1; + struct clk_hw *cpu_clk_premux1; +}; + +static int g12a_cpu_clk_postmux_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct g12a_cpu_clk_postmux_nb_data *nb_data = + container_of(nb, struct g12a_cpu_clk_postmux_nb_data, nb); + + switch (event) { + case PRE_RATE_CHANGE: + /* + * This notifier means cpu_clk_postmux0 clock will be changed + * to feed cpu_clk, this is the current path : + * cpu_clk + * \- cpu_clk_dyn + * \- cpu_clk_postmux0 + * \- cpu_clk_muxX_div + * \- cpu_clk_premux0 + * \- fclk_div3 or fclk_div2 + * OR + * \- cpu_clk_premux0 + * \- fclk_div3 or fclk_div2 + */ + + /* Setup cpu_clk_premux1 to xtal */ + clk_hw_set_parent(nb_data->cpu_clk_premux1, + nb_data->xtal); + + /* Setup cpu_clk_postmux1 to bypass divider */ + clk_hw_set_parent(nb_data->cpu_clk_postmux1, + nb_data->cpu_clk_premux1); + + /* Switch to parking clk on cpu_clk_postmux1 */ + clk_hw_set_parent(nb_data->cpu_clk_dyn, + nb_data->cpu_clk_postmux1); + + /* + * Now, cpu_clk is 24MHz in the current path : + * cpu_clk + * \- cpu_clk_dyn + * \- cpu_clk_postmux1 + * \- cpu_clk_premux1 + * \- xtal + */ + + udelay(100); + + return NOTIFY_OK; + + case POST_RATE_CHANGE: + /* + * The cpu_clk_postmux0 has ben updated, now switch back + * cpu_clk_dyn to cpu_clk_postmux0 and take the changes + * in account. + */ + + /* Configure cpu_clk_dyn back to cpu_clk_postmux0 */ + clk_hw_set_parent(nb_data->cpu_clk_dyn, + nb_data->cpu_clk_postmux0); + + /* + * new path : + * cpu_clk + * \- cpu_clk_dyn + * \- cpu_clk_postmux0 + * \- cpu_clk_muxX_div + * \- cpu_clk_premux0 + * \- fclk_div3 or fclk_div2 + * OR + * \- cpu_clk_premux0 + * \- fclk_div3 or fclk_div2 + */ + + udelay(100); + + return NOTIFY_OK; + + default: + return NOTIFY_DONE; + } +} + +static struct g12a_cpu_clk_postmux_nb_data g12a_cpu_clk_postmux0_nb_data = { + .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw, + .cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw, + .cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw, + .cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw, + .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb, +}; + +static struct g12a_cpu_clk_postmux_nb_data g12b_cpub_clk_postmux0_nb_data = { + .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw, + .cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw, + .cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw, + .cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw, + .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb, +}; + +struct g12a_sys_pll_nb_data { + struct notifier_block nb; + struct clk_hw *sys_pll; + struct clk_hw *cpu_clk; + struct clk_hw *cpu_clk_dyn; +}; + +static int g12a_sys_pll_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct g12a_sys_pll_nb_data *nb_data = + container_of(nb, struct g12a_sys_pll_nb_data, nb); + + switch (event) { + case PRE_RATE_CHANGE: + /* + * This notifier means sys_pll clock will be changed + * to feed cpu_clk, this the current path : + * cpu_clk + * \- sys_pll + * \- sys_pll_dco + */ + + /* Configure cpu_clk to use cpu_clk_dyn */ + clk_hw_set_parent(nb_data->cpu_clk, + nb_data->cpu_clk_dyn); + + /* + * Now, cpu_clk uses the dyn path + * cpu_clk + * \- cpu_clk_dyn + * \- cpu_clk_dynX + * \- cpu_clk_dynX_sel + * \- cpu_clk_dynX_div + * \- xtal/fclk_div2/fclk_div3 + * \- xtal/fclk_div2/fclk_div3 + */ + + udelay(100); + + return NOTIFY_OK; + + case POST_RATE_CHANGE: + /* + * The sys_pll has ben updated, now switch back cpu_clk to + * sys_pll + */ + + /* Configure cpu_clk to use sys_pll */ + clk_hw_set_parent(nb_data->cpu_clk, + nb_data->sys_pll); + + udelay(100); + + /* new path : + * cpu_clk + * \- sys_pll + * \- sys_pll_dco + */ + + return NOTIFY_OK; + + default: + return NOTIFY_DONE; + } +} + +static struct g12a_sys_pll_nb_data g12a_sys_pll_nb_data = { + .sys_pll = &g12a_sys_pll.hw, + .cpu_clk = &g12a_cpu_clk.hw, + .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw, + .nb.notifier_call = g12a_sys_pll_notifier_cb, +}; + +/* G12B first CPU cluster uses sys1_pll */ +static struct g12a_sys_pll_nb_data g12b_cpu_clk_sys1_pll_nb_data = { + .sys_pll = &g12b_sys1_pll.hw, + .cpu_clk = &g12b_cpu_clk.hw, + .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw, + .nb.notifier_call = g12a_sys_pll_notifier_cb, +}; + +/* G12B second CPU cluster uses sys_pll */ +static struct g12a_sys_pll_nb_data g12b_cpub_clk_sys_pll_nb_data = { + .sys_pll = &g12a_sys_pll.hw, + .cpu_clk = &g12b_cpub_clk.hw, + .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw, + .nb.notifier_call = g12a_sys_pll_notifier_cb, +}; + static struct clk_regmap g12a_cpu_clk_div16_en = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_SYS_CPU_CLK_CNTL1, @@ -4097,28 +4342,210 @@ static const struct reg_sequence g12a_init_regs[] = { { .reg = HHI_MPLL_CNTL0, .def = 0x00000543 }, }; -static const struct meson_eeclkc_data g12a_clkc_data = { - .regmap_clks = g12a_clk_regmaps, - .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), - .hw_onecell_data = &g12a_hw_onecell_data, - .init_regs = g12a_init_regs, - .init_count = ARRAY_SIZE(g12a_init_regs), -}; - -static const struct meson_eeclkc_data g12b_clkc_data = { - .regmap_clks = g12a_clk_regmaps, - .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), - .hw_onecell_data = &g12b_hw_onecell_data +static int meson_g12a_dvfs_setup_common(struct platform_device *pdev, + struct clk_hw **hws) +{ + const char *notifier_clk_name; + struct clk *notifier_clk; + struct clk_hw *xtal; + int ret; + + xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0); + + /* Setup clock notifier for cpu_clk_postmux0 */ + g12a_cpu_clk_postmux0_nb_data.xtal = xtal; + notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_postmux0.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, + &g12a_cpu_clk_postmux0_nb_data.nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the cpu_clk_postmux0 notifier\n"); + return ret; + } + + /* Setup clock notifier for cpu_clk_dyn mux */ + notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_dyn.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the cpu_clk_dyn notifier\n"); + return ret; + } + + return 0; +} + +static int meson_g12b_dvfs_setup(struct platform_device *pdev) +{ + struct clk_hw **hws = g12b_hw_onecell_data.hws; + const char *notifier_clk_name; + struct clk *notifier_clk; + struct clk_hw *xtal; + int ret; + + ret = meson_g12a_dvfs_setup_common(pdev, hws); + if (ret) + return ret; + + xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0); + + /* Setup clock notifier for cpu_clk mux */ + notifier_clk_name = clk_hw_get_name(&g12b_cpu_clk.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n"); + return ret; + } + + /* Setup clock notifier for sys1_pll */ + notifier_clk_name = clk_hw_get_name(&g12b_sys1_pll.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, + &g12b_cpu_clk_sys1_pll_nb_data.nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the sys1_pll notifier\n"); + return ret; + } + + /* Add notifiers for the second CPU cluster */ + + /* Setup clock notifier for cpub_clk_postmux0 */ + g12b_cpub_clk_postmux0_nb_data.xtal = xtal; + notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_postmux0.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, + &g12b_cpub_clk_postmux0_nb_data.nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the cpub_clk_postmux0 notifier\n"); + return ret; + } + + /* Setup clock notifier for cpub_clk_dyn mux */ + notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_dyn.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the cpub_clk_dyn notifier\n"); + return ret; + } + + /* Setup clock notifier for cpub_clk mux */ + notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the cpub_clk notifier\n"); + return ret; + } + + /* Setup clock notifier for sys_pll */ + notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, + &g12b_cpub_clk_sys_pll_nb_data.nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the sys_pll notifier\n"); + return ret; + } + + return 0; +} + +static int meson_g12a_dvfs_setup(struct platform_device *pdev) +{ + struct clk_hw **hws = g12a_hw_onecell_data.hws; + const char *notifier_clk_name; + struct clk *notifier_clk; + int ret; + + ret = meson_g12a_dvfs_setup_common(pdev, hws); + if (ret) + return ret; + + /* Setup clock notifier for cpu_clk mux */ + notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n"); + return ret; + } + + /* Setup clock notifier for sys_pll */ + notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, &g12a_sys_pll_nb_data.nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the sys_pll notifier\n"); + return ret; + } + + return 0; +} + +struct meson_g12a_data { + const struct meson_eeclkc_data eeclkc_data; + int (*dvfs_setup)(struct platform_device *pdev); +}; + +static int meson_g12a_probe(struct platform_device *pdev) +{ + const struct meson_eeclkc_data *eeclkc_data; + const struct meson_g12a_data *g12a_data; + int ret; + + eeclkc_data = of_device_get_match_data(&pdev->dev); + if (!eeclkc_data) + return -EINVAL; + + ret = meson_eeclkc_probe(pdev); + if (ret) + return ret; + + g12a_data = container_of(eeclkc_data, struct meson_g12a_data, + eeclkc_data); + + if (g12a_data->dvfs_setup) + return g12a_data->dvfs_setup(pdev); + + return 0; +} + +static const struct meson_g12a_data g12a_clkc_data = { + .eeclkc_data = { + .regmap_clks = g12a_clk_regmaps, + .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), + .hw_onecell_data = &g12a_hw_onecell_data, + .init_regs = g12a_init_regs, + .init_count = ARRAY_SIZE(g12a_init_regs), + }, + .dvfs_setup = meson_g12a_dvfs_setup, +}; + +static const struct meson_g12a_data g12b_clkc_data = { + .eeclkc_data = { + .regmap_clks = g12a_clk_regmaps, + .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), + .hw_onecell_data = &g12b_hw_onecell_data, + }, + .dvfs_setup = meson_g12b_dvfs_setup, }; static const struct of_device_id clkc_match_table[] = { - { .compatible = "amlogic,g12a-clkc", .data = &g12a_clkc_data }, - { .compatible = "amlogic,g12b-clkc", .data = &g12b_clkc_data }, + { + .compatible = "amlogic,g12a-clkc", + .data = &g12a_clkc_data.eeclkc_data + }, + { + .compatible = "amlogic,g12b-clkc", + .data = &g12b_clkc_data.eeclkc_data + }, {} }; static struct platform_driver g12a_driver = { - .probe = meson_eeclkc_probe, + .probe = meson_g12a_probe, .driver = { .name = "g12a-clkc", .of_match_table = clkc_match_table, -- 2.22.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 4/4] clk: meson: g12a: expose CPUB clock ID for G12B 2019-07-31 8:40 [PATCH v2 0/4] clk: meson: g12a: add support for DVFS Neil Armstrong ` (2 preceding siblings ...) 2019-07-31 8:40 ` [PATCH v2 3/4] clk: meson: g12a: add notifiers to handle cpu clock change Neil Armstrong @ 2019-07-31 8:40 ` Neil Armstrong 2019-08-06 8:38 ` [PATCH v2 0/4] clk: meson: g12a: add support for DVFS Jerome Brunet 2019-08-08 21:18 ` Kevin Hilman 5 siblings, 0 replies; 12+ messages in thread From: Neil Armstrong @ 2019-07-31 8:40 UTC (permalink / raw) To: jbrunet Cc: Neil Armstrong, linux-clk, linux-kernel, linux-amlogic, linux-arm-kernel, Martin Blumenstingl Expose the CPUB clock id to add DVFS to the second CPU cluster of the Amlogic G12B SoC. Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- drivers/clk/meson/g12a.h | 1 - include/dt-bindings/clock/g12a-clkc.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h index c8aed31fbe17..559a34cfdfeb 100644 --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h @@ -216,7 +216,6 @@ #define CLKID_CPUB_CLK_DYN1_DIV 221 #define CLKID_CPUB_CLK_DYN1 222 #define CLKID_CPUB_CLK_DYN 223 -#define CLKID_CPUB_CLK 224 #define CLKID_CPUB_CLK_DIV16_EN 225 #define CLKID_CPUB_CLK_DIV16 226 #define CLKID_CPUB_CLK_DIV2 227 diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index b6b127e45634..8ccc29ac7a72 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -137,5 +137,6 @@ #define CLKID_VDEC_HEVC 207 #define CLKID_VDEC_HEVCF 210 #define CLKID_TS 212 +#define CLKID_CPUB_CLK 224 #endif /* __G12A_CLKC_H */ -- 2.22.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 0/4] clk: meson: g12a: add support for DVFS 2019-07-31 8:40 [PATCH v2 0/4] clk: meson: g12a: add support for DVFS Neil Armstrong ` (3 preceding siblings ...) 2019-07-31 8:40 ` [PATCH v2 4/4] clk: meson: g12a: expose CPUB clock ID for G12B Neil Armstrong @ 2019-08-06 8:38 ` Jerome Brunet 2019-08-08 21:18 ` Kevin Hilman 5 siblings, 0 replies; 12+ messages in thread From: Jerome Brunet @ 2019-08-06 8:38 UTC (permalink / raw) To: Neil Armstrong, sboyd Cc: Neil Armstrong, linux-clk, linux-kernel, linux-amlogic, linux-arm-kernel On Wed 31 Jul 2019 at 10:40, Neil Armstrong <narmstrong@baylibre.com> wrote: > > Neil Armstrong (4): > clk: core: introduce clk_hw_set_parent() > clk: meson: add g12a cpu dynamic divider driver > clk: meson: g12a: add notifiers to handle cpu clock change > clk: meson: g12a: expose CPUB clock ID for G12B > > drivers/clk/clk.c | 6 + > drivers/clk/meson/Kconfig | 5 + > drivers/clk/meson/Makefile | 1 + > drivers/clk/meson/clk-cpu-dyndiv.c | 73 ++++ > drivers/clk/meson/clk-cpu-dyndiv.h | 20 + > drivers/clk/meson/g12a.c | 535 +++++++++++++++++++++++--- > drivers/clk/meson/g12a.h | 1 - > include/dt-bindings/clock/g12a-clkc.h | 1 + > include/linux/clk-provider.h | 1 + > 9 files changed, 588 insertions(+), 55 deletions(-) > create mode 100644 drivers/clk/meson/clk-cpu-dyndiv.c > create mode 100644 drivers/clk/meson/clk-cpu-dyndiv.h Patchset looks good to me. Waiting for Stephen's ack on patch #1 to apply it. > > -- > 2.22.0 ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 0/4] clk: meson: g12a: add support for DVFS 2019-07-31 8:40 [PATCH v2 0/4] clk: meson: g12a: add support for DVFS Neil Armstrong ` (4 preceding siblings ...) 2019-08-06 8:38 ` [PATCH v2 0/4] clk: meson: g12a: add support for DVFS Jerome Brunet @ 2019-08-08 21:18 ` Kevin Hilman 2019-08-09 13:02 ` Jerome Brunet 5 siblings, 1 reply; 12+ messages in thread From: Kevin Hilman @ 2019-08-08 21:18 UTC (permalink / raw) To: Neil Armstrong, sboyd, jbrunet Cc: Neil Armstrong, linux-clk, linux-kernel, linux-amlogic, linux-arm-kernel Neil Armstrong <narmstrong@baylibre.com> writes: > The G12A/G12B Socs embeds a specific clock tree for each CPU cluster : > cpu_clk / cpub_clk > | \- cpu_clk_dyn > | | \- cpu_clk_premux0 > | | |- cpu_clk_postmux0 > | | | |- cpu_clk_dyn0_div > | | | \- xtal/fclk_div2/fclk_div3 > | | \- xtal/fclk_div2/fclk_div3 > | \- cpu_clk_premux1 > | |- cpu_clk_postmux1 > | | |- cpu_clk_dyn1_div > | | \- xtal/fclk_div2/fclk_div3 > | \- xtal/fclk_div2/fclk_div3 > \ sys_pll / sys1_pll > > This patchset adds notifiers on cpu_clk / cpub_clk, cpu_clk_dyn, > cpu_clk_premux0 and sys_pll / sys1_pll to permit change frequency of > the CPU clock in a safe way as recommended by the vendor Documentation > and reference code. > > This patchset : > - introduces needed core and meson clk changes > - adds the clock notifiers > > Dependencies: > - None nit: this doesn't apply to v5.3-rc, but appears to apply on clk-meson/v5.4/drivers, so it appears to be dependent on the cleanups from Alex. Kevin ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 0/4] clk: meson: g12a: add support for DVFS 2019-08-08 21:18 ` Kevin Hilman @ 2019-08-09 13:02 ` Jerome Brunet 2019-08-09 17:55 ` Kevin Hilman 0 siblings, 1 reply; 12+ messages in thread From: Jerome Brunet @ 2019-08-09 13:02 UTC (permalink / raw) To: Kevin Hilman, Neil Armstrong, sboyd Cc: Neil Armstrong, linux-clk, linux-kernel, linux-amlogic, linux-arm-kernel On Thu 08 Aug 2019 at 14:18, Kevin Hilman <khilman@baylibre.com> wrote: > Neil Armstrong <narmstrong@baylibre.com> writes: > >> The G12A/G12B Socs embeds a specific clock tree for each CPU cluster : >> cpu_clk / cpub_clk >> | \- cpu_clk_dyn >> | | \- cpu_clk_premux0 >> | | |- cpu_clk_postmux0 >> | | | |- cpu_clk_dyn0_div >> | | | \- xtal/fclk_div2/fclk_div3 >> | | \- xtal/fclk_div2/fclk_div3 >> | \- cpu_clk_premux1 >> | |- cpu_clk_postmux1 >> | | |- cpu_clk_dyn1_div >> | | \- xtal/fclk_div2/fclk_div3 >> | \- xtal/fclk_div2/fclk_div3 >> \ sys_pll / sys1_pll >> >> This patchset adds notifiers on cpu_clk / cpub_clk, cpu_clk_dyn, >> cpu_clk_premux0 and sys_pll / sys1_pll to permit change frequency of >> the CPU clock in a safe way as recommended by the vendor Documentation >> and reference code. >> >> This patchset : >> - introduces needed core and meson clk changes >> - adds the clock notifiers >> >> Dependencies: >> - None > > nit: this doesn't apply to v5.3-rc, but appears to apply on > clk-meson/v5.4/drivers, so it appears to be dependent on the cleanups > from Alex. Indeed, Applied on top of this. > > Kevin ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 0/4] clk: meson: g12a: add support for DVFS 2019-08-09 13:02 ` Jerome Brunet @ 2019-08-09 17:55 ` Kevin Hilman 0 siblings, 0 replies; 12+ messages in thread From: Kevin Hilman @ 2019-08-09 17:55 UTC (permalink / raw) To: Jerome Brunet, Neil Armstrong, sboyd Cc: Neil Armstrong, linux-clk, linux-kernel, linux-amlogic, linux-arm-kernel Jerome Brunet <jbrunet@baylibre.com> writes: > On Thu 08 Aug 2019 at 14:18, Kevin Hilman <khilman@baylibre.com> wrote: > >> Neil Armstrong <narmstrong@baylibre.com> writes: >> >>> The G12A/G12B Socs embeds a specific clock tree for each CPU cluster : >>> cpu_clk / cpub_clk >>> | \- cpu_clk_dyn >>> | | \- cpu_clk_premux0 >>> | | |- cpu_clk_postmux0 >>> | | | |- cpu_clk_dyn0_div >>> | | | \- xtal/fclk_div2/fclk_div3 >>> | | \- xtal/fclk_div2/fclk_div3 >>> | \- cpu_clk_premux1 >>> | |- cpu_clk_postmux1 >>> | | |- cpu_clk_dyn1_div >>> | | \- xtal/fclk_div2/fclk_div3 >>> | \- xtal/fclk_div2/fclk_div3 >>> \ sys_pll / sys1_pll >>> >>> This patchset adds notifiers on cpu_clk / cpub_clk, cpu_clk_dyn, >>> cpu_clk_premux0 and sys_pll / sys1_pll to permit change frequency of >>> the CPU clock in a safe way as recommended by the vendor Documentation >>> and reference code. >>> >>> This patchset : >>> - introduces needed core and meson clk changes >>> - adds the clock notifiers >>> >>> Dependencies: >>> - None >> >> nit: this doesn't apply to v5.3-rc, but appears to apply on >> clk-meson/v5.4/drivers, so it appears to be dependent on the cleanups >> from Alex. > > Indeed, Applied on top of this. > Please let me know when you have a stable tag for this. I wont' be able to apply the odroid-n2 DVFS patch until I have this. Kevin ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-08-09 17:55 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-07-31 8:40 [PATCH v2 0/4] clk: meson: g12a: add support for DVFS Neil Armstrong 2019-07-31 8:40 ` [PATCH v2 1/4] clk: core: introduce clk_hw_set_parent() Neil Armstrong 2019-08-06 8:28 ` Jerome Brunet 2019-08-08 4:47 ` Stephen Boyd 2019-07-31 8:40 ` [PATCH v2 2/4] clk: meson: add g12a cpu dynamic divider driver Neil Armstrong 2019-08-03 18:34 ` Martin Blumenstingl 2019-07-31 8:40 ` [PATCH v2 3/4] clk: meson: g12a: add notifiers to handle cpu clock change Neil Armstrong 2019-07-31 8:40 ` [PATCH v2 4/4] clk: meson: g12a: expose CPUB clock ID for G12B Neil Armstrong 2019-08-06 8:38 ` [PATCH v2 0/4] clk: meson: g12a: add support for DVFS Jerome Brunet 2019-08-08 21:18 ` Kevin Hilman 2019-08-09 13:02 ` Jerome Brunet 2019-08-09 17:55 ` Kevin Hilman
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