From: Masahiro Yamada <yamada.masahiro@socionext.com>
To: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-clk <linux-clk@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Masami Hiramatsu <masami.hiramatsu@linaro.org>,
Jassi Brar <jaswinder.singh@linaro.org>
Subject: Re: [PATCH] clk: uniphier: Add SCSSI clock gate for each channel
Date: Tue, 3 Dec 2019 15:41:22 +0900 [thread overview]
Message-ID: <CAK7LNARjGtt-Ee_seet=nB7K0AVA8x4Q+bFRm=1A_aLn7Qancg@mail.gmail.com> (raw)
In-Reply-To: <1575000968-19434-1-git-send-email-hayashi.kunihiko@socionext.com>
On Fri, Nov 29, 2019 at 1:16 PM Kunihiko Hayashi
<hayashi.kunihiko@socionext.com> wrote:
>
> SCSSI has clock gates for each channel in the SoCs newer than Pro4,
> so this adds missing clock gates for channel 1, 2 and 3. And more, this
> moves MCSSI clock ID after SCSSI.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
Fixes: ff388ee36516 ("clk: uniphier: add clock frequency support for SPI")
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> drivers/clk/uniphier/clk-uniphier-peri.c | 13 ++++++++-----
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/uniphier/clk-uniphier-peri.c b/drivers/clk/uniphier/clk-uniphier-peri.c
> index 9caa529..3e32db9 100644
> --- a/drivers/clk/uniphier/clk-uniphier-peri.c
> +++ b/drivers/clk/uniphier/clk-uniphier-peri.c
> @@ -18,8 +18,8 @@
> #define UNIPHIER_PERI_CLK_FI2C(idx, ch) \
> UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c", 0x24, 24 + (ch))
>
> -#define UNIPHIER_PERI_CLK_SCSSI(idx) \
> - UNIPHIER_CLK_GATE("scssi", (idx), "spi", 0x20, 17)
> +#define UNIPHIER_PERI_CLK_SCSSI(idx, ch) \
> + UNIPHIER_CLK_GATE("scssi" #ch, (idx), "spi", 0x20, 17 + (ch))
>
> #define UNIPHIER_PERI_CLK_MCSSI(idx) \
> UNIPHIER_CLK_GATE("mcssi", (idx), "spi", 0x24, 14)
> @@ -35,7 +35,7 @@ const struct uniphier_clk_data uniphier_ld4_peri_clk_data[] = {
> UNIPHIER_PERI_CLK_I2C(6, 2),
> UNIPHIER_PERI_CLK_I2C(7, 3),
> UNIPHIER_PERI_CLK_I2C(8, 4),
> - UNIPHIER_PERI_CLK_SCSSI(11),
> + UNIPHIER_PERI_CLK_SCSSI(11, 0),
> { /* sentinel */ }
> };
>
> @@ -51,7 +51,10 @@ const struct uniphier_clk_data uniphier_pro4_peri_clk_data[] = {
> UNIPHIER_PERI_CLK_FI2C(8, 4),
> UNIPHIER_PERI_CLK_FI2C(9, 5),
> UNIPHIER_PERI_CLK_FI2C(10, 6),
> - UNIPHIER_PERI_CLK_SCSSI(11),
> - UNIPHIER_PERI_CLK_MCSSI(12),
> + UNIPHIER_PERI_CLK_SCSSI(11, 0),
> + UNIPHIER_PERI_CLK_SCSSI(12, 1),
> + UNIPHIER_PERI_CLK_SCSSI(13, 2),
> + UNIPHIER_PERI_CLK_SCSSI(14, 3),
> + UNIPHIER_PERI_CLK_MCSSI(15),
> { /* sentinel */ }
> };
> --
> 2.7.4
>
--
Best Regards
Masahiro Yamada
prev parent reply other threads:[~2019-12-03 6:42 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-29 4:16 [PATCH] clk: uniphier: Add SCSSI clock gate for each channel Kunihiko Hayashi
2019-12-03 6:41 ` Masahiro Yamada [this message]
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