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bh=NM4cO7yx6XHdWkikFjcDmehOMtjxSh2FAaet+Jaova8=; b=fTcfXfYZDE5hPphO+uXhCRncVfgCPbD61bG9y+8R+0pkvt48gkvpZYFZKdYJlEBgYi iuYNJ1Ls/wJqgs23rN4vLVM1q19JHA4XSRzbMhu8SblqjwDYCeawuC1/phr71lc6IgK6 zvQEBa1Tw0PpLGEeY8xaIx9C39B7QKjgc4RIhVLnmdFOdi9xwjQw2DJPFVWXwP3gHB9T HrXNMkToRPzkU4UQ+oSaPYN9TZk0HeFXznnM3qhTsO+T12mB4YX7IYmumJJRXAAcEPpS M36uyFusTNpB7u5kENTx71RpKztHlBSrpqFJHBlzQEK7A+A69QS47YNu3tJvIvPigXKU 9Zaw== X-Gm-Message-State: APjAAAVDwWTfqec3RBy4FYjvjStYQ0SIHt3PTYejx/2QJxTcnDbpJVvb PrQvkaM4HCINjbTbWYCfgZFfQrSlyU1eklsj+OM= X-Google-Smtp-Source: APXvYqyL0u361qZHtYP5NXawXdgFVviSEzFvt2t+iyc4L3etqBxubixvgUGBf2C08rJKMqTlkvE+MGfhYtfKGSUrSwE= X-Received: by 2002:a05:6402:12d1:: with SMTP id k17mr105414587edx.291.1578284247470; Sun, 05 Jan 2020 20:17:27 -0800 (PST) MIME-Version: 1.0 References: <55183b0a7c466528361802fabef65a57f969d07b.1574922435.git.shubhrajyoti.datta@xilinx.com> <20200105200014.4904320678@mail.kernel.org> In-Reply-To: <20200105200014.4904320678@mail.kernel.org> From: Shubhrajyoti Datta Date: Mon, 6 Jan 2020 09:47:16 +0530 Message-ID: Subject: Re: [PATCH v3 07/10] clk: clock-wizard: Update the fixed factor divisors To: Stephen Boyd Cc: devel@driverdev.osuosl.org, linux-clk@vger.kernel.org, linux-kernel , Greg Kroah-Hartman , Mike Turquette , Rob Herring , Mark Rutland , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , =?UTF-8?Q?S=C3=B6ren_Brinkmann?= , Shubhrajyoti Datta Content-Type: text/plain; charset="UTF-8" Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On Mon, Jan 6, 2020 at 1:30 AM Stephen Boyd wrote: > > Quoting shubhrajyoti.datta@gmail.com (2019-11-27 22:36:14) > > From: Shubhrajyoti Datta > > > > Update the fixed factor clock registration to register the divisors. > > > > Signed-off-by: Shubhrajyoti Datta > > --- > > drivers/clk/clk-xlnx-clock-wizard.c | 17 +++++++++++------ > > 1 file changed, 11 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c > > index 4c6155b..75ea745 100644 > > --- a/drivers/clk/clk-xlnx-clock-wizard.c > > +++ b/drivers/clk/clk-xlnx-clock-wizard.c > > @@ -491,9 +491,11 @@ static int clk_wzrd_probe(struct platform_device *pdev) > > u32 reg, reg_f, mult; > > unsigned long rate; > > const char *clk_name; > > + void __iomem *ctrl_reg; > > struct clk_wzrd *clk_wzrd; > > struct resource *mem; > > int outputs; > > + unsigned long flags = 0; > > struct device_node *np = pdev->dev.of_node; > > > > clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL); > > @@ -564,19 +566,22 @@ static int clk_wzrd_probe(struct platform_device *pdev) > > goto err_disable_clk; > > } > > > > - /* register div */ > > - reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) & > > - WZRD_DIVCLK_DIVIDE_MASK) >> WZRD_DIVCLK_DIVIDE_SHIFT; > > + outputs = of_property_count_strings(np, "clock-output-names"); > > + if (outputs == 1) > > + flags = CLK_SET_RATE_PARENT; > > What does the number of clk outputs have to do with the ability to > change the rate of a parent clk? The commit text doesn't inform me of > what this is for either. Please help us understand. If there are multiple clocks then changing the rate of the parent changes the rate of all the outputs so we donot allow changing the rate of the parent if there are multiple clocks. If there is only one output then that is not an issue. I will update the description in the next version. > > > clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev)); > > if (!clk_name) { > > ret = -ENOMEM; > > goto err_rm_int_clk; > > } > >