From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9347C4707F for ; Thu, 27 May 2021 11:47:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8752A61090 for ; Thu, 27 May 2021 11:47:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234010AbhE0LtB (ORCPT ); Thu, 27 May 2021 07:49:01 -0400 Received: from mail-ua1-f45.google.com ([209.85.222.45]:36433 "EHLO mail-ua1-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233633AbhE0LtB (ORCPT ); Thu, 27 May 2021 07:49:01 -0400 Received: by mail-ua1-f45.google.com with SMTP id b1so32493uap.3; Thu, 27 May 2021 04:47:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=MsBQ4Q5uVxLNj8Ul/iePVuRBGV+cnzR1jbtuFYV4EZ0=; b=c0xvo/JwuuRRb2SXO15WqxPEdsAs5UT3RMNLcEvjd4ANfpvCYlIMqg9gYsTnCW5cv1 B/hupkCskdlceEdUTfnUfdj5hjUanrgH5S4+8gzd18yNrE+aP1okhkYj6SqPLNw4x/gj ughhwUePLbr9/4F45vnytGCsn7x7UQmNLnyz0jaLZIZ2NUE5vw1pzjM+2z0RF4fBdAOc Um6juaAnnCmYi5gB3ilBCkI7eJ5Dn6BdSIg/iGgWKMLG9Su/OKFg3+6ZNGLl5ItDjGxh N3kHaqpRMRHLkW7MGGqwjznn1mB3XJTKBN6qPSu+M55O0iyiL/ZV7WtBB090iAwmq/+x 2sug== X-Gm-Message-State: AOAM5334IE3kxh0ucnirhq51BqIOcXkpe4rZpDpNPl5uO+9juDjlkuHh GKIkvLgpTVL04XK4dGfdWfbBlq3TyDjP1nzLb7K3CY40 X-Google-Smtp-Source: ABdhPJxtpCZMaXr7F6D5isqhbntEmor5OBA8Rb5CQorqKhpEyu5WxZJa8xiG/V/zm1UfZsM+AFHfaWPqHA8At/PLQmI= X-Received: by 2002:ab0:2a8b:: with SMTP id h11mr1643377uar.4.1622116047643; Thu, 27 May 2021 04:47:27 -0700 (PDT) MIME-Version: 1.0 References: <20210514192218.13022-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20210514192218.13022-5-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Thu, 27 May 2021 13:47:15 +0200 Message-ID: Subject: Re: [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L,LC} for the new RZ/G2{L,LC} SoC's To: "Lad, Prabhakar" Cc: Lad Prabhakar , Rob Herring , Magnus Damm , Michael Turquette , Stephen Boyd , Greg Kroah-Hartman , Catalin Marinas , Will Deacon , Jiri Slaby , Philipp Zabel , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Kernel Mailing List , Linux-Renesas , linux-clk , "open list:SERIAL DRIVERS" , Linux ARM , Biju Das Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hi Prabhakar, On Fri, May 21, 2021 at 7:21 PM Lad, Prabhakar wrote: > On Fri, May 21, 2021 at 2:25 PM Geert Uytterhoeven wrote: > > On Fri, May 14, 2021 at 9:23 PM Lad Prabhakar > > wrote: > > > Add ARCH_R9A07G044{L,LC} as a configuration symbol for the new Renesas > > > RZ/G2{L,LC} SoC's. > > > > > > Signed-off-by: Lad Prabhakar > > > Reviewed-by: Biju Das > > > > Thanks for your patch! > > > > > --- a/drivers/soc/renesas/Kconfig > > > +++ b/drivers/soc/renesas/Kconfig > > > @@ -279,6 +279,16 @@ config ARCH_R8A774B1 > > > help > > > This enables support for the Renesas RZ/G2N SoC. > > > > > > +config ARCH_R9A07G044L > > > + bool "ARM64 Platform support for RZ/G2L SoC" > > > > Please drop the "SoC", for consistency with other entries. > > > Oops will do that. > > > > + help > > > + This enables support for the Renesas RZ/G2L SoC. > > > + > > > +config ARCH_R9A07G044LC > > > + bool "ARM64 Platform support for RZ/G2LC SoC" > > > > Likewise. > > > will do. > > > > + help > > > + This enables support for the Renesas RZ/G2LC SoC. > > > + > > > endif # ARM64 > > > > Given LSI DEVID is the same, do we need both, or can we do with a > > single ARCH_R9A07G044? > > > The reason behind adding separate configs was in case if we wanted to > just build an image for RZ/G2L and not RZ/G2LC this would increase > image size and also build unneeded dtb's. How would it increase image size? I understand clock and pin control are the same blocks. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds