From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Chris Brandt <chris.brandt@renesas.com>
Cc: Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-spi <linux-spi@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
linux-clk <linux-clk@vger.kernel.org>,
Mason Yang <masonccyang@mxic.com.tw>,
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Subject: Re: [PATCH v2 2/6] dt-bindings: spi: Document Renesas SPIBSC bindings
Date: Mon, 9 Dec 2019 15:09:27 +0100 [thread overview]
Message-ID: <CAMuHMdXW6_tCcx_DE66qBSTK8XmWyWm82ZD6h-N5YX_+xcvBtw@mail.gmail.com> (raw)
In-Reply-To: <20191206134202.18784-3-chris.brandt@renesas.com>
Hi Chris,
On Fri, Dec 6, 2019 at 2:43 PM Chris Brandt <chris.brandt@renesas.com> wrote:
> Document the bindings used by the Renesas SPI bus space controller.
>
> Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
> ---
> v2:
> * change to YAML format
> * add interrupts property
> * Used more terms directly from the hardware manual
Thanks for the update!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/renesas,spibsc.yaml
> @@ -0,0 +1,115 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/renesas,spibsc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas SPI Bus Space Controller (SPIBSC) Device Tree Bindings
> +
> +description: |
> + Otherwise referred to as the "SPI Multi I/O Bus Controller" in SoC hardware
> + manuals. This controller was designed specifically for accessing Serial flash
> + devices such as SPI Flash, HyperFlash and OctaFlash. The HW can operate in two
> + modes. One mode allows for normal byte by byte access (refereed to as
> + "Manual Mode"). The other mode allows for direct memory mapped access (read
> + only) to the flash area by the CPU (refereed to as "External Address Space
> + Read Mode").
> +
> +allOf:
> + - $ref: spi-controller.yaml#
> +
> +maintainers:
> + - Chris Brandt <chris.brandt@renesas.com>
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - renesas,r7s72100-spibsc # RZ/A1
> + - renesas,r7s9210-spibsc # RZ/A2
> +
> + reg:
> + minItems: 2
> + maxItems: 2
> + items:
> + - description: Registers
> + - description: Memory Mapped Address Space
The second one is not needed, if you would add "ranges" for the
memory-mapped mode.
> +
> + interrupts:
> + description: Some HW versions do not contain interrupts
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + flash:
> + description: |
> + (Optional) In order to use the HW for R/W access ("Manual Mode"), a "flash"
> + subnode must be present with a "compatible" property that contains
> + "jedec,spi-nor". If a spi-nor property is not found, the HW is assumed to be
> + already operating in "External Address Space Read Mode".
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - '#address-cells'
> + - '#size-cells'
I would make the flash subnode mandatory.
> +
> +examples:
> + - |
> + # This example is for "Manual Mode"
> + spibsc: spi@1f800000 {
> + compatible = "renesas,r7s9210-spibsc";
> + reg = <0x1f800000 0x100>, <0x20000000 0x10000000>;
> + clocks = <&cpg CPG_MOD 83>;
> + power-domains = <&cpg>;
> + interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <40000000>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@0000000 {
> + label = "u-boot";
> + reg = <0x00000000 0x80000>;
> + };
> + };
> + };
> +
> + # This example is for "External Address Space Read Mode"
> + spibsc: spi@1f800000 {
> + compatible = "renesas,r7s9210-spibsc";
> + reg = <0x1f800000 0x100>, <0x20000000 0x10000000>;
> + clocks = <&cpg CPG_MOD 83>;
> + power-domains = <&cpg>;
> + interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + flash@20000000 {
This does not describe the hardware topology: the flash node should be
a subnode of the spibsc node, as it relies on the spibsc being clocked.
I think when using:
spibsc: spi@1f800000 {
compatible = "renesas,r7s9210-spibsc", "simple-pm-bus";
reg = <0x1f800000 0x100>;
clocks = <&cpg CPG_MOD 83>;
power-domains = <&cpg>;
interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x20000000 0x10000000>;
flash@0 {
...
};
};
and applying "[PATCH] mtd: maps: physmap: Add minimal Runtime PM
support"[1], the memory-mapped case should work, without your spibsc
driver.
Of course, you still need your driver for using the FLASH in SPI mode.
> + compatible = "mtd-rom";
> + probe-type = "direct-mapped";
> + reg = <0x20000000 0x4000000>;
> + bank-width = <4>;
> + device-width = <1>;
> + #address-cells = <1>;
> + #size-cells = <1>;
1> +
> + partition@80000 {
> + label ="uboot_env";
> + reg = <0x00080000 0x010000>;
> + read-only;
> + };
> + };
[1] https://lore.kernel.org/linux-mtd/20191209134823.13330-1-geert+renesas@glider.be/
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2019-12-09 14:09 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-06 13:41 [PATCH v2 0/6] spi: Add Renesas SPIBSC controller Chris Brandt
2019-12-06 13:41 ` [PATCH v2 1/6] spi: Add SPIBSC driver Chris Brandt
2019-12-12 19:36 ` Sergei Shtylyov
2019-12-12 20:19 ` Chris Brandt
2019-12-13 10:01 ` Geert Uytterhoeven
2019-12-13 14:45 ` Chris Brandt
2019-12-13 14:48 ` Geert Uytterhoeven
2019-12-13 19:37 ` Sergei Shtylyov
2019-12-13 18:36 ` Sergei Shtylyov
2019-12-13 19:40 ` Sergei Shtylyov
2019-12-13 20:43 ` Chris Brandt
2019-12-16 18:47 ` Sergei Shtylyov
2019-12-06 13:41 ` [PATCH v2 2/6] dt-bindings: spi: Document Renesas SPIBSC bindings Chris Brandt
2019-12-09 14:09 ` Geert Uytterhoeven [this message]
2019-12-09 15:45 ` Chris Brandt
2019-12-09 19:34 ` Geert Uytterhoeven
2019-12-10 20:07 ` Sergei Shtylyov
2019-12-10 20:17 ` Geert Uytterhoeven
2019-12-10 20:33 ` Chris Brandt
2019-12-10 20:23 ` Chris Brandt
2019-12-06 13:41 ` [PATCH v2 3/6] clk: renesas: r7s9210: Add SPIBSC clock Chris Brandt
2019-12-06 18:40 ` Sergei Shtylyov
2019-12-06 19:49 ` Chris Brandt
2019-12-20 14:38 ` Geert Uytterhoeven
2019-12-20 14:50 ` Chris Brandt
2019-12-06 13:42 ` [PATCH v2 4/6] ARM: dts: r7s72100: Add SPIBSC devices Chris Brandt
2019-12-06 13:42 ` [PATCH v2 5/6] ARM: dts: r7s9210: Add SPIBSC device Chris Brandt
2019-12-06 13:42 ` [PATCH v2 6/6] ARM: dts: gr-peach: Enable SPIBSC Chris Brandt
2019-12-07 20:28 ` [PATCH v2 0/6] spi: Add Renesas SPIBSC controller Sergei Shtylyov
2019-12-09 15:10 ` Chris Brandt
2019-12-11 19:09 ` Sergei Shtylyov
2019-12-12 14:29 ` Chris Brandt
2019-12-12 15:28 ` Mark Brown
2019-12-12 16:53 ` Chris Brandt
2019-12-12 17:13 ` Mark Brown
2019-12-12 17:25 ` Chris Brandt
2019-12-16 15:21 ` Mark Brown
2019-12-16 20:31 ` Sergei Shtylyov
2019-12-16 22:21 ` Chris Brandt
2019-12-17 19:30 ` Sergei Shtylyov
2019-12-17 20:26 ` Geert Uytterhoeven
2019-12-19 16:57 ` Chris Brandt
2019-12-19 19:01 ` Sergei Shtylyov
2019-12-19 21:04 ` Chris Brandt
2019-12-20 1:45 ` masonccyang
2019-12-20 7:55 ` Geert Uytterhoeven
2019-12-24 16:58 ` Sergei Shtylyov
2019-12-27 0:58 ` Mark Brown
2019-12-17 19:44 ` Sergei Shtylyov
2019-12-18 8:09 ` Boris Brezillon
2019-12-19 16:32 ` Chris Brandt
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