From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8FC6C433ED for ; Fri, 21 May 2021 13:26:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AE0DA61164 for ; Fri, 21 May 2021 13:26:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235462AbhEUN1c (ORCPT ); Fri, 21 May 2021 09:27:32 -0400 Received: from mail-vs1-f43.google.com ([209.85.217.43]:43584 "EHLO mail-vs1-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231601AbhEUN1K (ORCPT ); Fri, 21 May 2021 09:27:10 -0400 Received: by mail-vs1-f43.google.com with SMTP id n1so8885179vsr.10; Fri, 21 May 2021 06:25:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=b6PugjoAaJt+l80R28svGGy/E47HBQC4C74ypfx68hc=; b=Vc2UnRAIcP6SYvBeDiK3g4lY7FIZTNgxxtW3XQGSmGt4Kv4PruyirVoC5fxtv+C4cb fwcouNbSvmTjiNasd24LjiulBcavV8lzNVtKy9BSLKMXciF7xXSDlZsIu4cUKx/ii6Gw qtsLTPTBbKkzss/pPx9RAgw6RRChNNgZ8aAS0FmUO12wXG3o9Akx05rEXeY6/lznpZbR u9S0okOCVQWeU/NRlbd7wAVxtk5XQzK7j0/xpTfXV4xDvvHVL+uUcQ04fz3+hbBdgXVU XWCNevrM+2DEU21tceMrflAQDC3rmsHAP+TuM9hQUxgSgxz/Bh1uhPoA0zQGM67uD0R/ ZMUw== X-Gm-Message-State: AOAM532ksfyL8E/qqqQM6GnqPVX3sQJKchQSAgHmG45/GKIxCQ1L6llr a+AOgBKn1hEz/qEUBfBd+heNlkiy5DIDfJj6CaY= X-Google-Smtp-Source: ABdhPJxEH3kZKLf8SMB6v9o7mwBYSIk9ws1qQLFEyBIXhU52GxAxOiTv0cchQy/EJ/jvaJlpuo0OcIdXm94XTK/+Kpg= X-Received: by 2002:a67:fb52:: with SMTP id e18mr10648951vsr.18.1621603546669; Fri, 21 May 2021 06:25:46 -0700 (PDT) MIME-Version: 1.0 References: <20210514192218.13022-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20210514192218.13022-7-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20210514192218.13022-7-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Fri, 21 May 2021 15:25:34 +0200 Message-ID: Subject: Re: [PATCH 06/16] dt-bindings: arm: renesas,prr: Add new compatible string for RZ/G{L,LC,UL} To: Lad Prabhakar Cc: Rob Herring , Magnus Damm , Michael Turquette , Stephen Boyd , Greg Kroah-Hartman , Catalin Marinas , Will Deacon , Jiri Slaby , Philipp Zabel , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Kernel Mailing List , Linux-Renesas , linux-clk , "open list:SERIAL DRIVERS" , Linux ARM , Biju Das , Prabhakar Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hi Prabhakar, On Fri, May 14, 2021 at 9:23 PM Lad Prabhakar wrote: > RZ/G2{L,LC,UL} SoC's have LSI_DEVID register to retrieve SoC product and > revision information. > > RZ/G{L,LC,UL} SoC's have 28-bit product-id compared to other R-Car and > RZ/G2{E,H,M,N} SoC's hence a new compatible string "renesas,devid" is > added. > > Signed-off-by: Lad Prabhakar > Reviewed-by: Biju Das Thanks for your patch! > --- a/Documentation/devicetree/bindings/arm/renesas,prr.yaml > +++ b/Documentation/devicetree/bindings/arm/renesas,prr.yaml > @@ -12,14 +12,16 @@ maintainers: > > description: | > Most Renesas ARM SoCs have a Product Register or Boundary Scan ID > - Register that allows to retrieve SoC product and revision information. > - If present, a device node for this register should be added. > + Register or LSI Device ID Register that allows to retrieve SoC product > + and revision information. If present, a device node for this register > + should be added. Note that this register does not seem to be documented, so I have to trust you on this. However, from looking at the LSI DEVID register address, this does not seem to be a lone register (like the Product Register on other SoCs), but to be part of the System Controller (SYSC). Hence I think there should be separate bindings for the whole SYSC block instead. You can still read the LSI DEVID register from renesas_soc_init(), using the SYSC node. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds