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* [PATCH v2 0/5] Mediatek MT8192 clock support
@ 2020-07-29  8:44 Weiyi Lu
  2020-07-29  8:44 ` [PATCH v2 1/5] dt-bindings: ARM: Mediatek: Document bindings for MT8192 Weiyi Lu
                   ` (4 more replies)
  0 siblings, 5 replies; 17+ messages in thread
From: Weiyi Lu @ 2020-07-29  8:44 UTC (permalink / raw)
  To: Matthias Brugger, Rob Herring, Stephen Boyd, Nicolas Boichat
  Cc: James Liao, linux-arm-kernel, linux-kernel, linux-mediatek,
	linux-clk, srv_heupstream, Weiyi Lu, Wendell Lin

This series is based on v5.8-rc1

changes since v1:
- fix asymmetrical control of PLL
- have en_mask used as divider enable mask on all MediaTek SoC

Weiyi Lu (5):
  dt-bindings: ARM: Mediatek: Document bindings for MT8192
  clk: mediatek: Add dt-bindings for MT8192 clocks
  clk: mediatek: Fix asymmetrical PLL enable and disable control
  clk: mediatek: Add configurable enable control to mtk_pll_data
  clk: mediatek: Add MT8192 clock support

 .../arm/mediatek/mediatek,apmixedsys.txt      |    1 +
 .../bindings/arm/mediatek/mediatek,audsys.txt |    1 +
 .../arm/mediatek/mediatek,camsys-raw.yaml     |   40 +
 .../bindings/arm/mediatek/mediatek,camsys.txt |    1 +
 .../bindings/arm/mediatek/mediatek,imgsys.txt |    2 +
 .../arm/mediatek/mediatek,imp_iic_wrap.yaml   |   43 +
 .../arm/mediatek/mediatek,infracfg.txt        |    1 +
 .../bindings/arm/mediatek/mediatek,ipesys.txt |    1 +
 .../arm/mediatek/mediatek,mdpsys.yaml         |   38 +
 .../bindings/arm/mediatek/mediatek,mfgcfg.txt |    1 +
 .../bindings/arm/mediatek/mediatek,mmsys.txt  |    1 +
 .../bindings/arm/mediatek/mediatek,msdc.yaml  |   39 +
 .../arm/mediatek/mediatek,pericfg.yaml        |    1 +
 .../arm/mediatek/mediatek,scp-adsp.yaml       |   38 +
 .../arm/mediatek/mediatek,topckgen.txt        |    1 +
 .../arm/mediatek/mediatek,vdecsys-soc.yaml    |   38 +
 .../arm/mediatek/mediatek,vdecsys.txt         |    1 +
 .../arm/mediatek/mediatek,vencsys.txt         |    1 +
 drivers/clk/mediatek/Kconfig                  |  146 ++
 drivers/clk/mediatek/Makefile                 |   24 +
 drivers/clk/mediatek/clk-mt2701.c             |   26 +-
 drivers/clk/mediatek/clk-mt2712.c             |   30 +-
 drivers/clk/mediatek/clk-mt6765.c             |   20 +-
 drivers/clk/mediatek/clk-mt6779.c             |   24 +-
 drivers/clk/mediatek/clk-mt6797.c             |   20 +-
 drivers/clk/mediatek/clk-mt7622.c             |   18 +-
 drivers/clk/mediatek/clk-mt7629.c             |   12 +-
 drivers/clk/mediatek/clk-mt8173.c             |   42 +-
 drivers/clk/mediatek/clk-mt8183.c             |   22 +-
 drivers/clk/mediatek/clk-mt8192-aud.c         |  150 ++
 drivers/clk/mediatek/clk-mt8192-cam.c         |   69 +
 drivers/clk/mediatek/clk-mt8192-cam_rawa.c    |   56 +
 drivers/clk/mediatek/clk-mt8192-cam_rawb.c    |   56 +
 drivers/clk/mediatek/clk-mt8192-cam_rawc.c    |   56 +
 drivers/clk/mediatek/clk-mt8192-img.c         |   57 +
 drivers/clk/mediatek/clk-mt8192-img2.c        |   59 +
 .../clk/mediatek/clk-mt8192-imp_iic_wrap_c.c  |   61 +
 .../clk/mediatek/clk-mt8192-imp_iic_wrap_e.c  |   55 +
 .../clk/mediatek/clk-mt8192-imp_iic_wrap_n.c  |   57 +
 .../clk/mediatek/clk-mt8192-imp_iic_wrap_s.c  |   59 +
 .../clk/mediatek/clk-mt8192-imp_iic_wrap_w.c  |   55 +
 .../clk/mediatek/clk-mt8192-imp_iic_wrap_ws.c |   59 +
 drivers/clk/mediatek/clk-mt8192-ipe.c         |   61 +
 drivers/clk/mediatek/clk-mt8192-mdp.c         |   89 +
 drivers/clk/mediatek/clk-mt8192-mfg.c         |   54 +
 drivers/clk/mediatek/clk-mt8192-mm.c          |  108 ++
 drivers/clk/mediatek/clk-mt8192-msdc.c        |   54 +
 drivers/clk/mediatek/clk-mt8192-msdc_top.c    |   83 +
 drivers/clk/mediatek/clk-mt8192-scp_adsp.c    |   55 +
 drivers/clk/mediatek/clk-mt8192-vdec.c        |   81 +
 drivers/clk/mediatek/clk-mt8192-vdec_soc.c    |   86 +
 drivers/clk/mediatek/clk-mt8192-venc.c        |   57 +
 drivers/clk/mediatek/clk-mt8192.c             | 1549 +++++++++++++++++
 drivers/clk/mediatek/clk-mtk.h                |    2 +
 drivers/clk/mediatek/clk-mux.h                |   15 +
 drivers/clk/mediatek/clk-pll.c                |   20 +-
 include/dt-bindings/clock/mt8192-clk.h        |  593 +++++++
 57 files changed, 4284 insertions(+), 105 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,imp_iic_wrap.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdpsys.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,scp-adsp.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml
 create mode 100644 drivers/clk/mediatek/clk-mt8192-aud.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-cam.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-cam_rawa.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-cam_rawb.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-cam_rawc.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-img.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-img2.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_c.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_e.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_n.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_s.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_w.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_ws.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-ipe.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-mdp.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-mfg.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-mm.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-msdc.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-msdc_top.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-scp_adsp.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-vdec.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-vdec_soc.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-venc.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192.c
 create mode 100644 include/dt-bindings/clock/mt8192-clk.h

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v2 1/5] dt-bindings: ARM: Mediatek: Document bindings for MT8192
  2020-07-29  8:44 [PATCH v2 0/5] Mediatek MT8192 clock support Weiyi Lu
@ 2020-07-29  8:44 ` Weiyi Lu
  2020-07-29  9:53   ` Enric Balletbo Serra
  2020-07-29  8:44 ` [PATCH v2 2/5] clk: mediatek: Add dt-bindings for MT8192 clocks Weiyi Lu
                   ` (3 subsequent siblings)
  4 siblings, 1 reply; 17+ messages in thread
From: Weiyi Lu @ 2020-07-29  8:44 UTC (permalink / raw)
  To: Matthias Brugger, Rob Herring, Stephen Boyd, Nicolas Boichat
  Cc: James Liao, linux-arm-kernel, linux-kernel, linux-mediatek,
	linux-clk, srv_heupstream, Weiyi Lu, Wendell Lin

This patch adds the binding documentation for apmixedsys, audsys,
camsys-raw, camsys, imgsys, imp_iic_wrap, infracfg, ipesys, mdpsys,
mfgcfg, mmsys, msdc, pericfg, scp-adsp, topckgen, vdecsys-soc,
vdecsys and vencsys for Mediatek MT8192.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
 .../bindings/arm/mediatek/mediatek,apmixedsys.txt  |  1 +
 .../bindings/arm/mediatek/mediatek,audsys.txt      |  1 +
 .../bindings/arm/mediatek/mediatek,camsys-raw.yaml | 40 ++++++++++++++++++++
 .../bindings/arm/mediatek/mediatek,camsys.txt      |  1 +
 .../bindings/arm/mediatek/mediatek,imgsys.txt      |  2 +
 .../arm/mediatek/mediatek,imp_iic_wrap.yaml        | 43 ++++++++++++++++++++++
 .../bindings/arm/mediatek/mediatek,infracfg.txt    |  1 +
 .../bindings/arm/mediatek/mediatek,ipesys.txt      |  1 +
 .../bindings/arm/mediatek/mediatek,mdpsys.yaml     | 38 +++++++++++++++++++
 .../bindings/arm/mediatek/mediatek,mfgcfg.txt      |  1 +
 .../bindings/arm/mediatek/mediatek,mmsys.txt       |  1 +
 .../bindings/arm/mediatek/mediatek,msdc.yaml       | 39 ++++++++++++++++++++
 .../bindings/arm/mediatek/mediatek,pericfg.yaml    |  1 +
 .../bindings/arm/mediatek/mediatek,scp-adsp.yaml   | 38 +++++++++++++++++++
 .../bindings/arm/mediatek/mediatek,topckgen.txt    |  1 +
 .../arm/mediatek/mediatek,vdecsys-soc.yaml         | 38 +++++++++++++++++++
 .../bindings/arm/mediatek/mediatek,vdecsys.txt     |  1 +
 .../bindings/arm/mediatek/mediatek,vencsys.txt     |  1 +
 18 files changed, 249 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,imp_iic_wrap.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdpsys.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,scp-adsp.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
index bd7a0fa..6942ad4 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
@@ -17,6 +17,7 @@ Required Properties:
 	- "mediatek,mt8135-apmixedsys"
 	- "mediatek,mt8173-apmixedsys"
 	- "mediatek,mt8183-apmixedsys", "syscon"
+	- "mediatek,mt8192-apmixedsys", "syscon"
 	- "mediatek,mt8516-apmixedsys"
 - #clock-cells: Must be 1
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
index 38309db..fdcb267 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
@@ -12,6 +12,7 @@ Required Properties:
 	- "mediatek,mt7622-audsys", "syscon"
 	- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
 	- "mediatek,mt8183-audiosys", "syscon"
+	- "mediatek,mt8192-audsys", "syscon"
 	- "mediatek,mt8516-audsys", "syscon"
 - #clock-cells: Must be 1
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml
new file mode 100644
index 0000000..db6f425
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,camsys-raw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek CAMSYS RAW Controller
+
+maintainers:
+  - Weiyi Lu <weiyi.lu@mediatek.com>
+
+description:
+  The Mediatek camsys raw controller provides various clocks to the system.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt8192-camsys_rawa
+          - mediatek,mt8192-camsys_rawb
+          - mediatek,mt8192-camsys_rawc
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    camsys_rawa: camsys_rawa@1a04f000 {
+        compatible = "mediatek,mt8192-camsys_rawa", "syscon";
+        reg = <0 0x1a04f000 0 0x1000>;
+        #clock-cells = <1>;
+    };
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
index a0ce820..0082f21 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
@@ -9,6 +9,7 @@ Required Properties:
 	- "mediatek,mt6765-camsys", "syscon"
 	- "mediatek,mt6779-camsys", "syscon"
 	- "mediatek,mt8183-camsys", "syscon"
+	- "mediatek,mt8192-camsys", "syscon"
 - #clock-cells: Must be 1
 
 The camsys controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
index 1e1f007..b4312d1 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
@@ -14,6 +14,8 @@ Required Properties:
 	- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
 	- "mediatek,mt8173-imgsys", "syscon"
 	- "mediatek,mt8183-imgsys", "syscon"
+	- "mediatek,mt8192-imgsys", "syscon"
+	- "mediatek,mt8192-imgsys2", "syscon"
 - #clock-cells: Must be 1
 
 The imgsys controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imp_iic_wrap.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imp_iic_wrap.yaml
new file mode 100644
index 0000000..2af6f98
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imp_iic_wrap.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,imp_iic_wrap.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek IMP I2C Wrapper Controller
+
+maintainers:
+  - Weiyi Lu <weiyi.lu@mediatek.com>
+
+description:
+  The Mediatek imp i2c wrapper controller provides various clocks to the system.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt8192-imp_iic_wrap_c
+          - mediatek,mt8192-imp_iic_wrap_e
+          - mediatek,mt8192-imp_iic_wrap_s
+          - mediatek,mt8192-imp_iic_wrap_ws
+          - mediatek,mt8192-imp_iic_wrap_w
+          - mediatek,mt8192-imp_iic_wrap_n
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    imp_iic_wrap_c@11007000 {
+        compatible = "mediatek,mt8192-imp_iic_wrap_c", "syscon";
+        reg = <0 0x11007000 0 0x1000>;
+        #clock-cells = <1>;
+    };
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
index 49a968b..ba5e781 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
@@ -18,6 +18,7 @@ Required Properties:
 	- "mediatek,mt8135-infracfg", "syscon"
 	- "mediatek,mt8173-infracfg", "syscon"
 	- "mediatek,mt8183-infracfg", "syscon"
+	- "mediatek,mt8192-infracfg", "syscon"
 	- "mediatek,mt8516-infracfg", "syscon"
 - #clock-cells: Must be 1
 - #reset-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt
index 2ce889b..9cd1035 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt
@@ -7,6 +7,7 @@ Required Properties:
 
 - compatible: Should be one of:
 	- "mediatek,mt6779-ipesys", "syscon"
+	- "mediatek,mt8192-ipesys", "syscon"
 - #clock-cells: Must be 1
 
 The ipesys controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mdpsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mdpsys.yaml
new file mode 100644
index 0000000..88698a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mdpsys.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mdpsys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MDPSYS Controller
+
+maintainers:
+  - Weiyi Lu <weiyi.lu@mediatek.com>
+
+description:
+  The Mediatek mdpsys controller provides various clocks to the system.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt8192-mdpsys
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    mdpsys: mdpsys@1f000000 {
+        compatible = "mediatek,mt8192-mdpsys", "syscon";
+        reg = <0 0x1f000000 0 0x1000>;
+        #clock-cells = <1>;
+    };
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
index ad5f9d2..fc1ce61 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
@@ -9,6 +9,7 @@ Required Properties:
 	- "mediatek,mt2712-mfgcfg", "syscon"
 	- "mediatek,mt6779-mfgcfg", "syscon"
 	- "mediatek,mt8183-mfgcfg", "syscon"
+	- "mediatek,mt8192-mfgcfg", "syscon"
 - #clock-cells: Must be 1
 
 The mfgcfg controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
index d8c9108..81fa345 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
@@ -15,6 +15,7 @@ Required Properties:
 	- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
 	- "mediatek,mt8173-mmsys", "syscon"
 	- "mediatek,mt8183-mmsys", "syscon"
+	- "mediatek,mt8192-mmsys", "syscon"
 - #clock-cells: Must be 1
 
 For the clock control, the mmsys controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml
new file mode 100644
index 0000000..23ad419e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,msdc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MSDC Controller
+
+maintainers:
+  - Weiyi Lu <weiyi.lu@mediatek.com>
+
+description:
+  The Mediatek msdc controller provides various clocks to the system.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt8192-msdc
+          - mediatek,mt8192-msdc_top
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    msdc: msdc@11f60000 {
+        compatible = "mediatek,mt8192-msdc", "syscon";
+        reg = <0 0x11f60000 0 0x1000>;
+        #clock-cells = <1>;
+    };
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
index e271c46..c2e106c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
@@ -26,6 +26,7 @@ properties:
           - mediatek,mt8135-pericfg
           - mediatek,mt8173-pericfg
           - mediatek,mt8183-pericfg
+          - mediatek,mt8192-pericfg
           - mediatek,mt8516-pericfg
         - const: syscon
       - items:
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,scp-adsp.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,scp-adsp.yaml
new file mode 100644
index 0000000..25cc59f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,scp-adsp.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,scp-adsp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek SCP ADSP Controller
+
+maintainers:
+  - Weiyi Lu <weiyi.lu@mediatek.com>
+
+description:
+  The Mediatek scp adsp controller provides various clocks to the system.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt8192-scp_adsp
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    scp_adsp: scp_adsp@10720000 {
+        compatible = "mediatek,mt8192-scp_adsp", "syscon";
+        reg = <0x10720000 0x1000>;
+        #clock-cells = <1>;
+    };
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
index 9b0394c..c480278 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
@@ -17,6 +17,7 @@ Required Properties:
 	- "mediatek,mt8135-topckgen"
 	- "mediatek,mt8173-topckgen"
 	- "mediatek,mt8183-topckgen", "syscon"
+	- "mediatek,mt8192-topckgen", "syscon"
 	- "mediatek,mt8516-topckgen"
 - #clock-cells: Must be 1
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml
new file mode 100644
index 0000000..5cb8740
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,vdecsys-soc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek VDECSYS SOC Controller
+
+maintainers:
+  - Weiyi Lu <weiyi.lu@mediatek.com>
+
+description:
+  The Mediatek vdecsys soc controller provides various clocks to the system.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt8192-vdecsys_soc
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    vdecsys_soc: vdecsys_soc@1600f000 {
+        compatible = "mediatek,mt8192-vdecsys_soc", "syscon";
+        reg = <0 0x1600f000 0 0x1000>;
+        #clock-cells = <1>;
+    };
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
index 7894558..ee679e0 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
@@ -13,6 +13,7 @@ Required Properties:
 	- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
 	- "mediatek,mt8173-vdecsys", "syscon"
 	- "mediatek,mt8183-vdecsys", "syscon"
+	- "mediatek,mt8192-vdecsys", "syscon"
 - #clock-cells: Must be 1
 
 The vdecsys controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
index 6a6a14e..d22de01 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
@@ -11,6 +11,7 @@ Required Properties:
 	- "mediatek,mt6797-vencsys", "syscon"
 	- "mediatek,mt8173-vencsys", "syscon"
 	- "mediatek,mt8183-vencsys", "syscon"
+	- "mediatek,mt8192-vencsys", "syscon"
 - #clock-cells: Must be 1
 
 The vencsys controller uses the common clk binding from
-- 
1.8.1.1.dirty

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v2 2/5] clk: mediatek: Add dt-bindings for MT8192 clocks
  2020-07-29  8:44 [PATCH v2 0/5] Mediatek MT8192 clock support Weiyi Lu
  2020-07-29  8:44 ` [PATCH v2 1/5] dt-bindings: ARM: Mediatek: Document bindings for MT8192 Weiyi Lu
@ 2020-07-29  8:44 ` Weiyi Lu
  2020-07-29  8:44 ` [PATCH v2 3/5] clk: mediatek: Fix asymmetrical PLL enable and disable control Weiyi Lu
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 17+ messages in thread
From: Weiyi Lu @ 2020-07-29  8:44 UTC (permalink / raw)
  To: Matthias Brugger, Rob Herring, Stephen Boyd, Nicolas Boichat
  Cc: James Liao, linux-arm-kernel, linux-kernel, linux-mediatek,
	linux-clk, srv_heupstream, Weiyi Lu, Wendell Lin

Add MT8192 clock dt-bindings, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
 include/dt-bindings/clock/mt8192-clk.h | 593 +++++++++++++++++++++++++++++++++
 1 file changed, 593 insertions(+)
 create mode 100644 include/dt-bindings/clock/mt8192-clk.h

diff --git a/include/dt-bindings/clock/mt8192-clk.h b/include/dt-bindings/clock/mt8192-clk.h
new file mode 100644
index 0000000..0f50844
--- /dev/null
+++ b/include/dt-bindings/clock/mt8192-clk.h
@@ -0,0 +1,593 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8192_H
+#define _DT_BINDINGS_CLK_MT8192_H
+
+/* TOPCKGEN */
+
+#define CLK_TOP_AXI_SEL			0
+#define CLK_TOP_SPM_SEL			1
+#define CLK_TOP_SCP_SEL			2
+#define CLK_TOP_BUS_AXIMEM_SEL		3
+#define CLK_TOP_DISP_SEL		4
+#define CLK_TOP_MDP_SEL			5
+#define CLK_TOP_IMG1_SEL		6
+#define CLK_TOP_IMG2_SEL		7
+#define CLK_TOP_IPE_SEL			8
+#define CLK_TOP_DPE_SEL			9
+#define CLK_TOP_CAM_SEL			10
+#define CLK_TOP_CCU_SEL			11
+#define CLK_TOP_DSP7_SEL		12
+#define CLK_TOP_MFG_REF_SEL		13
+#define CLK_TOP_MFG_PLL_SEL		14
+#define CLK_TOP_CAMTG_SEL		15
+#define CLK_TOP_CAMTG2_SEL		16
+#define CLK_TOP_CAMTG3_SEL		17
+#define CLK_TOP_CAMTG4_SEL		18
+#define CLK_TOP_CAMTG5_SEL		19
+#define CLK_TOP_CAMTG6_SEL		20
+#define CLK_TOP_UART_SEL		21
+#define CLK_TOP_SPI_SEL			22
+#define CLK_TOP_MSDC50_0_H_SEL		23
+#define CLK_TOP_MSDC50_0_SEL		24
+#define CLK_TOP_MSDC30_1_SEL		25
+#define CLK_TOP_MSDC30_2_SEL		26
+#define CLK_TOP_AUDIO_SEL		27
+#define CLK_TOP_AUD_INTBUS_SEL		28
+#define CLK_TOP_PWRAP_ULPOSC_SEL	29
+#define CLK_TOP_ATB_SEL			30
+#define CLK_TOP_SSPM_SEL		31
+#define CLK_TOP_DPI_SEL			32
+#define CLK_TOP_SCAM_SEL		33
+#define CLK_TOP_DISP_PWM_SEL		34
+#define CLK_TOP_USB_TOP_SEL		35
+#define CLK_TOP_SSUSB_XHCI_SEL		36
+#define CLK_TOP_I2C_SEL			37
+#define CLK_TOP_SENINF_SEL		38
+#define CLK_TOP_SENINF1_SEL		39
+#define CLK_TOP_SENINF2_SEL		40
+#define CLK_TOP_SENINF3_SEL		41
+#define CLK_TOP_TL_SEL			42
+#define CLK_TOP_DXCC_SEL		43
+#define CLK_TOP_AUD_ENGEN1_SEL		44
+#define CLK_TOP_AUD_ENGEN2_SEL		45
+#define CLK_TOP_AES_UFSFDE_SEL		46
+#define CLK_TOP_UFS_SEL			47
+#define CLK_TOP_AUD_1_SEL		48
+#define CLK_TOP_AUD_2_SEL		49
+#define CLK_TOP_ADSP_SEL		50
+#define CLK_TOP_DPMAIF_MAIN_SEL		51
+#define CLK_TOP_VENC_SEL		52
+#define CLK_TOP_VDEC_SEL		53
+#define CLK_TOP_CAMTM_SEL		54
+#define CLK_TOP_PWM_SEL			55
+#define CLK_TOP_AUDIO_H_SEL		56
+#define CLK_TOP_SPMI_MST_SEL		57
+#define CLK_TOP_AES_MSDCFDE_SEL		58
+#define CLK_TOP_MCUPM_SEL		59
+#define CLK_TOP_SFLASH_SEL		60
+#define CLK_TOP_APLL_I2S0_M_SEL		61
+#define CLK_TOP_APLL_I2S1_M_SEL		62
+#define CLK_TOP_APLL_I2S2_M_SEL		63
+#define CLK_TOP_APLL_I2S3_M_SEL		64
+#define CLK_TOP_APLL_I2S4_M_SEL		65
+#define CLK_TOP_APLL_I2S5_M_SEL		66
+#define CLK_TOP_APLL_I2S6_M_SEL		67
+#define CLK_TOP_APLL_I2S7_M_SEL		68
+#define CLK_TOP_APLL_I2S8_M_SEL		69
+#define CLK_TOP_APLL_I2S9_M_SEL		70
+#define CLK_TOP_MAINPLL_D3		71
+#define CLK_TOP_MAINPLL_D4		72
+#define CLK_TOP_MAINPLL_D4_D2		73
+#define CLK_TOP_MAINPLL_D4_D4		74
+#define CLK_TOP_MAINPLL_D4_D8		75
+#define CLK_TOP_MAINPLL_D4_D16		76
+#define CLK_TOP_MAINPLL_D5		77
+#define CLK_TOP_MAINPLL_D5_D2		78
+#define CLK_TOP_MAINPLL_D5_D4		79
+#define CLK_TOP_MAINPLL_D5_D8		80
+#define CLK_TOP_MAINPLL_D6		81
+#define CLK_TOP_MAINPLL_D6_D2		82
+#define CLK_TOP_MAINPLL_D6_D4		83
+#define CLK_TOP_MAINPLL_D7		84
+#define CLK_TOP_MAINPLL_D7_D2		85
+#define CLK_TOP_MAINPLL_D7_D4		86
+#define CLK_TOP_MAINPLL_D7_D8		87
+#define CLK_TOP_UNIVPLL_D3		88
+#define CLK_TOP_UNIVPLL_D4		89
+#define CLK_TOP_UNIVPLL_D4_D2		90
+#define CLK_TOP_UNIVPLL_D4_D4		91
+#define CLK_TOP_UNIVPLL_D4_D8		92
+#define CLK_TOP_UNIVPLL_D5		93
+#define CLK_TOP_UNIVPLL_D5_D2		94
+#define CLK_TOP_UNIVPLL_D5_D4		95
+#define CLK_TOP_UNIVPLL_D5_D8		96
+#define CLK_TOP_UNIVPLL_D6		97
+#define CLK_TOP_UNIVPLL_D6_D2		98
+#define CLK_TOP_UNIVPLL_D6_D4		99
+#define CLK_TOP_UNIVPLL_D6_D8		100
+#define CLK_TOP_UNIVPLL_D6_D16		101
+#define CLK_TOP_UNIVPLL_D7		102
+#define CLK_TOP_APLL1			103
+#define CLK_TOP_APLL1_D2		104
+#define CLK_TOP_APLL1_D4		105
+#define CLK_TOP_APLL1_D8		106
+#define CLK_TOP_APLL2			107
+#define CLK_TOP_APLL2_D2		108
+#define CLK_TOP_APLL2_D4		109
+#define CLK_TOP_APLL2_D8		110
+#define CLK_TOP_MMPLL_D4		111
+#define CLK_TOP_MMPLL_D4_D2		112
+#define CLK_TOP_MMPLL_D5		113
+#define CLK_TOP_MMPLL_D5_D2		114
+#define CLK_TOP_MMPLL_D6		115
+#define CLK_TOP_MMPLL_D6_D2		116
+#define CLK_TOP_MMPLL_D7		117
+#define CLK_TOP_MMPLL_D9		118
+#define CLK_TOP_APUPLL			119
+#define CLK_TOP_NPUPLL			120
+#define CLK_TOP_TVDPLL			121
+#define CLK_TOP_TVDPLL_D2		122
+#define CLK_TOP_TVDPLL_D4		123
+#define CLK_TOP_TVDPLL_D8		124
+#define CLK_TOP_TVDPLL_D16		125
+#define CLK_TOP_MSDCPLL			126
+#define CLK_TOP_MSDCPLL_D2		127
+#define CLK_TOP_MSDCPLL_D4		128
+#define CLK_TOP_ULPOSC			129
+#define CLK_TOP_OSC_D2			130
+#define CLK_TOP_OSC_D4			131
+#define CLK_TOP_OSC_D8			132
+#define CLK_TOP_OSC_D10			133
+#define CLK_TOP_OSC_D16			134
+#define CLK_TOP_OSC_D20			135
+#define CLK_TOP_CSW_F26M_D2		136
+#define CLK_TOP_ADSPPLL			137
+#define CLK_TOP_UNIVPLL_192M		138
+#define CLK_TOP_UNIVPLL_192M_D2		139
+#define CLK_TOP_UNIVPLL_192M_D4		140
+#define CLK_TOP_UNIVPLL_192M_D8		141
+#define CLK_TOP_UNIVPLL_192M_D16	142
+#define CLK_TOP_UNIVPLL_192M_D32	143
+#define CLK_TOP_APLL12_DIV0		144
+#define CLK_TOP_APLL12_DIV1		145
+#define CLK_TOP_APLL12_DIV2		146
+#define CLK_TOP_APLL12_DIV3		147
+#define CLK_TOP_APLL12_DIV4		148
+#define CLK_TOP_APLL12_DIVB		149
+#define CLK_TOP_APLL12_DIV5		150
+#define CLK_TOP_APLL12_DIV6		151
+#define CLK_TOP_APLL12_DIV7		152
+#define CLK_TOP_APLL12_DIV8		153
+#define CLK_TOP_APLL12_DIV9		154
+#define CLK_TOP_SSUSB_TOP_REF		155
+#define CLK_TOP_SSUSB_PHY_REF		156
+#define CLK_TOP_NR_CLK			157
+
+/* INFRACFG */
+
+#define CLK_INFRA_PMIC_TMR		0
+#define CLK_INFRA_PMIC_AP		1
+#define CLK_INFRA_PMIC_MD		2
+#define CLK_INFRA_PMIC_CONN		3
+#define CLK_INFRA_SCPSYS		4
+#define CLK_INFRA_SEJ			5
+#define CLK_INFRA_APXGPT		6
+#define CLK_INFRA_MCUPM			7
+#define CLK_INFRA_GCE			8
+#define CLK_INFRA_GCE2			9
+#define CLK_INFRA_THERM			10
+#define CLK_INFRA_I2C0			11
+#define CLK_INFRA_AP_DMA_PSEUDO		12
+#define CLK_INFRA_I2C2			13
+#define CLK_INFRA_I2C3			14
+#define CLK_INFRA_PWM_H			15
+#define CLK_INFRA_PWM1			16
+#define CLK_INFRA_PWM2			17
+#define CLK_INFRA_PWM3			18
+#define CLK_INFRA_PWM4			19
+#define CLK_INFRA_PWM			20
+#define CLK_INFRA_UART0			21
+#define CLK_INFRA_UART1			22
+#define CLK_INFRA_UART2			23
+#define CLK_INFRA_UART3			24
+#define CLK_INFRA_GCE_26M		25
+#define CLK_INFRA_CQ_DMA_FPC		26
+#define CLK_INFRA_BTIF			27
+#define CLK_INFRA_SPI0			28
+#define CLK_INFRA_MSDC0			29
+#define CLK_INFRA_MSDC1			30
+#define CLK_INFRA_MSDC2			31
+#define CLK_INFRA_MSDC0_SRC		32
+#define CLK_INFRA_GCPU			33
+#define CLK_INFRA_TRNG			34
+#define CLK_INFRA_AUXADC		35
+#define CLK_INFRA_CPUM			36
+#define CLK_INFRA_CCIF1_AP		37
+#define CLK_INFRA_CCIF1_MD		38
+#define CLK_INFRA_AUXADC_MD		39
+#define CLK_INFRA_PCIE_TL_26M		40
+#define CLK_INFRA_MSDC1_SRC		41
+#define CLK_INFRA_MSDC2_SRC		42
+#define CLK_INFRA_PCIE_TL_96M		43
+#define CLK_INFRA_PCIE_PL_P_250M	44
+#define CLK_INFRA_DEVICE_APC		45
+#define CLK_INFRA_CCIF_AP		46
+#define CLK_INFRA_DEBUGSYS		47
+#define CLK_INFRA_AUDIO			48
+#define CLK_INFRA_CCIF_MD		49
+#define CLK_INFRA_DXCC_SEC_CORE		50
+#define CLK_INFRA_DXCC_AO		51
+#define CLK_INFRA_DBG_TRACE		52
+#define CLK_INFRA_DEVMPU_B		53
+#define CLK_INFRA_DRAMC_F26M		54
+#define CLK_INFRA_IRTX			55
+#define CLK_INFRA_SSUSB			56
+#define CLK_INFRA_DISP_PWM		57
+#define CLK_INFRA_CLDMA_B		58
+#define CLK_INFRA_AUDIO_26M_B		59
+#define CLK_INFRA_MODEM_TEMP_SHARE	60
+#define CLK_INFRA_SPI1			61
+#define CLK_INFRA_I2C4			62
+#define CLK_INFRA_SPI2			63
+#define CLK_INFRA_SPI3			64
+#define CLK_INFRA_UNIPRO_SYS		65
+#define CLK_INFRA_UNIPRO_TICK		66
+#define CLK_INFRA_UFS_MP_SAP_B		67
+#define CLK_INFRA_MD32_B		68
+#define CLK_INFRA_SSPM			69
+#define CLK_INFRA_UNIPRO_MBIST		70
+#define CLK_INFRA_SSPM_BUS_H		71
+#define CLK_INFRA_I2C5			72
+#define CLK_INFRA_I2C5_ARBITER		73
+#define CLK_INFRA_I2C5_IMM		74
+#define CLK_INFRA_I2C1_ARBITER		75
+#define CLK_INFRA_I2C1_IMM		76
+#define CLK_INFRA_I2C2_ARBITER		77
+#define CLK_INFRA_I2C2_IMM		78
+#define CLK_INFRA_SPI4			79
+#define CLK_INFRA_SPI5			80
+#define CLK_INFRA_CQ_DMA		81
+#define CLK_INFRA_UFS			82
+#define CLK_INFRA_AES_UFSFDE		83
+#define CLK_INFRA_UFS_TICK		84
+#define CLK_INFRA_SSUSB_XHCI		85
+#define CLK_INFRA_MSDC0_SELF		86
+#define CLK_INFRA_MSDC1_SELF		87
+#define CLK_INFRA_MSDC2_SELF		88
+#define CLK_INFRA_SSPM_26M_SELF		89
+#define CLK_INFRA_SSPM_32K_SELF		90
+#define CLK_INFRA_UFS_AXI		91
+#define CLK_INFRA_I2C6			92
+#define CLK_INFRA_AP_MSDC0		93
+#define CLK_INFRA_MD_MSDC0		94
+#define CLK_INFRA_CCIF5_AP		95
+#define CLK_INFRA_CCIF5_MD		96
+#define CLK_INFRA_PCIE_TOP_H_133M	97
+#define CLK_INFRA_FLASHIF_TOP_H_133M	98
+#define CLK_INFRA_PCIE_PERI_26M		99
+#define CLK_INFRA_CCIF2_AP		100
+#define CLK_INFRA_CCIF2_MD		101
+#define CLK_INFRA_CCIF3_AP		102
+#define CLK_INFRA_CCIF3_MD		103
+#define CLK_INFRA_SEJ_F13M		104
+#define CLK_INFRA_AES			105
+#define CLK_INFRA_I2C7			106
+#define CLK_INFRA_I2C8			107
+#define CLK_INFRA_FBIST2FPC		108
+#define CLK_INFRA_DEVICE_APC_SYNC	109
+#define CLK_INFRA_DPMAIF_MAIN		110
+#define CLK_INFRA_PCIE_TL_32K		111
+#define CLK_INFRA_CCIF4_AP		112
+#define CLK_INFRA_CCIF4_MD		113
+#define CLK_INFRA_SPI6			114
+#define CLK_INFRA_SPI7			115
+#define CLK_INFRA_133M			116
+#define CLK_INFRA_66M			117
+#define CLK_INFRA_66M_PERI_BUS		118
+#define CLK_INFRA_FREE_DCM_133M		119
+#define CLK_INFRA_FREE_DCM_66M		120
+#define CLK_INFRA_PERI_BUS_DCM_133M	121
+#define CLK_INFRA_PERI_BUS_DCM_66M	122
+#define CLK_INFRA_FLASHIF_PERI_26M	123
+#define CLK_INFRA_FLASHIF_SFLASH	124
+#define CLK_INFRA_AP_DMA		125
+#define CLK_INFRA_NR_CLK		126
+
+/* PERICFG */
+
+#define CLK_PERI_PERIAXI		0
+#define CLK_PERI_NR_CLK			1
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_MAINPLL		0
+#define CLK_APMIXED_UNIVPLL		1
+#define CLK_APMIXED_USBPLL		2
+#define CLK_APMIXED_MSDCPLL		3
+#define CLK_APMIXED_MMPLL		4
+#define CLK_APMIXED_ADSPPLL		5
+#define CLK_APMIXED_MFGPLL		6
+#define CLK_APMIXED_TVDPLL		7
+#define CLK_APMIXED_APLL1		8
+#define CLK_APMIXED_APLL2		9
+#define CLK_APMIXED_MIPID26M		10
+#define CLK_APMIXED_NR_CLK		11
+
+/* SCP_ADSP */
+
+#define CLK_SCP_ADSP_AUDIODSP		0
+#define CLK_SCP_ADSP_NR_CLK		1
+
+/* IMP_IIC_WRAP_C */
+
+#define CLK_IMP_IIC_WRAP_C_I2C10	0
+#define CLK_IMP_IIC_WRAP_C_I2C11	1
+#define CLK_IMP_IIC_WRAP_C_I2C12	2
+#define CLK_IMP_IIC_WRAP_C_I2C13	3
+#define CLK_IMP_IIC_WRAP_C_NR_CLK	4
+
+/* AUDSYS */
+
+#define CLK_AUD_AFE			0
+#define CLK_AUD_22M			1
+#define CLK_AUD_24M			2
+#define CLK_AUD_APLL2_TUNER		3
+#define CLK_AUD_APLL_TUNER		4
+#define CLK_AUD_TDM			5
+#define CLK_AUD_ADC			6
+#define CLK_AUD_DAC			7
+#define CLK_AUD_DAC_PREDIS		8
+#define CLK_AUD_TML			9
+#define CLK_AUD_NLE			10
+#define CLK_AUD_I2S1_B			11
+#define CLK_AUD_I2S2_B			12
+#define CLK_AUD_I2S3_B			13
+#define CLK_AUD_I2S4_B			14
+#define CLK_AUD_CONNSYS_I2S_ASRC	15
+#define CLK_AUD_GENERAL1_ASRC		16
+#define CLK_AUD_GENERAL2_ASRC		17
+#define CLK_AUD_DAC_HIRES		18
+#define CLK_AUD_ADC_HIRES		19
+#define CLK_AUD_ADC_HIRES_TML		20
+#define CLK_AUD_ADDA6_ADC		21
+#define CLK_AUD_ADDA6_ADC_HIRES		22
+#define CLK_AUD_3RD_DAC			23
+#define CLK_AUD_3RD_DAC_PREDIS		24
+#define CLK_AUD_3RD_DAC_TML		25
+#define CLK_AUD_3RD_DAC_HIRES		26
+#define CLK_AUD_I2S5_B			27
+#define CLK_AUD_I2S6_B			28
+#define CLK_AUD_I2S7_B			29
+#define CLK_AUD_I2S8_B			30
+#define CLK_AUD_I2S9_B			31
+#define CLK_AUD_NR_CLK			32
+
+/* IMP_IIC_WRAP_E */
+
+#define CLK_IMP_IIC_WRAP_E_I2C3		0
+#define CLK_IMP_IIC_WRAP_E_NR_CLK	1
+
+/* IMP_IIC_WRAP_S */
+
+#define CLK_IMP_IIC_WRAP_S_I2C7		0
+#define CLK_IMP_IIC_WRAP_S_I2C8		1
+#define CLK_IMP_IIC_WRAP_S_I2C9		2
+#define CLK_IMP_IIC_WRAP_S_NR_CLK	3
+
+/* IMP_IIC_WRAP_WS */
+
+#define CLK_IMP_IIC_WRAP_WS_I2C1	0
+#define CLK_IMP_IIC_WRAP_WS_I2C2	1
+#define CLK_IMP_IIC_WRAP_WS_I2C4	2
+#define CLK_IMP_IIC_WRAP_WS_NR_CLK	3
+
+/* IMP_IIC_WRAP_W */
+
+#define CLK_IMP_IIC_WRAP_W_I2C5		0
+#define CLK_IMP_IIC_WRAP_W_NR_CLK	1
+
+/* IMP_IIC_WRAP_N */
+
+#define CLK_IMP_IIC_WRAP_N_I2C0		0
+#define CLK_IMP_IIC_WRAP_N_I2C6		1
+#define CLK_IMP_IIC_WRAP_N_NR_CLK	2
+
+/* MSDC_TOP */
+
+#define CLK_MSDC_TOP_AES_0P		0
+#define CLK_MSDC_TOP_SRC_0P		1
+#define CLK_MSDC_TOP_SRC_1P		2
+#define CLK_MSDC_TOP_SRC_2P		3
+#define CLK_MSDC_TOP_P_MSDC0		4
+#define CLK_MSDC_TOP_P_MSDC1		5
+#define CLK_MSDC_TOP_P_MSDC2		6
+#define CLK_MSDC_TOP_P_CFG		7
+#define CLK_MSDC_TOP_AXI		8
+#define CLK_MSDC_TOP_H_MST_0P		9
+#define CLK_MSDC_TOP_H_MST_1P		10
+#define CLK_MSDC_TOP_H_MST_2P		11
+#define CLK_MSDC_TOP_MEM_OFF_DLY_26M	12
+#define CLK_MSDC_TOP_32K		13
+#define CLK_MSDC_TOP_AHB2AXI_BRG_AXI	14
+#define CLK_MSDC_TOP_NR_CLK		15
+
+/* MSDC */
+
+#define CLK_MSDC_AXI_WRAP		0
+#define CLK_MSDC_NR_CLK			1
+
+/* MFGCFG */
+
+#define CLK_MFG_BG3D			0
+#define CLK_MFG_NR_CLK			1
+
+/* MMSYS */
+
+#define CLK_MM_DISP_MUTEX0		0
+#define CLK_MM_DISP_CONFIG		1
+#define CLK_MM_DISP_OVL0		2
+#define CLK_MM_DISP_RDMA0		3
+#define CLK_MM_DISP_OVL0_2L		4
+#define CLK_MM_DISP_WDMA0		5
+#define CLK_MM_DISP_UFBC_WDMA0		6
+#define CLK_MM_DISP_RSZ0		7
+#define CLK_MM_DISP_AAL0		8
+#define CLK_MM_DISP_CCORR0		9
+#define CLK_MM_DISP_DITHER0		10
+#define CLK_MM_SMI_INFRA		11
+#define CLK_MM_DISP_GAMMA0		12
+#define CLK_MM_DISP_POSTMASK0		13
+#define CLK_MM_DISP_DSC_WRAP0		14
+#define CLK_MM_DSI0			15
+#define CLK_MM_DISP_COLOR0		16
+#define CLK_MM_SMI_COMMON		17
+#define CLK_MM_DISP_FAKE_ENG0		18
+#define CLK_MM_DISP_FAKE_ENG1		19
+#define CLK_MM_MDP_TDSHP4		20
+#define CLK_MM_MDP_RSZ4			21
+#define CLK_MM_MDP_AAL4			22
+#define CLK_MM_MDP_HDR4			23
+#define CLK_MM_MDP_RDMA4		24
+#define CLK_MM_MDP_COLOR4		25
+#define CLK_MM_DISP_Y2R0		26
+#define CLK_MM_SMI_GALS			27
+#define CLK_MM_DISP_OVL2_2L		28
+#define CLK_MM_DISP_RDMA4		29
+#define CLK_MM_DISP_DPI0		30
+#define CLK_MM_SMI_IOMMU		31
+#define CLK_MM_DSI_DSI0			32
+#define CLK_MM_DPI_DPI0			33
+#define CLK_MM_26MHZ			34
+#define CLK_MM_32KHZ			35
+#define CLK_MM_NR_CLK			36
+
+/* IMGSYS */
+
+#define CLK_IMG_LARB9			0
+#define CLK_IMG_LARB10			1
+#define CLK_IMG_DIP			2
+#define CLK_IMG_GALS			3
+#define CLK_IMG_NR_CLK			4
+
+/* IMGSYS2 */
+
+#define CLK_IMG2_LARB11			0
+#define CLK_IMG2_LARB12			1
+#define CLK_IMG2_MFB			2
+#define CLK_IMG2_WPE			3
+#define CLK_IMG2_MSS			4
+#define CLK_IMG2_GALS			5
+#define CLK_IMG2_NR_CLK			6
+
+/* VDECSYS_SOC */
+
+#define CLK_VDEC_SOC_LARB1		0
+#define CLK_VDEC_SOC_LAT		1
+#define CLK_VDEC_SOC_LAT_ACTIVE		2
+#define CLK_VDEC_SOC_VDEC		3
+#define CLK_VDEC_SOC_VDEC_ACTIVE	4
+#define CLK_VDEC_SOC_NR_CLK		5
+
+/* VDECSYS */
+
+#define CLK_VDEC_LARB1			0
+#define CLK_VDEC_LAT			1
+#define CLK_VDEC_LAT_ACTIVE		2
+#define CLK_VDEC_VDEC			3
+#define CLK_VDEC_ACTIVE			4
+#define CLK_VDEC_NR_CLK			5
+
+/* VENCSYS */
+
+#define CLK_VENC_SET0_LARB		0
+#define CLK_VENC_SET1_VENC		1
+#define CLK_VENC_SET2_JPGENC		2
+#define CLK_VENC_SET5_GALS		3
+#define CLK_VENC_NR_CLK			4
+
+/* CAMSYS */
+
+#define CLK_CAM_LARB13			0
+#define CLK_CAM_DFP_VAD			1
+#define CLK_CAM_LARB14			2
+#define CLK_CAM_CAM			3
+#define CLK_CAM_CAMTG			4
+#define CLK_CAM_SENINF			5
+#define CLK_CAM_CAMSV0			6
+#define CLK_CAM_CAMSV1			7
+#define CLK_CAM_CAMSV2			8
+#define CLK_CAM_CAMSV3			9
+#define CLK_CAM_CCU0			10
+#define CLK_CAM_CCU1			11
+#define CLK_CAM_MRAW0			12
+#define CLK_CAM_FAKE_ENG		13
+#define CLK_CAM_CCU_GALS		14
+#define CLK_CAM_CAM2MM_GALS		15
+#define CLK_CAM_NR_CLK			16
+
+/* CAMSYS_RAWA */
+
+#define CLK_CAM_RAWA_LARBX		0
+#define CLK_CAM_RAWA_CAM		1
+#define CLK_CAM_RAWA_CAMTG		2
+#define CLK_CAM_RAWA_NR_CLK		3
+
+/* CAMSYS_RAWB */
+
+#define CLK_CAM_RAWB_LARBX		0
+#define CLK_CAM_RAWB_CAM		1
+#define CLK_CAM_RAWB_CAMTG		2
+#define CLK_CAM_RAWB_NR_CLK		3
+
+/* CAMSYS_RAWC */
+
+#define CLK_CAM_RAWC_LARBX		0
+#define CLK_CAM_RAWC_CAM		1
+#define CLK_CAM_RAWC_CAMTG		2
+#define CLK_CAM_RAWC_NR_CLK		3
+
+/* IPESYS */
+
+#define CLK_IPE_LARB19			0
+#define CLK_IPE_LARB20			1
+#define CLK_IPE_SMI_SUBCOM		2
+#define CLK_IPE_FD			3
+#define CLK_IPE_FE			4
+#define CLK_IPE_RSC			5
+#define CLK_IPE_DPE			6
+#define CLK_IPE_GALS			7
+#define CLK_IPE_NR_CLK			8
+
+/* MDPSYS */
+
+#define CLK_MDP_RDMA0			0
+#define CLK_MDP_TDSHP0			1
+#define CLK_MDP_IMG_DL_ASYNC0		2
+#define CLK_MDP_IMG_DL_ASYNC1		3
+#define CLK_MDP_RDMA1			4
+#define CLK_MDP_TDSHP1			5
+#define CLK_MDP_SMI0			6
+#define CLK_MDP_APB_BUS			7
+#define CLK_MDP_WROT0			8
+#define CLK_MDP_RSZ0			9
+#define CLK_MDP_HDR0			10
+#define CLK_MDP_MUTEX0			11
+#define CLK_MDP_WROT1			12
+#define CLK_MDP_RSZ1			13
+#define CLK_MDP_HDR1			14
+#define CLK_MDP_FAKE_ENG0		15
+#define CLK_MDP_AAL0			16
+#define CLK_MDP_AAL1			17
+#define CLK_MDP_COLOR0			18
+#define CLK_MDP_COLOR1			19
+#define CLK_MDP_IMG_DL_RELAY0_ASYNC0	20
+#define CLK_MDP_IMG_DL_RELAY1_ASYNC1	21
+#define CLK_MDP_NR_CLK			22
+
+#endif /* _DT_BINDINGS_CLK_MT8192_H */
+
-- 
1.8.1.1.dirty

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v2 3/5] clk: mediatek: Fix asymmetrical PLL enable and disable control
  2020-07-29  8:44 [PATCH v2 0/5] Mediatek MT8192 clock support Weiyi Lu
  2020-07-29  8:44 ` [PATCH v2 1/5] dt-bindings: ARM: Mediatek: Document bindings for MT8192 Weiyi Lu
  2020-07-29  8:44 ` [PATCH v2 2/5] clk: mediatek: Add dt-bindings for MT8192 clocks Weiyi Lu
@ 2020-07-29  8:44 ` Weiyi Lu
  2020-07-29 10:51   ` Nicolas Boichat
  2020-07-29  8:44 ` [PATCH v2 4/5] clk: mediatek: Add configurable enable control to mtk_pll_data Weiyi Lu
       [not found] ` <1596012277-8448-6-git-send-email-weiyi.lu@mediatek.com>
  4 siblings, 1 reply; 17+ messages in thread
From: Weiyi Lu @ 2020-07-29  8:44 UTC (permalink / raw)
  To: Matthias Brugger, Rob Herring, Stephen Boyd, Nicolas Boichat
  Cc: James Liao, linux-arm-kernel, linux-kernel, linux-mediatek,
	linux-clk, srv_heupstream, Weiyi Lu, Wendell Lin

The en_mask actually is a combination of divider enable mask
and pll enable bit(bit0).
Before this patch, we enabled both divider mask and bit0 in prepare(),
but only cleared the bit0 in unprepare().
Now, setting the enable register(CON0) in 2 steps: first divider mask,
then bit0 during prepare(), vice versa.
Hence, en_mask will only be used as divider enable mask.
Meanwhile, all the SoC PLL data are updated.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
 drivers/clk/mediatek/clk-mt2701.c | 26 ++++++++++++------------
 drivers/clk/mediatek/clk-mt2712.c | 30 ++++++++++++++--------------
 drivers/clk/mediatek/clk-mt6765.c | 20 +++++++++----------
 drivers/clk/mediatek/clk-mt6779.c | 24 +++++++++++-----------
 drivers/clk/mediatek/clk-mt6797.c | 20 +++++++++----------
 drivers/clk/mediatek/clk-mt7622.c | 18 ++++++++---------
 drivers/clk/mediatek/clk-mt7629.c | 12 +++++------
 drivers/clk/mediatek/clk-mt8173.c | 42 ++++++++++++++++++++++++++-------------
 drivers/clk/mediatek/clk-mt8183.c | 22 ++++++++++----------
 drivers/clk/mediatek/clk-pll.c    | 10 ++++++++--
 10 files changed, 122 insertions(+), 102 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 695be0f..10d0b92 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -934,31 +934,31 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 	}
 
 static const struct mtk_pll_data apmixed_plls[] = {
-	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000001,
+	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000000,
 			PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0),
-	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000001,
+	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000000,
 		  HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),
-	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000001,
+	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000000,
 		  HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0,
+	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000000, 0,
 				21, 0x230, 4, 0x0, 0x234, 0),
-	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
+	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000000, 0,
 				21, 0x240, 4, 0x0, 0x244, 0),
-	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
+	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000000, 0,
 				21, 0x250, 4, 0x0, 0x254, 0),
-	PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
+	PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000000, 0,
 				31, 0x270, 4, 0x0, 0x274, 0),
-	PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
+	PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000000, 0,
 				31, 0x280, 4, 0x0, 0x284, 0),
-	PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
+	PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000000, 0,
 				31, 0x290, 4, 0x0, 0x294, 0),
-	PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
+	PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000000, 0,
 				31, 0x2a0, 4, 0x0, 0x2a4, 0),
-	PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0,
+	PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000000, 0,
 				31, 0x2b0, 4, 0x0, 0x2b4, 0),
-	PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0,
+	PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000000, 0,
 				31, 0x2c0, 4, 0x0, 0x2c4, 0),
-	PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0,
+	PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000000, 0,
 				21, 0x2d0, 4, 0x0, 0x2d4, 0),
 };
 
diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
index a3bd9a1..fd81162 100644
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -1222,38 +1222,38 @@
 };
 
 static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000101,
+	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100,
 		HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
-	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000101,
+	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100,
 		HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
-	PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000101,
+	PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100,
 		0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
-	PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000101,
+	PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100,
 		0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
-	PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000101,
+	PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100,
 		0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
-	PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000101,
+	PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100,
 		0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
-	PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000101,
+	PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100,
 		0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
-	PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000101,
+	PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100,
 		0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
-	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000101,
+	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100,
 		0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
-	PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000101,
+	PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100,
 		0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
-	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000101,
+	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100,
 		0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
-	PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000101,
+	PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100,
 		0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0,
 		mmpll_div_table),
-	PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000101,
+	PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000100,
 		HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0,
 		armca35pll_div_table),
-	PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000101,
+	PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000100,
 		0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0,
 		armca72pll_div_table),
-	PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000101,
+	PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000100,
 		0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
 };
 
diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-mt6765.c
index db8db1b..097bbc4 100644
--- a/drivers/clk/mediatek/clk-mt6765.c
+++ b/drivers/clk/mediatek/clk-mt6765.c
@@ -747,26 +747,26 @@
 			_pcw_reg, _pcw_shift, NULL)	\
 
 static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, BIT(0),
+	PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, 0,
 	    PLL_AO, 22, 8, 0x0220, 24, 0, 0, 0, 0x0220, 0),
-	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, BIT(0),
+	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, 0,
 	    PLL_AO, 22, 8, 0x0210, 24, 0, 0, 0, 0x0210, 0),
-	PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, BIT(0),
+	PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, 0,
 	    PLL_AO, 22, 8, 0x0230, 24, 0, 0, 0, 0x0230, 0),
-	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, BIT(0),
+	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, 0,
 	    (HAVE_RST_BAR | PLL_AO), 22, 8, 0x0240, 24, 0, 0, 0, 0x0240,
 	    0),
-	PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, BIT(0),
+	PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, 0,
 	    0, 22, 8, 0x0250, 24, 0, 0, 0, 0x0250, 0),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, BIT(0),
+	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, 0,
 	    0, 22, 8, 0x0260, 24, 0, 0, 0, 0x0260, 0),
-	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, BIT(0),
+	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, 0,
 	    HAVE_RST_BAR, 22, 8, 0x0270, 24, 0, 0, 0, 0x0270, 0),
-	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, BIT(0),
+	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, 0,
 	    0, 22, 8, 0x0280, 24, 0, 0, 0, 0x0280, 0),
-	PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, BIT(0),
+	PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, 0,
 	    0, 32, 8, 0x0290, 24, 0x0040, 0x000C, 0, 0x0294, 0),
-	PLL(CLK_APMIXED_MPLL, "mpll", 0x02A0, 0x02AC, BIT(0),
+	PLL(CLK_APMIXED_MPLL, "mpll", 0x02A0, 0x02AC, 0,
 	    PLL_AO, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0),
 };
 
diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
index 9766ccc..d8444ed 100644
--- a/drivers/clk/mediatek/clk-mt6779.c
+++ b/drivers/clk/mediatek/clk-mt6779.c
@@ -1178,33 +1178,33 @@
 			_pcw_chg_reg, NULL)
 
 static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, BIT(0),
+	PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,
 	    PLL_AO, 0, 22, 8, 0x0204, 24, 0, 0, 0, 0x0204, 0, 0),
-	PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, BIT(0),
+	PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, 0,
 	    PLL_AO, 0, 22, 8, 0x0214, 24, 0, 0, 0, 0x0214, 0, 0),
-	PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, BIT(0),
+	PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, 0,
 	    PLL_AO, 0, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0, 0),
-	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, BIT(0),
+	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0,
 	    (HAVE_RST_BAR), BIT(24), 22, 8, 0x0234, 24, 0, 0, 0,
 	    0x0234, 0, 0),
-	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, BIT(0),
+	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, 0,
 	    (HAVE_RST_BAR), BIT(24), 22, 8, 0x0244, 24,
 	    0, 0, 0, 0x0244, 0, 0),
-	PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, BIT(0),
+	PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, 0,
 	    0, 0, 22, 8, 0x0254, 24, 0, 0, 0, 0x0254, 0, 0),
-	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, BIT(0),
+	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, 0,
 	    0, 0, 22, 8, 0x0264, 24, 0, 0, 0, 0x0264, 0, 0),
-	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, BIT(0),
+	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0,
 	    0, 0, 22, 8, 0x0274, 24, 0, 0, 0, 0x0274, 0, 0),
-	PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, BIT(0),
+	PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, 0,
 	    (HAVE_RST_BAR), BIT(23), 22, 8, 0x02b4, 24,
 	    0, 0, 0, 0x02b4, 0, 0),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, BIT(0),
+	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, 0,
 	    (HAVE_RST_BAR), BIT(23), 22, 8, 0x0284, 24,
 	    0, 0, 0, 0x0284, 0, 0),
-	PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, BIT(0),
+	PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, 0,
 	    0, 0, 32, 8, 0x02C0, 1, 0, 0x14, 0, 0x02C4, 0, 0x2C0),
-	PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, BIT(0),
+	PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, 0,
 	    0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4),
 };
 
diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c
index f35389a..4395423 100644
--- a/drivers/clk/mediatek/clk-mt6797.c
+++ b/drivers/clk/mediatek/clk-mt6797.c
@@ -638,25 +638,25 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 			NULL)
 
 static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000101, PLL_AO,
+	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000100, PLL_AO,
 	    21, 0x220, 4, 0x0, 0x224, 0),
-	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000011, 0, 7,
+	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000010, 0, 7,
 	    0x230, 4, 0x0, 0x234, 14),
-	PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000101, 0, 21,
+	PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000100, 0, 21,
 	    0x244, 24, 0x0, 0x244, 0),
-	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000121, 0, 21,
+	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000120, 0, 21,
 	    0x250, 4, 0x0, 0x254, 0),
-	PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000121, 0, 21,
+	PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000120, 0, 21,
 	    0x260, 4, 0x0, 0x264, 0),
-	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000121, 0, 21,
+	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000120, 0, 21,
 	    0x270, 4, 0x0, 0x274, 0),
-	PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000121, 0, 21,
+	PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000120, 0, 21,
 	    0x290, 4, 0x0, 0x294, 0),
-	PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000121, 0, 21,
+	PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000120, 0, 21,
 	    0x2E4, 4, 0x0, 0x2E8, 0),
-	PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000131, 0, 31,
+	PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000130, 0, 31,
 	    0x2A0, 4, 0x2A8, 0x2A4, 0),
-	PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000131, 0, 31,
+	PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000130, 0, 31,
 	    0x2B4, 4, 0x2BC, 0x2B8, 0),
 };
 
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index ef5947e1..3ac222c 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -328,23 +328,23 @@
 };
 
 static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
+	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000000,
 	    PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
-	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
+	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000000,
 	    HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
-	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
+	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000000,
 	    HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
-	PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
+	PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000000,
 	    0, 21, 0x0300, 1, 0, 0x0304, 0),
-	PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
+	PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000000,
 	    0, 21, 0x0314, 1, 0, 0x0318, 0),
-	PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001,
+	PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000000,
 	    0, 31, 0x0324, 1, 0, 0x0328, 0),
-	PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001,
+	PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000000,
 	    0, 31, 0x0334, 1, 0, 0x0338, 0),
-	PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001,
+	PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000000,
 	    0, 21, 0x0344, 1, 0, 0x0348, 0),
-	PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
+	PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000000,
 	    0, 21, 0x0358, 1, 0, 0x035C, 0),
 };
 
diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index b73bdf1..2d434a9 100644
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -335,17 +335,17 @@
 };
 
 static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
+	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000000,
 	    0, 21, 0x0204, 24, 0, 0x0204, 0),
-	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
+	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000000,
 	    HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
-	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
+	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000000,
 	    HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
-	PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
+	PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000000,
 	    0, 21, 0x0300, 1, 0, 0x0304, 0),
-	PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
+	PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000000,
 	    0, 21, 0x0314, 1, 0, 0x0318, 0),
-	PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
+	PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000000,
 	    0, 21, 0x0358, 1, 0, 0x035C, 0),
 };
 
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 8f898ac..92d8bdd 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -972,20 +972,34 @@ struct mtk_clk_usb {
 };
 
 static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
-	PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000001, 0, 21, 0x214, 24, 0x0, 0x214, 0),
-	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
-	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000001, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
-	PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table),
-	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000001, 0, 21, 0x250, 4, 0x0, 0x254, 0),
-	PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000001, 0, 21, 0x260, 4, 0x0, 0x264, 0),
-	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000001, 0, 21, 0x270, 4, 0x0, 0x274, 0),
-	PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x00000001, 0, 21, 0x280, 4, 0x0, 0x284, 0),
-	PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0x00000001, 0, 21, 0x290, 4, 0x0, 0x294, 0),
-	PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0x00000001, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
-	PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0x00000001, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
-	PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0x00000001, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
-	PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0x00000001, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
+	PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000000,
+		0, 21, 0x204, 24, 0x0, 0x204, 0),
+	PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000000,
+		0, 21, 0x214, 24, 0x0, 0x214, 0),
+	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100,
+		HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
+	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000,
+		HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
+	PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000000,
+		0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table),
+	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000000,
+		0, 21, 0x250, 4, 0x0, 0x254, 0),
+	PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000000,
+		0, 21, 0x260, 4, 0x0, 0x264, 0),
+	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000000,
+		0, 21, 0x270, 4, 0x0, 0x274, 0),
+	PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x00000000,
+		0, 21, 0x280, 4, 0x0, 0x284, 0),
+	PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0x00000000,
+		0, 21, 0x290, 4, 0x0, 0x294, 0),
+	PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0x00000000,
+		0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
+	PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0x00000000,
+		0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
+	PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0x00000000,
+		0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
+	PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0x00000000,
+		0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
 };
 
 static void __init mtk_apmixedsys_init(struct device_node *node)
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 5046852..e1b0a13 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -1121,34 +1121,34 @@
 };
 
 static const struct mtk_pll_data plls[] = {
-	PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0x00000001,
+	PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0x00000000,
 		HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0,
 		0x0204, 0, 0, armpll_div_table),
-	PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0x00000001,
+	PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0x00000000,
 		HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0,
 		0x0214, 0, 0, armpll_div_table),
-	PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0x00000001,
+	PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0x00000000,
 		HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0,
 		0x0294, 0, 0),
-	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0x00000001,
+	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0x00000000,
 		HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0,
 		0x0224, 0, 0),
-	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0x00000001,
+	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0x00000000,
 		HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0,
 		0x0234, 0, 0),
-	PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000001,
+	PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000000,
 		0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0,
 		mfgpll_div_table),
-	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000001,
+	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000000,
 		0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0),
-	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0x00000001,
+	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0x00000000,
 		0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0x00000001,
+	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0x00000000,
 		HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0,
 		0x0274, 0, 0),
-	PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000001,
+	PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000000,
 		0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0),
-	PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0x00000001,
+	PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0x00000000,
 		0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
 };
 
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index f440f2cd..3c79e1a 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -247,8 +247,10 @@ static int mtk_pll_prepare(struct clk_hw *hw)
 	writel(r, pll->pwr_addr);
 	udelay(1);
 
-	r = readl(pll->base_addr + REG_CON0);
-	r |= pll->data->en_mask;
+	r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN;
+	writel(r, pll->base_addr + REG_CON0);
+
+	r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
 	writel(r, pll->base_addr + REG_CON0);
 
 	__mtk_pll_tuner_enable(pll);
@@ -278,6 +280,10 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
 	__mtk_pll_tuner_disable(pll);
 
 	r = readl(pll->base_addr + REG_CON0);
+	r &= ~pll->data->en_mask;
+	writel(r, pll->base_addr + REG_CON0);
+
+	r = readl(pll->base_addr + REG_CON0);
 	r &= ~CON0_BASE_EN;
 	writel(r, pll->base_addr + REG_CON0);
 
-- 
1.8.1.1.dirty

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v2 4/5] clk: mediatek: Add configurable enable control to mtk_pll_data
  2020-07-29  8:44 [PATCH v2 0/5] Mediatek MT8192 clock support Weiyi Lu
                   ` (2 preceding siblings ...)
  2020-07-29  8:44 ` [PATCH v2 3/5] clk: mediatek: Fix asymmetrical PLL enable and disable control Weiyi Lu
@ 2020-07-29  8:44 ` Weiyi Lu
  2020-07-29 10:58   ` Nicolas Boichat
       [not found] ` <1596012277-8448-6-git-send-email-weiyi.lu@mediatek.com>
  4 siblings, 1 reply; 17+ messages in thread
From: Weiyi Lu @ 2020-07-29  8:44 UTC (permalink / raw)
  To: Matthias Brugger, Rob Herring, Stephen Boyd, Nicolas Boichat
  Cc: James Liao, linux-arm-kernel, linux-kernel, linux-mediatek,
	linux-clk, srv_heupstream, Weiyi Lu, Wendell Lin

In all MediaTek PLL design, bit0 of CON0 register is always
the enable bit.
However, there's a special case of usbpll on MT8192.
The enable bit of usbpll is moved to bit2 of other register.
Add configurable en_reg and pll_en_bit for enable control or
default 0 where pll data are static variables.
Hence, CON0_BASE_EN could also be removed.
And there might have another special case on other chips,
the enable bit is still on CON0 register but not at bit0.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
 drivers/clk/mediatek/clk-mtk.h |  2 ++
 drivers/clk/mediatek/clk-pll.c | 18 +++++++++++-------
 2 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index c3d6756..810eb97 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -233,6 +233,8 @@ struct mtk_pll_data {
 	uint32_t pcw_chg_reg;
 	const struct mtk_pll_div_table *div_table;
 	const char *parent_name;
+	uint32_t en_reg;
+	uint8_t pll_en_bit;
 };
 
 void mtk_clk_register_plls(struct device_node *node,
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 3c79e1a..1434e99 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -16,7 +16,6 @@
 #define REG_CON0		0
 #define REG_CON1		4
 
-#define CON0_BASE_EN		BIT(0)
 #define CON0_PWR_ON		BIT(0)
 #define CON0_ISO_EN		BIT(1)
 #define PCW_CHG_MASK		BIT(31)
@@ -44,6 +43,7 @@ struct mtk_clk_pll {
 	void __iomem	*tuner_en_addr;
 	void __iomem	*pcw_addr;
 	void __iomem	*pcw_chg_addr;
+	void __iomem	*en_addr;
 	const struct mtk_pll_data *data;
 };
 
@@ -56,7 +56,7 @@ static int mtk_pll_is_prepared(struct clk_hw *hw)
 {
 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
 
-	return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
+	return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
 }
 
 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
@@ -247,8 +247,8 @@ static int mtk_pll_prepare(struct clk_hw *hw)
 	writel(r, pll->pwr_addr);
 	udelay(1);
 
-	r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN;
-	writel(r, pll->base_addr + REG_CON0);
+	r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);
+	writel(r, pll->en_addr);
 
 	r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
 	writel(r, pll->base_addr + REG_CON0);
@@ -283,9 +283,9 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
 	r &= ~pll->data->en_mask;
 	writel(r, pll->base_addr + REG_CON0);
 
-	r = readl(pll->base_addr + REG_CON0);
-	r &= ~CON0_BASE_EN;
-	writel(r, pll->base_addr + REG_CON0);
+	r = readl(pll->en_addr);
+	r &= ~BIT(pll->data->pll_en_bit);
+	writel(r, pll->en_addr);
 
 	r = readl(pll->pwr_addr) | CON0_ISO_EN;
 	writel(r, pll->pwr_addr);
@@ -327,6 +327,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
 		pll->tuner_addr = base + data->tuner_reg;
 	if (data->tuner_en_reg)
 		pll->tuner_en_addr = base + data->tuner_en_reg;
+	if (data->en_reg)
+		pll->en_addr = base + data->en_reg;
+	else
+		pll->en_addr = pll->base_addr + REG_CON0;
 	pll->hw.init = &init;
 	pll->data = data;
 
-- 
1.8.1.1.dirty

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v2 5/5] clk: mediatek: Add MT8192 clock support
       [not found] ` <1596012277-8448-6-git-send-email-weiyi.lu@mediatek.com>
@ 2020-07-29  9:32   ` Enric Balletbo Serra
  2020-08-11  7:03     ` Weiyi Lu
  0 siblings, 1 reply; 17+ messages in thread
From: Enric Balletbo Serra @ 2020-07-29  9:32 UTC (permalink / raw)
  To: Weiyi Lu
  Cc: Matthias Brugger, Rob Herring, Stephen Boyd, Nicolas Boichat,
	James Liao, Linux ARM, linux-kernel,
	moderated list:ARM/Mediatek SoC support, linux-clk,
	srv_heupstream, Wendell Lin

Hi Weiyi,

Thank you for your patch. Some few comment below, I'll focus on
clk-mt8192-mm file, but I think can apply to other files too.

[snip]

> diff --git a/drivers/clk/mediatek/clk-mt8192-mm.c b/drivers/clk/mediatek/clk-mt8192-mm.c
> new file mode 100644
> index 0000000..02eef24
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8192-mm.c
> @@ -0,0 +1,108 @@
> +// SPDX-License-Identifier: GPL-2.0

nit: Although is a valid license identifier for the kernel would be
better to use the non-deprecated form by SPDX, GPL-2.0-only

> +//
> +// Copyright (c) 2020 MediaTek Inc.
> +// Author: Weiyi Lu <weiyi.lu@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8192-clk.h>
> +
> +static const struct mtk_gate_regs mm0_cg_regs = {
> +       .set_ofs = 0x104,
> +       .clr_ofs = 0x108,
> +       .sta_ofs = 0x100,
> +};
> +
> +static const struct mtk_gate_regs mm1_cg_regs = {
> +       .set_ofs = 0x114,
> +       .clr_ofs = 0x118,
> +       .sta_ofs = 0x110,
> +};
> +
> +static const struct mtk_gate_regs mm2_cg_regs = {
> +       .set_ofs = 0x1a4,
> +       .clr_ofs = 0x1a8,
> +       .sta_ofs = 0x1a0,
> +};
> +
> +#define GATE_MM0(_id, _name, _parent, _shift)                  \
> +       GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift,     \
> +               &mtk_clk_gate_ops_setclr)

nit: You can take advantage of the new line length limit, which is now
100 characters.

> +
> +#define GATE_MM1(_id, _name, _parent, _shift)                  \
> +       GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift,     \
> +               &mtk_clk_gate_ops_setclr)
> +

ditto

> +#define GATE_MM2(_id, _name, _parent, _shift)                  \
> +       GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift,     \
> +               &mtk_clk_gate_ops_setclr)
> +

ditto

> +static const struct mtk_gate mm_clks[] = {
> +       /* MM0 */
> +       GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "disp_sel", 0),
> +       GATE_MM0(CLK_MM_DISP_CONFIG, "mm_disp_config", "disp_sel", 1),
> +       GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "disp_sel", 2),
> +       GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "disp_sel", 3),
> +       GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "disp_sel", 4),
> +       GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp_sel", 5),
> +       GATE_MM0(CLK_MM_DISP_UFBC_WDMA0, "mm_disp_ufbc_wdma0", "disp_sel", 6),
> +       GATE_MM0(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "disp_sel", 7),
> +       GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "disp_sel", 8),
> +       GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "disp_sel", 9),
> +       GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "disp_sel", 10),
> +       GATE_MM0(CLK_MM_SMI_INFRA, "mm_smi_infra", "disp_sel", 11),
> +       GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "disp_sel", 12),
> +       GATE_MM0(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "disp_sel", 13),
> +       GATE_MM0(CLK_MM_DISP_DSC_WRAP0, "mm_disp_dsc_wrap0", "disp_sel", 14),
> +       GATE_MM0(CLK_MM_DSI0, "mm_dsi0", "disp_sel", 15),
> +       GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "disp_sel", 16),
> +       GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "disp_sel", 17),
> +       GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "disp_sel", 18),
> +       GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1", "disp_sel", 19),
> +       GATE_MM0(CLK_MM_MDP_TDSHP4, "mm_mdp_tdshp4", "disp_sel", 20),
> +       GATE_MM0(CLK_MM_MDP_RSZ4, "mm_mdp_rsz4", "disp_sel", 21),
> +       GATE_MM0(CLK_MM_MDP_AAL4, "mm_mdp_aal4", "disp_sel", 22),
> +       GATE_MM0(CLK_MM_MDP_HDR4, "mm_mdp_hdr4", "disp_sel", 23),
> +       GATE_MM0(CLK_MM_MDP_RDMA4, "mm_mdp_rdma4", "disp_sel", 24),
> +       GATE_MM0(CLK_MM_MDP_COLOR4, "mm_mdp_color4", "disp_sel", 25),
> +       GATE_MM0(CLK_MM_DISP_Y2R0, "mm_disp_y2r0", "disp_sel", 26),
> +       GATE_MM0(CLK_MM_SMI_GALS, "mm_smi_gals", "disp_sel", 27),
> +       GATE_MM0(CLK_MM_DISP_OVL2_2L, "mm_disp_ovl2_2l", "disp_sel", 28),
> +       GATE_MM0(CLK_MM_DISP_RDMA4, "mm_disp_rdma4", "disp_sel", 29),
> +       GATE_MM0(CLK_MM_DISP_DPI0, "mm_disp_dpi0", "disp_sel", 30),
> +       /* MM1 */
> +       GATE_MM1(CLK_MM_SMI_IOMMU, "mm_smi_iommu", "disp_sel", 0),
> +       /* MM2 */
> +       GATE_MM2(CLK_MM_DSI_DSI0, "mm_dsi_dsi0", "disp_sel", 0),
> +       GATE_MM2(CLK_MM_DPI_DPI0, "mm_dpi_dpi0", "dpi_sel", 8),
> +       GATE_MM2(CLK_MM_26MHZ, "mm_26mhz", "clk26m", 24),
> +       GATE_MM2(CLK_MM_32KHZ, "mm_32khz", "clk32k", 25),
> +};
> +
> +static int clk_mt8192_mm_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct device_node *node = dev->parent->of_node;
> +       struct clk_onecell_data *clk_data;
> +
> +       clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);

mtk_alloc_clk_data can return NULL

           if (!clk_data)
              return -ENOMEM;

> +
> +       mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
> +                       clk_data);
> +

The above function can fail, better check for error

         if (ret)
             return ret;

> +       return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> +

No need for double line spacing.

> +static struct platform_driver clk_mt8192_mm_drv = {
> +       .probe = clk_mt8192_mm_probe,
> +       .driver = {
> +               .name = "clk-mt8192-mm",
> +       },
> +};
> +
> +builtin_platform_driver(clk_mt8192_mm_drv);

[snip]

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v2 1/5] dt-bindings: ARM: Mediatek: Document bindings for MT8192
  2020-07-29  8:44 ` [PATCH v2 1/5] dt-bindings: ARM: Mediatek: Document bindings for MT8192 Weiyi Lu
@ 2020-07-29  9:53   ` Enric Balletbo Serra
  2020-08-11  7:01     ` Weiyi Lu
  0 siblings, 1 reply; 17+ messages in thread
From: Enric Balletbo Serra @ 2020-07-29  9:53 UTC (permalink / raw)
  To: Weiyi Lu
  Cc: Matthias Brugger, Rob Herring, Stephen Boyd, Nicolas Boichat,
	James Liao, Linux ARM, linux-kernel,
	moderated list:ARM/Mediatek SoC support, linux-clk,
	srv_heupstream, Wendell Lin

Hi Weiyu,

Thanks for the patch, some comments below. I am not sure what
maintainers think but your patches, in general, are really big and I'm
wondering if wouldn't be better split by functionalities. Will make
your series much longer but easy to review in my opinion. Anyway, I'm
going to comment a few files but the comments can be applied to other
files.

Missatge de Weiyi Lu <weiyi.lu@mediatek.com> del dia dc., 29 de jul.
2020 a les 10:46:
>
> This patch adds the binding documentation for apmixedsys, audsys,
> camsys-raw, camsys, imgsys, imp_iic_wrap, infracfg, ipesys, mdpsys,
> mfgcfg, mmsys, msdc, pericfg, scp-adsp, topckgen, vdecsys-soc,
> vdecsys and vencsys for Mediatek MT8192.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
>  .../bindings/arm/mediatek/mediatek,apmixedsys.txt  |  1 +
>  .../bindings/arm/mediatek/mediatek,audsys.txt      |  1 +
>  .../bindings/arm/mediatek/mediatek,camsys-raw.yaml | 40 ++++++++++++++++++++
>  .../bindings/arm/mediatek/mediatek,camsys.txt      |  1 +
>  .../bindings/arm/mediatek/mediatek,imgsys.txt      |  2 +
>  .../arm/mediatek/mediatek,imp_iic_wrap.yaml        | 43 ++++++++++++++++++++++
>  .../bindings/arm/mediatek/mediatek,infracfg.txt    |  1 +
>  .../bindings/arm/mediatek/mediatek,ipesys.txt      |  1 +
>  .../bindings/arm/mediatek/mediatek,mdpsys.yaml     | 38 +++++++++++++++++++
>  .../bindings/arm/mediatek/mediatek,mfgcfg.txt      |  1 +
>  .../bindings/arm/mediatek/mediatek,mmsys.txt       |  1 +
>  .../bindings/arm/mediatek/mediatek,msdc.yaml       | 39 ++++++++++++++++++++
>  .../bindings/arm/mediatek/mediatek,pericfg.yaml    |  1 +
>  .../bindings/arm/mediatek/mediatek,scp-adsp.yaml   | 38 +++++++++++++++++++
>  .../bindings/arm/mediatek/mediatek,topckgen.txt    |  1 +
>  .../arm/mediatek/mediatek,vdecsys-soc.yaml         | 38 +++++++++++++++++++
>  .../bindings/arm/mediatek/mediatek,vdecsys.txt     |  1 +
>  .../bindings/arm/mediatek/mediatek,vencsys.txt     |  1 +
>  18 files changed, 249 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml
>  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,imp_iic_wrap.yaml
>  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdpsys.yaml
>  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml
>  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,scp-adsp.yaml
>  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
> index bd7a0fa..6942ad4 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
> @@ -17,6 +17,7 @@ Required Properties:
>         - "mediatek,mt8135-apmixedsys"
>         - "mediatek,mt8173-apmixedsys"
>         - "mediatek,mt8183-apmixedsys", "syscon"
> +       - "mediatek,mt8192-apmixedsys", "syscon"
>         - "mediatek,mt8516-apmixedsys"
>  - #clock-cells: Must be 1
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
> index 38309db..fdcb267 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
> @@ -12,6 +12,7 @@ Required Properties:
>         - "mediatek,mt7622-audsys", "syscon"
>         - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
>         - "mediatek,mt8183-audiosys", "syscon"
> +       - "mediatek,mt8192-audsys", "syscon"
>         - "mediatek,mt8516-audsys", "syscon"
>  - #clock-cells: Must be 1
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml
> new file mode 100644
> index 0000000..db6f425
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml
> @@ -0,0 +1,40 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,camsys-raw.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek CAMSYS RAW Controller
> +
> +maintainers:
> +  - Weiyi Lu <weiyi.lu@mediatek.com>
> +
> +description:
> +  The Mediatek camsys raw controller provides various clocks to the system.
> +

It only provides clocks or also provides configuration registers
non-clock related?

> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - mediatek,mt8192-camsys_rawa
> +          - mediatek,mt8192-camsys_rawb
> +          - mediatek,mt8192-camsys_rawc
> +      - const: syscon
> +
> +  reg:
> +    maxItems: 1
> +
> +  '#clock-cells':
> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +
> +examples:
> +  - |
> +    camsys_rawa: camsys_rawa@1a04f000 {

I think that this should be  "syscon@1a04f000", since node names are
supposed to match the class of the device instead of the name of the
device.

Just because I am curious, can you show me an example of
"mediatek,mt8192-camsys_rawb" or "mediatek,mt8192-camsys_rawc"? It's a
different address space?

> +        compatible = "mediatek,mt8192-camsys_rawa", "syscon";
> +        reg = <0 0x1a04f000 0 0x1000>;
> +        #clock-cells = <1>;
> +    };

[snip]

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v2 3/5] clk: mediatek: Fix asymmetrical PLL enable and disable control
  2020-07-29  8:44 ` [PATCH v2 3/5] clk: mediatek: Fix asymmetrical PLL enable and disable control Weiyi Lu
@ 2020-07-29 10:51   ` Nicolas Boichat
  2020-07-29 11:02     ` Nicolas Boichat
  2020-08-11  6:50     ` Weiyi Lu
  0 siblings, 2 replies; 17+ messages in thread
From: Nicolas Boichat @ 2020-07-29 10:51 UTC (permalink / raw)
  To: Weiyi Lu
  Cc: Matthias Brugger, Rob Herring, Stephen Boyd, James Liao,
	linux-arm Mailing List, lkml,
	moderated list:ARM/Mediatek SoC support, linux-clk,
	srv_heupstream, Wendell Lin

On Wed, Jul 29, 2020 at 4:44 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
>
> The en_mask actually is a combination of divider enable mask
> and pll enable bit(bit0).
> Before this patch, we enabled both divider mask and bit0 in prepare(),
> but only cleared the bit0 in unprepare().
> Now, setting the enable register(CON0) in 2 steps: first divider mask,
> then bit0 during prepare(), vice versa.
> Hence, en_mask will only be used as divider enable mask.
> Meanwhile, all the SoC PLL data are updated.

I like this a lot better, most changes look fine, just a few nits.

>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
>  drivers/clk/mediatek/clk-mt2701.c | 26 ++++++++++++------------
>  drivers/clk/mediatek/clk-mt2712.c | 30 ++++++++++++++--------------
>  drivers/clk/mediatek/clk-mt6765.c | 20 +++++++++----------
>  drivers/clk/mediatek/clk-mt6779.c | 24 +++++++++++-----------
>  drivers/clk/mediatek/clk-mt6797.c | 20 +++++++++----------
>  drivers/clk/mediatek/clk-mt7622.c | 18 ++++++++---------
>  drivers/clk/mediatek/clk-mt7629.c | 12 +++++------
>  drivers/clk/mediatek/clk-mt8173.c | 42 ++++++++++++++++++++++++++-------------
>  drivers/clk/mediatek/clk-mt8183.c | 22 ++++++++++----------
>  drivers/clk/mediatek/clk-pll.c    | 10 ++++++++--
>  10 files changed, 122 insertions(+), 102 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
> index 695be0f..10d0b92 100644
> --- a/drivers/clk/mediatek/clk-mt2701.c
> +++ b/drivers/clk/mediatek/clk-mt2701.c
> @@ -934,31 +934,31 @@ static int mtk_pericfg_init(struct platform_device *pdev)
>         }
>
>  static const struct mtk_pll_data apmixed_plls[] = {
> -       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000001,
> +       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000000,
>                         PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0),
> -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000001,
> +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000000,
>                   HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),
> -       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000001,
> +       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000000,
>                   HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),
> -       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0,
> +       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000000, 0,
>                                 21, 0x230, 4, 0x0, 0x234, 0),
> -       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
> +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000000, 0,
>                                 21, 0x240, 4, 0x0, 0x244, 0),
> -       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
> +       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000000, 0,
>                                 21, 0x250, 4, 0x0, 0x254, 0),
> -       PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
> +       PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000000, 0,
>                                 31, 0x270, 4, 0x0, 0x274, 0),
> -       PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
> +       PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000000, 0,
>                                 31, 0x280, 4, 0x0, 0x284, 0),
> -       PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
> +       PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000000, 0,
>                                 31, 0x290, 4, 0x0, 0x294, 0),
> -       PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
> +       PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000000, 0,
>                                 31, 0x2a0, 4, 0x0, 0x2a4, 0),
> -       PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0,
> +       PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000000, 0,
>                                 31, 0x2b0, 4, 0x0, 0x2b4, 0),
> -       PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0,
> +       PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000000, 0,
>                                 31, 0x2c0, 4, 0x0, 0x2c4, 0),
> -       PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0,
> +       PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000000, 0,
>                                 21, 0x2d0, 4, 0x0, 0x2d4, 0),
>  };
>
> diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
> index a3bd9a1..fd81162 100644
> --- a/drivers/clk/mediatek/clk-mt2712.c
> +++ b/drivers/clk/mediatek/clk-mt2712.c
> @@ -1222,38 +1222,38 @@
>  };
>
>  static const struct mtk_pll_data plls[] = {
> -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000101,
> +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100,
>                 HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
> -       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000101,
> +       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100,
>                 HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
> -       PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000101,
> +       PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100,
>                 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
> -       PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000101,
> +       PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100,
>                 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
> -       PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000101,
> +       PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100,
>                 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
> -       PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000101,
> +       PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100,
>                 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
> -       PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000101,
> +       PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100,
>                 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
> -       PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000101,
> +       PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100,
>                 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
> -       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000101,
> +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100,
>                 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
> -       PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000101,
> +       PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100,
>                 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
> -       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000101,
> +       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100,
>                 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
> -       PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000101,
> +       PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100,
>                 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0,
>                 mmpll_div_table),
> -       PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000101,
> +       PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000100,
>                 HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0,
>                 armca35pll_div_table),
> -       PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000101,
> +       PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000100,
>                 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0,
>                 armca72pll_div_table),
> -       PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000101,
> +       PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000100,
>                 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
>  };
>
> diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-mt6765.c
> index db8db1b..097bbc4 100644
> --- a/drivers/clk/mediatek/clk-mt6765.c
> +++ b/drivers/clk/mediatek/clk-mt6765.c
> @@ -747,26 +747,26 @@
>                         _pcw_reg, _pcw_shift, NULL)     \
>
>  static const struct mtk_pll_data plls[] = {
> -       PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, BIT(0),
> +       PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, 0,
>             PLL_AO, 22, 8, 0x0220, 24, 0, 0, 0, 0x0220, 0),
> -       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, BIT(0),
> +       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, 0,
>             PLL_AO, 22, 8, 0x0210, 24, 0, 0, 0, 0x0210, 0),
> -       PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, BIT(0),
> +       PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, 0,
>             PLL_AO, 22, 8, 0x0230, 24, 0, 0, 0, 0x0230, 0),
> -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, BIT(0),
> +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, 0,
>             (HAVE_RST_BAR | PLL_AO), 22, 8, 0x0240, 24, 0, 0, 0, 0x0240,
>             0),
> -       PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, BIT(0),
> +       PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, 0,
>             0, 22, 8, 0x0250, 24, 0, 0, 0, 0x0250, 0),
> -       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, BIT(0),
> +       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, 0,
>             0, 22, 8, 0x0260, 24, 0, 0, 0, 0x0260, 0),
> -       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, BIT(0),
> +       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, 0,
>             HAVE_RST_BAR, 22, 8, 0x0270, 24, 0, 0, 0, 0x0270, 0),
> -       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, BIT(0),
> +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, 0,
>             0, 22, 8, 0x0280, 24, 0, 0, 0, 0x0280, 0),
> -       PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, BIT(0),
> +       PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, 0,
>             0, 32, 8, 0x0290, 24, 0x0040, 0x000C, 0, 0x0294, 0),
> -       PLL(CLK_APMIXED_MPLL, "mpll", 0x02A0, 0x02AC, BIT(0),
> +       PLL(CLK_APMIXED_MPLL, "mpll", 0x02A0, 0x02AC, 0,
>             PLL_AO, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0),
>  };
>
> diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
> index 9766ccc..d8444ed 100644
> --- a/drivers/clk/mediatek/clk-mt6779.c
> +++ b/drivers/clk/mediatek/clk-mt6779.c
> @@ -1178,33 +1178,33 @@
>                         _pcw_chg_reg, NULL)
>
>  static const struct mtk_pll_data plls[] = {
> -       PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, BIT(0),
> +       PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,
>             PLL_AO, 0, 22, 8, 0x0204, 24, 0, 0, 0, 0x0204, 0, 0),
> -       PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, BIT(0),
> +       PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, 0,
>             PLL_AO, 0, 22, 8, 0x0214, 24, 0, 0, 0, 0x0214, 0, 0),
> -       PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, BIT(0),
> +       PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, 0,
>             PLL_AO, 0, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0, 0),
> -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, BIT(0),
> +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0,
>             (HAVE_RST_BAR), BIT(24), 22, 8, 0x0234, 24, 0, 0, 0,
>             0x0234, 0, 0),
> -       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, BIT(0),
> +       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, 0,
>             (HAVE_RST_BAR), BIT(24), 22, 8, 0x0244, 24,
>             0, 0, 0, 0x0244, 0, 0),
> -       PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, BIT(0),
> +       PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, 0,
>             0, 0, 22, 8, 0x0254, 24, 0, 0, 0, 0x0254, 0, 0),
> -       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, BIT(0),
> +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, 0,
>             0, 0, 22, 8, 0x0264, 24, 0, 0, 0, 0x0264, 0, 0),
> -       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, BIT(0),
> +       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0,
>             0, 0, 22, 8, 0x0274, 24, 0, 0, 0, 0x0274, 0, 0),
> -       PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, BIT(0),
> +       PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, 0,
>             (HAVE_RST_BAR), BIT(23), 22, 8, 0x02b4, 24,
>             0, 0, 0, 0x02b4, 0, 0),
> -       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, BIT(0),
> +       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, 0,
>             (HAVE_RST_BAR), BIT(23), 22, 8, 0x0284, 24,
>             0, 0, 0, 0x0284, 0, 0),
> -       PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, BIT(0),
> +       PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, 0,
>             0, 0, 32, 8, 0x02C0, 1, 0, 0x14, 0, 0x02C4, 0, 0x2C0),
> -       PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, BIT(0),
> +       PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, 0,
>             0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4),
>  };
>
> diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c
> index f35389a..4395423 100644
> --- a/drivers/clk/mediatek/clk-mt6797.c
> +++ b/drivers/clk/mediatek/clk-mt6797.c
> @@ -638,25 +638,25 @@ static int mtk_infrasys_init(struct platform_device *pdev)
>                         NULL)
>
>  static const struct mtk_pll_data plls[] = {
> -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000101, PLL_AO,
> +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000100, PLL_AO,
>             21, 0x220, 4, 0x0, 0x224, 0),
> -       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000011, 0, 7,
> +       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000010, 0, 7,
>             0x230, 4, 0x0, 0x234, 14),
> -       PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000101, 0, 21,
> +       PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000100, 0, 21,
>             0x244, 24, 0x0, 0x244, 0),
> -       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000121, 0, 21,
> +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000120, 0, 21,
>             0x250, 4, 0x0, 0x254, 0),
> -       PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000121, 0, 21,
> +       PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000120, 0, 21,
>             0x260, 4, 0x0, 0x264, 0),
> -       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000121, 0, 21,
> +       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000120, 0, 21,
>             0x270, 4, 0x0, 0x274, 0),
> -       PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000121, 0, 21,
> +       PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000120, 0, 21,
>             0x290, 4, 0x0, 0x294, 0),
> -       PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000121, 0, 21,
> +       PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000120, 0, 21,
>             0x2E4, 4, 0x0, 0x2E8, 0),
> -       PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000131, 0, 31,
> +       PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000130, 0, 31,
>             0x2A0, 4, 0x2A8, 0x2A4, 0),
> -       PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000131, 0, 31,
> +       PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000130, 0, 31,
>             0x2B4, 4, 0x2BC, 0x2B8, 0),
>  };
>
> diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
> index ef5947e1..3ac222c 100644
> --- a/drivers/clk/mediatek/clk-mt7622.c
> +++ b/drivers/clk/mediatek/clk-mt7622.c
> @@ -328,23 +328,23 @@
>  };
>
>  static const struct mtk_pll_data plls[] = {
> -       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
> +       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000000,

Or just 0 for consistency with clk-mt6779.c?

>             PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
> -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
> +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000000,
>             HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
> -       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
> +       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000000,
>             HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
> -       PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
> +       PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000000,
>             0, 21, 0x0300, 1, 0, 0x0304, 0),
> -       PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
> +       PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000000,
>             0, 21, 0x0314, 1, 0, 0x0318, 0),
> -       PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001,
> +       PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000000,
>             0, 31, 0x0324, 1, 0, 0x0328, 0),
> -       PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001,
> +       PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000000,
>             0, 31, 0x0334, 1, 0, 0x0338, 0),
> -       PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001,
> +       PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000000,
>             0, 21, 0x0344, 1, 0, 0x0348, 0),
> -       PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
> +       PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000000,
>             0, 21, 0x0358, 1, 0, 0x035C, 0),
>  };
>
> diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
> index b73bdf1..2d434a9 100644
> --- a/drivers/clk/mediatek/clk-mt7629.c
> +++ b/drivers/clk/mediatek/clk-mt7629.c
> @@ -335,17 +335,17 @@
>  };
>
>  static const struct mtk_pll_data plls[] = {
> -       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
> +       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000000,

ditto

>             0, 21, 0x0204, 24, 0, 0x0204, 0),
> -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
> +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000000,
>             HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
> -       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
> +       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000000,
>             HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
> -       PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
> +       PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000000,
>             0, 21, 0x0300, 1, 0, 0x0304, 0),
> -       PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
> +       PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000000,
>             0, 21, 0x0314, 1, 0, 0x0318, 0),
> -       PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
> +       PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000000,
>             0, 21, 0x0358, 1, 0, 0x035C, 0),
>  };
>
> diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
> index 8f898ac..92d8bdd 100644
> --- a/drivers/clk/mediatek/clk-mt8173.c
> +++ b/drivers/clk/mediatek/clk-mt8173.c
> @@ -972,20 +972,34 @@ struct mtk_clk_usb {
>  };
>
>  static const struct mtk_pll_data plls[] = {
> -       PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),

Why reflow? 100 chars is fine nowadays. (and also it's hard to review now ,-P)

> -       PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000001, 0, 21, 0x214, 24, 0x0, 0x214, 0),
> -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
> -       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000001, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
> -       PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table),
> -       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000001, 0, 21, 0x250, 4, 0x0, 0x254, 0),
> -       PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000001, 0, 21, 0x260, 4, 0x0, 0x264, 0),
> -       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000001, 0, 21, 0x270, 4, 0x0, 0x274, 0),
> -       PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x00000001, 0, 21, 0x280, 4, 0x0, 0x284, 0),
> -       PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0x00000001, 0, 21, 0x290, 4, 0x0, 0x294, 0),
> -       PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0x00000001, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
> -       PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0x00000001, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
> -       PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0x00000001, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
> -       PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0x00000001, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
> +       PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000000,
> +               0, 21, 0x204, 24, 0x0, 0x204, 0),
> +       PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000000,
> +               0, 21, 0x214, 24, 0x0, 0x214, 0),
> +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100,
> +               HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
> +       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000,
> +               HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
> +       PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000000,
> +               0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table),
> +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000000,
> +               0, 21, 0x250, 4, 0x0, 0x254, 0),
> +       PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000000,
> +               0, 21, 0x260, 4, 0x0, 0x264, 0),
> +       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000000,
> +               0, 21, 0x270, 4, 0x0, 0x274, 0),
> +       PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x00000000,
> +               0, 21, 0x280, 4, 0x0, 0x284, 0),
> +       PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0x00000000,
> +               0, 21, 0x290, 4, 0x0, 0x294, 0),
> +       PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0x00000000,
> +               0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
> +       PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0x00000000,
> +               0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
> +       PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0x00000000,
> +               0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
> +       PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0x00000000,
> +               0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
>  };
>
>  static void __init mtk_apmixedsys_init(struct device_node *node)
> diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
> index 5046852..e1b0a13 100644
> --- a/drivers/clk/mediatek/clk-mt8183.c
> +++ b/drivers/clk/mediatek/clk-mt8183.c
> @@ -1121,34 +1121,34 @@
>  };
>
>  static const struct mtk_pll_data plls[] = {
> -       PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0x00000001,
> +       PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0x00000000,
>                 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0,
>                 0x0204, 0, 0, armpll_div_table),
> -       PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0x00000001,
> +       PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0x00000000,
>                 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0,
>                 0x0214, 0, 0, armpll_div_table),
> -       PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0x00000001,
> +       PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0x00000000,
>                 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0,
>                 0x0294, 0, 0),
> -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0x00000001,
> +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0x00000000,
>                 HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0,
>                 0x0224, 0, 0),
> -       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0x00000001,
> +       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0x00000000,
>                 HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0,
>                 0x0234, 0, 0),
> -       PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000001,
> +       PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000000,
>                 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0,
>                 mfgpll_div_table),
> -       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000001,
> +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000000,
>                 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0),
> -       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0x00000001,
> +       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0x00000000,
>                 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0),
> -       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0x00000001,
> +       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0x00000000,
>                 HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0,
>                 0x0274, 0, 0),
> -       PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000001,
> +       PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000000,
>                 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0),
> -       PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0x00000001,
> +       PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0x00000000,
>                 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
>  };
>
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index f440f2cd..3c79e1a 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -247,8 +247,10 @@ static int mtk_pll_prepare(struct clk_hw *hw)
>         writel(r, pll->pwr_addr);
>         udelay(1);
>
> -       r = readl(pll->base_addr + REG_CON0);
> -       r |= pll->data->en_mask;
> +       r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN;
> +       writel(r, pll->base_addr + REG_CON0);
> +
> +       r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
>         writel(r, pll->base_addr + REG_CON0);

As a small optimization, you can do:

if (pll->data->en_mask) {
   r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
   writel(r, pll->base_addr + REG_CON0);
}

>
>         __mtk_pll_tuner_enable(pll);
> @@ -278,6 +280,10 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
>         __mtk_pll_tuner_disable(pll);
>
>         r = readl(pll->base_addr + REG_CON0);
> +       r &= ~pll->data->en_mask;

Move this to one line? (so that the code looks symmetrical, too?)

> +       writel(r, pll->base_addr + REG_CON0);
> +
> +       r = readl(pll->base_addr + REG_CON0);
>         r &= ~CON0_BASE_EN;

ditto?

>         writel(r, pll->base_addr + REG_CON0);
>
> --
> 1.8.1.1.dirty

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v2 4/5] clk: mediatek: Add configurable enable control to mtk_pll_data
  2020-07-29  8:44 ` [PATCH v2 4/5] clk: mediatek: Add configurable enable control to mtk_pll_data Weiyi Lu
@ 2020-07-29 10:58   ` Nicolas Boichat
  2020-08-11  6:43     ` Weiyi Lu
  0 siblings, 1 reply; 17+ messages in thread
From: Nicolas Boichat @ 2020-07-29 10:58 UTC (permalink / raw)
  To: Weiyi Lu
  Cc: Matthias Brugger, Rob Herring, Stephen Boyd, James Liao,
	linux-arm Mailing List, lkml,
	moderated list:ARM/Mediatek SoC support, linux-clk,
	srv_heupstream, Wendell Lin

On Wed, Jul 29, 2020 at 4:44 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
>
> In all MediaTek PLL design, bit0 of CON0 register is always
> the enable bit.
> However, there's a special case of usbpll on MT8192.
> The enable bit of usbpll is moved to bit2 of other register.
> Add configurable en_reg and pll_en_bit for enable control or
> default 0 where pll data are static variables.
> Hence, CON0_BASE_EN could also be removed.
> And there might have another special case on other chips,
> the enable bit is still on CON0 register but not at bit0.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
>  drivers/clk/mediatek/clk-mtk.h |  2 ++
>  drivers/clk/mediatek/clk-pll.c | 18 +++++++++++-------
>  2 files changed, 13 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index c3d6756..810eb97 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -233,6 +233,8 @@ struct mtk_pll_data {
>         uint32_t pcw_chg_reg;
>         const struct mtk_pll_div_table *div_table;
>         const char *parent_name;
> +       uint32_t en_reg;
> +       uint8_t pll_en_bit;
>  };
>
>  void mtk_clk_register_plls(struct device_node *node,
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index 3c79e1a..1434e99 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -16,7 +16,6 @@
>  #define REG_CON0               0
>  #define REG_CON1               4
>
> -#define CON0_BASE_EN           BIT(0)
>  #define CON0_PWR_ON            BIT(0)
>  #define CON0_ISO_EN            BIT(1)
>  #define PCW_CHG_MASK           BIT(31)
> @@ -44,6 +43,7 @@ struct mtk_clk_pll {
>         void __iomem    *tuner_en_addr;
>         void __iomem    *pcw_addr;
>         void __iomem    *pcw_chg_addr;
> +       void __iomem    *en_addr;
>         const struct mtk_pll_data *data;
>  };
>
> @@ -56,7 +56,7 @@ static int mtk_pll_is_prepared(struct clk_hw *hw)
>  {
>         struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
>
> -       return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
> +       return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
>  }
>
>  static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
> @@ -247,8 +247,8 @@ static int mtk_pll_prepare(struct clk_hw *hw)
>         writel(r, pll->pwr_addr);
>         udelay(1);
>
> -       r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN;
> -       writel(r, pll->base_addr + REG_CON0);
> +       r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);
> +       writel(r, pll->en_addr);
>
>         r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
>         writel(r, pll->base_addr + REG_CON0);
> @@ -283,9 +283,9 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
>         r &= ~pll->data->en_mask;
>         writel(r, pll->base_addr + REG_CON0);
>
> -       r = readl(pll->base_addr + REG_CON0);
> -       r &= ~CON0_BASE_EN;
> -       writel(r, pll->base_addr + REG_CON0);
> +       r = readl(pll->en_addr);
> +       r &= ~BIT(pll->data->pll_en_bit);

1 line, but that'll come naturally from the change I requested in the
previous patch.

> +       writel(r, pll->en_addr);
>
>         r = readl(pll->pwr_addr) | CON0_ISO_EN;
>         writel(r, pll->pwr_addr);
> @@ -327,6 +327,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
>                 pll->tuner_addr = base + data->tuner_reg;
>         if (data->tuner_en_reg)
>                 pll->tuner_en_addr = base + data->tuner_en_reg;
> +       if (data->en_reg)
> +               pll->en_addr = base + data->en_reg;
> +       else
> +               pll->en_addr = pll->base_addr + REG_CON0;

Don't you need to set pll->data->pll_en_bit to CON0_BASE_EN here?
(which probably means that you need to add a pll->en_bit field to
struct mtk_clk_pll)

>         pll->hw.init = &init;
>         pll->data = data;
>
> --
> 1.8.1.1.dirty

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v2 3/5] clk: mediatek: Fix asymmetrical PLL enable and disable control
  2020-07-29 10:51   ` Nicolas Boichat
@ 2020-07-29 11:02     ` Nicolas Boichat
  2020-08-11  6:34       ` Weiyi Lu
  2020-08-11  6:50     ` Weiyi Lu
  1 sibling, 1 reply; 17+ messages in thread
From: Nicolas Boichat @ 2020-07-29 11:02 UTC (permalink / raw)
  To: Weiyi Lu
  Cc: Matthias Brugger, Rob Herring, Stephen Boyd, James Liao,
	linux-arm Mailing List, lkml,
	moderated list:ARM/Mediatek SoC support, linux-clk,
	srv_heupstream, Wendell Lin

On Wed, Jul 29, 2020 at 6:51 PM Nicolas Boichat <drinkcat@chromium.org> wrote:
>
> On Wed, Jul 29, 2020 at 4:44 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
> >
> > The en_mask actually is a combination of divider enable mask
> > and pll enable bit(bit0).
> > Before this patch, we enabled both divider mask and bit0 in prepare(),
> > but only cleared the bit0 in unprepare().
> > Now, setting the enable register(CON0) in 2 steps: first divider mask,
> > then bit0 during prepare(), vice versa.
> > Hence, en_mask will only be used as divider enable mask.
> > Meanwhile, all the SoC PLL data are updated.
>
> I like this a lot better, most changes look fine, just a few nits.
>
> >
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > ---
> >  drivers/clk/mediatek/clk-mt2701.c | 26 ++++++++++++------------
> >  drivers/clk/mediatek/clk-mt2712.c | 30 ++++++++++++++--------------
> >  drivers/clk/mediatek/clk-mt6765.c | 20 +++++++++----------
> >  drivers/clk/mediatek/clk-mt6779.c | 24 +++++++++++-----------
> >  drivers/clk/mediatek/clk-mt6797.c | 20 +++++++++----------
> >  drivers/clk/mediatek/clk-mt7622.c | 18 ++++++++---------
> >  drivers/clk/mediatek/clk-mt7629.c | 12 +++++------
> >  drivers/clk/mediatek/clk-mt8173.c | 42 ++++++++++++++++++++++++++-------------
> >  drivers/clk/mediatek/clk-mt8183.c | 22 ++++++++++----------
> >  drivers/clk/mediatek/clk-pll.c    | 10 ++++++++--
> >  10 files changed, 122 insertions(+), 102 deletions(-)
> >
[snip]
> > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> > index f440f2cd..3c79e1a 100644
> > --- a/drivers/clk/mediatek/clk-pll.c
> > +++ b/drivers/clk/mediatek/clk-pll.c
> > @@ -247,8 +247,10 @@ static int mtk_pll_prepare(struct clk_hw *hw)
> >         writel(r, pll->pwr_addr);
> >         udelay(1);
> >
> > -       r = readl(pll->base_addr + REG_CON0);
> > -       r |= pll->data->en_mask;
> > +       r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN;
> > +       writel(r, pll->base_addr + REG_CON0);
> > +
> > +       r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;

One more question. I have the feeling that CON0_BASE_EN is what
enables the clock for good (and pll->data->en_mask is just an
additional setting/mask, since you could disable the clock by simply
clearing CON0_BASE_EN). Shouldn't you set pll->data->en_mask _first_,
then CON0_BASE_EN?

> >         writel(r, pll->base_addr + REG_CON0);
>
> As a small optimization, you can do:
>
> if (pll->data->en_mask) {
>    r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
>    writel(r, pll->base_addr + REG_CON0);
> }
>
> >
> >         __mtk_pll_tuner_enable(pll);
> > @@ -278,6 +280,10 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
> >         __mtk_pll_tuner_disable(pll);
> >
> >         r = readl(pll->base_addr + REG_CON0);
> > +       r &= ~pll->data->en_mask;
>
> Move this to one line? (so that the code looks symmetrical, too?)
>
> > +       writel(r, pll->base_addr + REG_CON0);
> > +
> > +       r = readl(pll->base_addr + REG_CON0);
> >         r &= ~CON0_BASE_EN;

And ditto, ~CON0_BASE_EN then ~pll->data->en_mask?

>
> ditto?
>
> >         writel(r, pll->base_addr + REG_CON0);
> >
> > --
> > 1.8.1.1.dirty

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v2 3/5] clk: mediatek: Fix asymmetrical PLL enable and disable control
  2020-07-29 11:02     ` Nicolas Boichat
@ 2020-08-11  6:34       ` Weiyi Lu
  0 siblings, 0 replies; 17+ messages in thread
From: Weiyi Lu @ 2020-08-11  6:34 UTC (permalink / raw)
  To: Nicolas Boichat
  Cc: Matthias Brugger, Rob Herring, Stephen Boyd, James Liao,
	linux-arm Mailing List, lkml,
	moderated list:ARM/Mediatek SoC support, linux-clk,
	srv_heupstream, Wendell Lin

On Wed, 2020-07-29 at 19:02 +0800, Nicolas Boichat wrote:
> On Wed, Jul 29, 2020 at 6:51 PM Nicolas Boichat <drinkcat@chromium.org> wrote:
> >
> > On Wed, Jul 29, 2020 at 4:44 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
> > >
> > > The en_mask actually is a combination of divider enable mask
> > > and pll enable bit(bit0).
> > > Before this patch, we enabled both divider mask and bit0 in prepare(),
> > > but only cleared the bit0 in unprepare().
> > > Now, setting the enable register(CON0) in 2 steps: first divider mask,
> > > then bit0 during prepare(), vice versa.
> > > Hence, en_mask will only be used as divider enable mask.
> > > Meanwhile, all the SoC PLL data are updated.
> >
> > I like this a lot better, most changes look fine, just a few nits.
> >
> > >
> > > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > > ---
> > >  drivers/clk/mediatek/clk-mt2701.c | 26 ++++++++++++------------
> > >  drivers/clk/mediatek/clk-mt2712.c | 30 ++++++++++++++--------------
> > >  drivers/clk/mediatek/clk-mt6765.c | 20 +++++++++----------
> > >  drivers/clk/mediatek/clk-mt6779.c | 24 +++++++++++-----------
> > >  drivers/clk/mediatek/clk-mt6797.c | 20 +++++++++----------
> > >  drivers/clk/mediatek/clk-mt7622.c | 18 ++++++++---------
> > >  drivers/clk/mediatek/clk-mt7629.c | 12 +++++------
> > >  drivers/clk/mediatek/clk-mt8173.c | 42 ++++++++++++++++++++++++++-------------
> > >  drivers/clk/mediatek/clk-mt8183.c | 22 ++++++++++----------
> > >  drivers/clk/mediatek/clk-pll.c    | 10 ++++++++--
> > >  10 files changed, 122 insertions(+), 102 deletions(-)
> > >
> [snip]
> > > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> > > index f440f2cd..3c79e1a 100644
> > > --- a/drivers/clk/mediatek/clk-pll.c
> > > +++ b/drivers/clk/mediatek/clk-pll.c
> > > @@ -247,8 +247,10 @@ static int mtk_pll_prepare(struct clk_hw *hw)
> > >         writel(r, pll->pwr_addr);
> > >         udelay(1);
> > >
> > > -       r = readl(pll->base_addr + REG_CON0);
> > > -       r |= pll->data->en_mask;
> > > +       r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN;
> > > +       writel(r, pll->base_addr + REG_CON0);
> > > +
> > > +       r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
> 
> One more question. I have the feeling that CON0_BASE_EN is what
> enables the clock for good (and pll->data->en_mask is just an
> additional setting/mask, since you could disable the clock by simply
> clearing CON0_BASE_EN). Shouldn't you set pll->data->en_mask _first_,
> then CON0_BASE_EN?
> 

Hi Nicolas,

Actually I had the same question when I first saw it.
But this is the recommended sequence in the PLL application notes.

preapre
{
    | CON0_BASE_EN;
    | pll->data->en_mask;
}

unprepare
{
    ~pll->data->en_mask;
    ~CON0_BASE_EN;
}

> > >         writel(r, pll->base_addr + REG_CON0);
> >
> > As a small optimization, you can do:
> >
> > if (pll->data->en_mask) {
> >    r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
> >    writel(r, pll->base_addr + REG_CON0);
> > }
> >
> > >
> > >         __mtk_pll_tuner_enable(pll);
> > > @@ -278,6 +280,10 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
> > >         __mtk_pll_tuner_disable(pll);
> > >
> > >         r = readl(pll->base_addr + REG_CON0);
> > > +       r &= ~pll->data->en_mask;
> >
> > Move this to one line? (so that the code looks symmetrical, too?)
> >
> > > +       writel(r, pll->base_addr + REG_CON0);
> > > +
> > > +       r = readl(pll->base_addr + REG_CON0);
> > >         r &= ~CON0_BASE_EN;
> 
> And ditto, ~CON0_BASE_EN then ~pll->data->en_mask?
> 
> >
> > ditto?
> >
> > >         writel(r, pll->base_addr + REG_CON0);
> > >
> > > --
> > > 1.8.1.1.dirty


^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v2 4/5] clk: mediatek: Add configurable enable control to mtk_pll_data
  2020-07-29 10:58   ` Nicolas Boichat
@ 2020-08-11  6:43     ` Weiyi Lu
  2020-08-11  7:28       ` Nicolas Boichat
  0 siblings, 1 reply; 17+ messages in thread
From: Weiyi Lu @ 2020-08-11  6:43 UTC (permalink / raw)
  To: Nicolas Boichat
  Cc: Rob Herring, srv_heupstream, James Liao, Stephen Boyd, lkml,
	moderated list:ARM/Mediatek SoC support, Matthias Brugger,
	Wendell Lin, linux-clk, linux-arm Mailing List

On Wed, 2020-07-29 at 18:58 +0800, Nicolas Boichat wrote:
> On Wed, Jul 29, 2020 at 4:44 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
> >
> > In all MediaTek PLL design, bit0 of CON0 register is always
> > the enable bit.
> > However, there's a special case of usbpll on MT8192.
> > The enable bit of usbpll is moved to bit2 of other register.
> > Add configurable en_reg and pll_en_bit for enable control or
> > default 0 where pll data are static variables.
> > Hence, CON0_BASE_EN could also be removed.
> > And there might have another special case on other chips,
> > the enable bit is still on CON0 register but not at bit0.
> >
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > ---
> >  drivers/clk/mediatek/clk-mtk.h |  2 ++
> >  drivers/clk/mediatek/clk-pll.c | 18 +++++++++++-------
> >  2 files changed, 13 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> > index c3d6756..810eb97 100644
> > --- a/drivers/clk/mediatek/clk-mtk.h
> > +++ b/drivers/clk/mediatek/clk-mtk.h
> > @@ -233,6 +233,8 @@ struct mtk_pll_data {
> >         uint32_t pcw_chg_reg;
> >         const struct mtk_pll_div_table *div_table;
> >         const char *parent_name;
> > +       uint32_t en_reg;
> > +       uint8_t pll_en_bit;
> >  };
> >
> >  void mtk_clk_register_plls(struct device_node *node,
> > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> > index 3c79e1a..1434e99 100644
> > --- a/drivers/clk/mediatek/clk-pll.c
> > +++ b/drivers/clk/mediatek/clk-pll.c
> > @@ -16,7 +16,6 @@
> >  #define REG_CON0               0
> >  #define REG_CON1               4
> >
> > -#define CON0_BASE_EN           BIT(0)
> >  #define CON0_PWR_ON            BIT(0)
> >  #define CON0_ISO_EN            BIT(1)
> >  #define PCW_CHG_MASK           BIT(31)
> > @@ -44,6 +43,7 @@ struct mtk_clk_pll {
> >         void __iomem    *tuner_en_addr;
> >         void __iomem    *pcw_addr;
> >         void __iomem    *pcw_chg_addr;
> > +       void __iomem    *en_addr;
> >         const struct mtk_pll_data *data;
> >  };
> >
> > @@ -56,7 +56,7 @@ static int mtk_pll_is_prepared(struct clk_hw *hw)
> >  {
> >         struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
> >
> > -       return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
> > +       return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
> >  }
> >
> >  static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
> > @@ -247,8 +247,8 @@ static int mtk_pll_prepare(struct clk_hw *hw)
> >         writel(r, pll->pwr_addr);
> >         udelay(1);
> >
> > -       r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN;
> > -       writel(r, pll->base_addr + REG_CON0);
> > +       r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);
> > +       writel(r, pll->en_addr);
> >
> >         r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
> >         writel(r, pll->base_addr + REG_CON0);
> > @@ -283,9 +283,9 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
> >         r &= ~pll->data->en_mask;
> >         writel(r, pll->base_addr + REG_CON0);
> >
> > -       r = readl(pll->base_addr + REG_CON0);
> > -       r &= ~CON0_BASE_EN;
> > -       writel(r, pll->base_addr + REG_CON0);
> > +       r = readl(pll->en_addr);
> > +       r &= ~BIT(pll->data->pll_en_bit);
> 
> 1 line, but that'll come naturally from the change I requested in the
> previous patch.
> 

OK, I'll put it into one line in previous patch.

> > +       writel(r, pll->en_addr);
> >
> >         r = readl(pll->pwr_addr) | CON0_ISO_EN;
> >         writel(r, pll->pwr_addr);
> > @@ -327,6 +327,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
> >                 pll->tuner_addr = base + data->tuner_reg;
> >         if (data->tuner_en_reg)
> >                 pll->tuner_en_addr = base + data->tuner_en_reg;
> > +       if (data->en_reg)
> > +               pll->en_addr = base + data->en_reg;
> > +       else
> > +               pll->en_addr = pll->base_addr + REG_CON0;
> 
> Don't you need to set pll->data->pll_en_bit to CON0_BASE_EN here?
> (which probably means that you need to add a pll->en_bit field to
> struct mtk_clk_pll)
> 

Because all mtk_clk_pll data are static variables, en_bit would be 0 if
NO value assigned.

r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);
writel(r, pll->en_addr);


> >         pll->hw.init = &init;
> >         pll->data = data;
> >
> > --
> > 1.8.1.1.dirty
> 
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> https://urldefense.com/v3/__http://lists.infradead.org/mailman/listinfo/linux-mediatek__;!!CTRNKA9wMg0ARbw!2XvAXZuAJJjXV1jAxEzu0cYVZCD7vQmuOtJtwHeW_npFbEIwVSZMMXsTkEXJEAXv$ 


^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v2 3/5] clk: mediatek: Fix asymmetrical PLL enable and disable control
  2020-07-29 10:51   ` Nicolas Boichat
  2020-07-29 11:02     ` Nicolas Boichat
@ 2020-08-11  6:50     ` Weiyi Lu
  1 sibling, 0 replies; 17+ messages in thread
From: Weiyi Lu @ 2020-08-11  6:50 UTC (permalink / raw)
  To: Nicolas Boichat
  Cc: Matthias Brugger, Rob Herring, Stephen Boyd, James Liao,
	linux-arm Mailing List, lkml,
	moderated list:ARM/Mediatek SoC support, linux-clk,
	srv_heupstream, Wendell Lin

On Wed, 2020-07-29 at 18:51 +0800, Nicolas Boichat wrote:
> On Wed, Jul 29, 2020 at 4:44 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
> >
> > The en_mask actually is a combination of divider enable mask
> > and pll enable bit(bit0).
> > Before this patch, we enabled both divider mask and bit0 in prepare(),
> > but only cleared the bit0 in unprepare().
> > Now, setting the enable register(CON0) in 2 steps: first divider mask,
> > then bit0 during prepare(), vice versa.
> > Hence, en_mask will only be used as divider enable mask.
> > Meanwhile, all the SoC PLL data are updated.
> 
> I like this a lot better, most changes look fine, just a few nits.
> 
> >
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > ---
> >  drivers/clk/mediatek/clk-mt2701.c | 26 ++++++++++++------------
> >  drivers/clk/mediatek/clk-mt2712.c | 30 ++++++++++++++--------------
> >  drivers/clk/mediatek/clk-mt6765.c | 20 +++++++++----------
> >  drivers/clk/mediatek/clk-mt6779.c | 24 +++++++++++-----------
> >  drivers/clk/mediatek/clk-mt6797.c | 20 +++++++++----------
> >  drivers/clk/mediatek/clk-mt7622.c | 18 ++++++++---------
> >  drivers/clk/mediatek/clk-mt7629.c | 12 +++++------
> >  drivers/clk/mediatek/clk-mt8173.c | 42 ++++++++++++++++++++++++++-------------
> >  drivers/clk/mediatek/clk-mt8183.c | 22 ++++++++++----------
> >  drivers/clk/mediatek/clk-pll.c    | 10 ++++++++--
> >  10 files changed, 122 insertions(+), 102 deletions(-)
> >
> > diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
> > index 695be0f..10d0b92 100644
> > --- a/drivers/clk/mediatek/clk-mt2701.c
> > +++ b/drivers/clk/mediatek/clk-mt2701.c
> > @@ -934,31 +934,31 @@ static int mtk_pericfg_init(struct platform_device *pdev)
> >         }
> >
> >  static const struct mtk_pll_data apmixed_plls[] = {
> > -       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000001,
> > +       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000000,
> >                         PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0),
> > -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000001,
> > +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000000,
> >                   HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),
> > -       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000001,
> > +       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000000,
> >                   HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),
> > -       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0,
> > +       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000000, 0,
> >                                 21, 0x230, 4, 0x0, 0x234, 0),
> > -       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
> > +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000000, 0,
> >                                 21, 0x240, 4, 0x0, 0x244, 0),
> > -       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
> > +       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000000, 0,
> >                                 21, 0x250, 4, 0x0, 0x254, 0),
> > -       PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
> > +       PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000000, 0,
> >                                 31, 0x270, 4, 0x0, 0x274, 0),
> > -       PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
> > +       PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000000, 0,
> >                                 31, 0x280, 4, 0x0, 0x284, 0),
> > -       PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
> > +       PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000000, 0,
> >                                 31, 0x290, 4, 0x0, 0x294, 0),
> > -       PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
> > +       PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000000, 0,
> >                                 31, 0x2a0, 4, 0x0, 0x2a4, 0),
> > -       PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0,
> > +       PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000000, 0,
> >                                 31, 0x2b0, 4, 0x0, 0x2b4, 0),
> > -       PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0,
> > +       PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000000, 0,
> >                                 31, 0x2c0, 4, 0x0, 0x2c4, 0),
> > -       PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0,
> > +       PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000000, 0,
> >                                 21, 0x2d0, 4, 0x0, 0x2d4, 0),
> >  };
> >
> > diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
> > index a3bd9a1..fd81162 100644
> > --- a/drivers/clk/mediatek/clk-mt2712.c
> > +++ b/drivers/clk/mediatek/clk-mt2712.c
> > @@ -1222,38 +1222,38 @@
> >  };
> >
> >  static const struct mtk_pll_data plls[] = {
> > -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000101,
> > +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100,
> >                 HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
> > -       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000101,
> > +       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100,
> >                 HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
> > -       PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000101,
> > +       PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100,
> >                 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
> > -       PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000101,
> > +       PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100,
> >                 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
> > -       PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000101,
> > +       PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100,
> >                 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
> > -       PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000101,
> > +       PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100,
> >                 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
> > -       PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000101,
> > +       PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100,
> >                 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
> > -       PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000101,
> > +       PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100,
> >                 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
> > -       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000101,
> > +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100,
> >                 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
> > -       PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000101,
> > +       PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100,
> >                 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
> > -       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000101,
> > +       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100,
> >                 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
> > -       PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000101,
> > +       PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100,
> >                 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0,
> >                 mmpll_div_table),
> > -       PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000101,
> > +       PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000100,
> >                 HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0,
> >                 armca35pll_div_table),
> > -       PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000101,
> > +       PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000100,
> >                 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0,
> >                 armca72pll_div_table),
> > -       PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000101,
> > +       PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000100,
> >                 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
> >  };
> >
> > diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-mt6765.c
> > index db8db1b..097bbc4 100644
> > --- a/drivers/clk/mediatek/clk-mt6765.c
> > +++ b/drivers/clk/mediatek/clk-mt6765.c
> > @@ -747,26 +747,26 @@
> >                         _pcw_reg, _pcw_shift, NULL)     \
> >
> >  static const struct mtk_pll_data plls[] = {
> > -       PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, BIT(0),
> > +       PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, 0,
> >             PLL_AO, 22, 8, 0x0220, 24, 0, 0, 0, 0x0220, 0),
> > -       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, BIT(0),
> > +       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, 0,
> >             PLL_AO, 22, 8, 0x0210, 24, 0, 0, 0, 0x0210, 0),
> > -       PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, BIT(0),
> > +       PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, 0,
> >             PLL_AO, 22, 8, 0x0230, 24, 0, 0, 0, 0x0230, 0),
> > -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, BIT(0),
> > +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, 0,
> >             (HAVE_RST_BAR | PLL_AO), 22, 8, 0x0240, 24, 0, 0, 0, 0x0240,
> >             0),
> > -       PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, BIT(0),
> > +       PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, 0,
> >             0, 22, 8, 0x0250, 24, 0, 0, 0, 0x0250, 0),
> > -       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, BIT(0),
> > +       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, 0,
> >             0, 22, 8, 0x0260, 24, 0, 0, 0, 0x0260, 0),
> > -       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, BIT(0),
> > +       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, 0,
> >             HAVE_RST_BAR, 22, 8, 0x0270, 24, 0, 0, 0, 0x0270, 0),
> > -       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, BIT(0),
> > +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, 0,
> >             0, 22, 8, 0x0280, 24, 0, 0, 0, 0x0280, 0),
> > -       PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, BIT(0),
> > +       PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, 0,
> >             0, 32, 8, 0x0290, 24, 0x0040, 0x000C, 0, 0x0294, 0),
> > -       PLL(CLK_APMIXED_MPLL, "mpll", 0x02A0, 0x02AC, BIT(0),
> > +       PLL(CLK_APMIXED_MPLL, "mpll", 0x02A0, 0x02AC, 0,
> >             PLL_AO, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0),
> >  };
> >
> > diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
> > index 9766ccc..d8444ed 100644
> > --- a/drivers/clk/mediatek/clk-mt6779.c
> > +++ b/drivers/clk/mediatek/clk-mt6779.c
> > @@ -1178,33 +1178,33 @@
> >                         _pcw_chg_reg, NULL)
> >
> >  static const struct mtk_pll_data plls[] = {
> > -       PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, BIT(0),
> > +       PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,
> >             PLL_AO, 0, 22, 8, 0x0204, 24, 0, 0, 0, 0x0204, 0, 0),
> > -       PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, BIT(0),
> > +       PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, 0,
> >             PLL_AO, 0, 22, 8, 0x0214, 24, 0, 0, 0, 0x0214, 0, 0),
> > -       PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, BIT(0),
> > +       PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, 0,
> >             PLL_AO, 0, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0, 0),
> > -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, BIT(0),
> > +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0,
> >             (HAVE_RST_BAR), BIT(24), 22, 8, 0x0234, 24, 0, 0, 0,
> >             0x0234, 0, 0),
> > -       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, BIT(0),
> > +       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, 0,
> >             (HAVE_RST_BAR), BIT(24), 22, 8, 0x0244, 24,
> >             0, 0, 0, 0x0244, 0, 0),
> > -       PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, BIT(0),
> > +       PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, 0,
> >             0, 0, 22, 8, 0x0254, 24, 0, 0, 0, 0x0254, 0, 0),
> > -       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, BIT(0),
> > +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, 0,
> >             0, 0, 22, 8, 0x0264, 24, 0, 0, 0, 0x0264, 0, 0),
> > -       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, BIT(0),
> > +       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0,
> >             0, 0, 22, 8, 0x0274, 24, 0, 0, 0, 0x0274, 0, 0),
> > -       PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, BIT(0),
> > +       PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, 0,
> >             (HAVE_RST_BAR), BIT(23), 22, 8, 0x02b4, 24,
> >             0, 0, 0, 0x02b4, 0, 0),
> > -       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, BIT(0),
> > +       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, 0,
> >             (HAVE_RST_BAR), BIT(23), 22, 8, 0x0284, 24,
> >             0, 0, 0, 0x0284, 0, 0),
> > -       PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, BIT(0),
> > +       PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, 0,
> >             0, 0, 32, 8, 0x02C0, 1, 0, 0x14, 0, 0x02C4, 0, 0x2C0),
> > -       PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, BIT(0),
> > +       PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, 0,
> >             0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4),
> >  };
> >
> > diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c
> > index f35389a..4395423 100644
> > --- a/drivers/clk/mediatek/clk-mt6797.c
> > +++ b/drivers/clk/mediatek/clk-mt6797.c
> > @@ -638,25 +638,25 @@ static int mtk_infrasys_init(struct platform_device *pdev)
> >                         NULL)
> >
> >  static const struct mtk_pll_data plls[] = {
> > -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000101, PLL_AO,
> > +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000100, PLL_AO,
> >             21, 0x220, 4, 0x0, 0x224, 0),
> > -       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000011, 0, 7,
> > +       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000010, 0, 7,
> >             0x230, 4, 0x0, 0x234, 14),
> > -       PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000101, 0, 21,
> > +       PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000100, 0, 21,
> >             0x244, 24, 0x0, 0x244, 0),
> > -       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000121, 0, 21,
> > +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000120, 0, 21,
> >             0x250, 4, 0x0, 0x254, 0),
> > -       PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000121, 0, 21,
> > +       PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000120, 0, 21,
> >             0x260, 4, 0x0, 0x264, 0),
> > -       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000121, 0, 21,
> > +       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000120, 0, 21,
> >             0x270, 4, 0x0, 0x274, 0),
> > -       PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000121, 0, 21,
> > +       PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000120, 0, 21,
> >             0x290, 4, 0x0, 0x294, 0),
> > -       PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000121, 0, 21,
> > +       PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000120, 0, 21,
> >             0x2E4, 4, 0x0, 0x2E8, 0),
> > -       PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000131, 0, 31,
> > +       PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000130, 0, 31,
> >             0x2A0, 4, 0x2A8, 0x2A4, 0),
> > -       PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000131, 0, 31,
> > +       PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000130, 0, 31,
> >             0x2B4, 4, 0x2BC, 0x2B8, 0),
> >  };
> >
> > diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
> > index ef5947e1..3ac222c 100644
> > --- a/drivers/clk/mediatek/clk-mt7622.c
> > +++ b/drivers/clk/mediatek/clk-mt7622.c
> > @@ -328,23 +328,23 @@
> >  };
> >
> >  static const struct mtk_pll_data plls[] = {
> > -       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
> > +       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000000,
> 
> Or just 0 for consistency with clk-mt6779.c?
> 

OK, will fix it in next version.

> >             PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
> > -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
> > +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000000,
> >             HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
> > -       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
> > +       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000000,
> >             HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
> > -       PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
> > +       PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000000,
> >             0, 21, 0x0300, 1, 0, 0x0304, 0),
> > -       PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
> > +       PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000000,
> >             0, 21, 0x0314, 1, 0, 0x0318, 0),
> > -       PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001,
> > +       PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000000,
> >             0, 31, 0x0324, 1, 0, 0x0328, 0),
> > -       PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001,
> > +       PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000000,
> >             0, 31, 0x0334, 1, 0, 0x0338, 0),
> > -       PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001,
> > +       PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000000,
> >             0, 21, 0x0344, 1, 0, 0x0348, 0),
> > -       PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
> > +       PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000000,
> >             0, 21, 0x0358, 1, 0, 0x035C, 0),
> >  };
> >
> > diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
> > index b73bdf1..2d434a9 100644
> > --- a/drivers/clk/mediatek/clk-mt7629.c
> > +++ b/drivers/clk/mediatek/clk-mt7629.c
> > @@ -335,17 +335,17 @@
> >  };
> >
> >  static const struct mtk_pll_data plls[] = {
> > -       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
> > +       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000000,
> 
> ditto
> 

Got it.

> >             0, 21, 0x0204, 24, 0, 0x0204, 0),
> > -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
> > +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000000,
> >             HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
> > -       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
> > +       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000000,
> >             HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
> > -       PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
> > +       PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000000,
> >             0, 21, 0x0300, 1, 0, 0x0304, 0),
> > -       PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
> > +       PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000000,
> >             0, 21, 0x0314, 1, 0, 0x0318, 0),
> > -       PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
> > +       PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000000,
> >             0, 21, 0x0358, 1, 0, 0x035C, 0),
> >  };
> >
> > diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
> > index 8f898ac..92d8bdd 100644
> > --- a/drivers/clk/mediatek/clk-mt8173.c
> > +++ b/drivers/clk/mediatek/clk-mt8173.c
> > @@ -972,20 +972,34 @@ struct mtk_clk_usb {
> >  };
> >
> >  static const struct mtk_pll_data plls[] = {
> > -       PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
> 
> Why reflow? 100 chars is fine nowadays. (and also it's hard to review now ,-P)
> 

Thanks.I can take advantage of the new line length limit.

> > -       PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000001, 0, 21, 0x214, 24, 0x0, 0x214, 0),
> > -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
> > -       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000001, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
> > -       PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table),
> > -       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000001, 0, 21, 0x250, 4, 0x0, 0x254, 0),
> > -       PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000001, 0, 21, 0x260, 4, 0x0, 0x264, 0),
> > -       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000001, 0, 21, 0x270, 4, 0x0, 0x274, 0),
> > -       PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x00000001, 0, 21, 0x280, 4, 0x0, 0x284, 0),
> > -       PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0x00000001, 0, 21, 0x290, 4, 0x0, 0x294, 0),
> > -       PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0x00000001, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
> > -       PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0x00000001, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
> > -       PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0x00000001, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
> > -       PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0x00000001, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
> > +       PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000000,
> > +               0, 21, 0x204, 24, 0x0, 0x204, 0),
> > +       PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000000,
> > +               0, 21, 0x214, 24, 0x0, 0x214, 0),
> > +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100,
> > +               HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
> > +       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000,
> > +               HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
> > +       PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000000,
> > +               0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table),
> > +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000000,
> > +               0, 21, 0x250, 4, 0x0, 0x254, 0),
> > +       PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000000,
> > +               0, 21, 0x260, 4, 0x0, 0x264, 0),
> > +       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000000,
> > +               0, 21, 0x270, 4, 0x0, 0x274, 0),
> > +       PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x00000000,
> > +               0, 21, 0x280, 4, 0x0, 0x284, 0),
> > +       PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0x00000000,
> > +               0, 21, 0x290, 4, 0x0, 0x294, 0),
> > +       PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0x00000000,
> > +               0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
> > +       PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0x00000000,
> > +               0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
> > +       PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0x00000000,
> > +               0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
> > +       PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0x00000000,
> > +               0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
> >  };
> >
> >  static void __init mtk_apmixedsys_init(struct device_node *node)
> > diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
> > index 5046852..e1b0a13 100644
> > --- a/drivers/clk/mediatek/clk-mt8183.c
> > +++ b/drivers/clk/mediatek/clk-mt8183.c
> > @@ -1121,34 +1121,34 @@
> >  };
> >
> >  static const struct mtk_pll_data plls[] = {
> > -       PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0x00000001,
> > +       PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0x00000000,
> >                 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0,
> >                 0x0204, 0, 0, armpll_div_table),
> > -       PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0x00000001,
> > +       PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0x00000000,
> >                 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0,
> >                 0x0214, 0, 0, armpll_div_table),
> > -       PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0x00000001,
> > +       PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0x00000000,
> >                 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0,
> >                 0x0294, 0, 0),
> > -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0x00000001,
> > +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0x00000000,
> >                 HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0,
> >                 0x0224, 0, 0),
> > -       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0x00000001,
> > +       PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0x00000000,
> >                 HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0,
> >                 0x0234, 0, 0),
> > -       PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000001,
> > +       PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000000,
> >                 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0,
> >                 mfgpll_div_table),
> > -       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000001,
> > +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000000,
> >                 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0),
> > -       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0x00000001,
> > +       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0x00000000,
> >                 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0),
> > -       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0x00000001,
> > +       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0x00000000,
> >                 HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0,
> >                 0x0274, 0, 0),
> > -       PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000001,
> > +       PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000000,
> >                 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0),
> > -       PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0x00000001,
> > +       PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0x00000000,
> >                 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
> >  };
> >
> > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> > index f440f2cd..3c79e1a 100644
> > --- a/drivers/clk/mediatek/clk-pll.c
> > +++ b/drivers/clk/mediatek/clk-pll.c
> > @@ -247,8 +247,10 @@ static int mtk_pll_prepare(struct clk_hw *hw)
> >         writel(r, pll->pwr_addr);
> >         udelay(1);
> >
> > -       r = readl(pll->base_addr + REG_CON0);
> > -       r |= pll->data->en_mask;
> > +       r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN;
> > +       writel(r, pll->base_addr + REG_CON0);
> > +
> > +       r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
> >         writel(r, pll->base_addr + REG_CON0);
> 
> As a small optimization, you can do:
> 
> if (pll->data->en_mask) {
>    r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
>    writel(r, pll->base_addr + REG_CON0);
> }
> 

Thanks, I'll do in next version.

> >
> >         __mtk_pll_tuner_enable(pll);
> > @@ -278,6 +280,10 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
> >         __mtk_pll_tuner_disable(pll);
> >
> >         r = readl(pll->base_addr + REG_CON0);
> > +       r &= ~pll->data->en_mask;
> 
> Move this to one line? (so that the code looks symmetrical, too?)
> 

Got it.

> > +       writel(r, pll->base_addr + REG_CON0);
> > +
> > +       r = readl(pll->base_addr + REG_CON0);
> >         r &= ~CON0_BASE_EN;
> 
> ditto?
> 

No problem.

> >         writel(r, pll->base_addr + REG_CON0);
> >
> > --
> > 1.8.1.1.dirty


^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v2 1/5] dt-bindings: ARM: Mediatek: Document bindings for MT8192
  2020-07-29  9:53   ` Enric Balletbo Serra
@ 2020-08-11  7:01     ` Weiyi Lu
  0 siblings, 0 replies; 17+ messages in thread
From: Weiyi Lu @ 2020-08-11  7:01 UTC (permalink / raw)
  To: Enric Balletbo Serra
  Cc: Matthias Brugger, Rob Herring, Stephen Boyd, Nicolas Boichat,
	James Liao, Linux ARM, linux-kernel,
	moderated list:ARM/Mediatek SoC support, linux-clk,
	srv_heupstream, Wendell Lin

On Wed, 2020-07-29 at 11:53 +0200, Enric Balletbo Serra wrote:
> Hi Weiyu,
> 
> Thanks for the patch, some comments below. I am not sure what
> maintainers think but your patches, in general, are really big and I'm
> wondering if wouldn't be better split by functionalities. Will make
> your series much longer but easy to review in my opinion. Anyway, I'm
> going to comment a few files but the comments can be applied to other
> files.
> 

Hi Enric,
You're right, these are big. I was trying to to add these documents
through the clock series at this stage. Do you suggest to send with
other functional series instead through the clock series?

> Missatge de Weiyi Lu <weiyi.lu@mediatek.com> del dia dc., 29 de jul.
> 2020 a les 10:46:
> >
> > This patch adds the binding documentation for apmixedsys, audsys,
> > camsys-raw, camsys, imgsys, imp_iic_wrap, infracfg, ipesys, mdpsys,
> > mfgcfg, mmsys, msdc, pericfg, scp-adsp, topckgen, vdecsys-soc,
> > vdecsys and vencsys for Mediatek MT8192.
> >
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > ---
> >  .../bindings/arm/mediatek/mediatek,apmixedsys.txt  |  1 +
> >  .../bindings/arm/mediatek/mediatek,audsys.txt      |  1 +
> >  .../bindings/arm/mediatek/mediatek,camsys-raw.yaml | 40 ++++++++++++++++++++
> >  .../bindings/arm/mediatek/mediatek,camsys.txt      |  1 +
> >  .../bindings/arm/mediatek/mediatek,imgsys.txt      |  2 +
> >  .../arm/mediatek/mediatek,imp_iic_wrap.yaml        | 43 ++++++++++++++++++++++
> >  .../bindings/arm/mediatek/mediatek,infracfg.txt    |  1 +
> >  .../bindings/arm/mediatek/mediatek,ipesys.txt      |  1 +
> >  .../bindings/arm/mediatek/mediatek,mdpsys.yaml     | 38 +++++++++++++++++++
> >  .../bindings/arm/mediatek/mediatek,mfgcfg.txt      |  1 +
> >  .../bindings/arm/mediatek/mediatek,mmsys.txt       |  1 +
> >  .../bindings/arm/mediatek/mediatek,msdc.yaml       | 39 ++++++++++++++++++++
> >  .../bindings/arm/mediatek/mediatek,pericfg.yaml    |  1 +
> >  .../bindings/arm/mediatek/mediatek,scp-adsp.yaml   | 38 +++++++++++++++++++
> >  .../bindings/arm/mediatek/mediatek,topckgen.txt    |  1 +
> >  .../arm/mediatek/mediatek,vdecsys-soc.yaml         | 38 +++++++++++++++++++
> >  .../bindings/arm/mediatek/mediatek,vdecsys.txt     |  1 +
> >  .../bindings/arm/mediatek/mediatek,vencsys.txt     |  1 +
> >  18 files changed, 249 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml
> >  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,imp_iic_wrap.yaml
> >  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdpsys.yaml
> >  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml
> >  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,scp-adsp.yaml
> >  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
> > index bd7a0fa..6942ad4 100644
> > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
> > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
> > @@ -17,6 +17,7 @@ Required Properties:
> >         - "mediatek,mt8135-apmixedsys"
> >         - "mediatek,mt8173-apmixedsys"
> >         - "mediatek,mt8183-apmixedsys", "syscon"
> > +       - "mediatek,mt8192-apmixedsys", "syscon"
> >         - "mediatek,mt8516-apmixedsys"
> >  - #clock-cells: Must be 1
> >
> > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
> > index 38309db..fdcb267 100644
> > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
> > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
> > @@ -12,6 +12,7 @@ Required Properties:
> >         - "mediatek,mt7622-audsys", "syscon"
> >         - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
> >         - "mediatek,mt8183-audiosys", "syscon"
> > +       - "mediatek,mt8192-audsys", "syscon"
> >         - "mediatek,mt8516-audsys", "syscon"
> >  - #clock-cells: Must be 1
> >
> > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml
> > new file mode 100644
> > index 0000000..db6f425
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml
> > @@ -0,0 +1,40 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,camsys-raw.yaml*__;Iw!!CTRNKA9wMg0ARbw!3w84XoXGRAkVX5zxTBA4o5h7EkKiKBuCO5VZDMmx94qoJK357wbTnjT9XN6SRPQc$ 
> > +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!3w84XoXGRAkVX5zxTBA4o5h7EkKiKBuCO5VZDMmx94qoJK357wbTnjT9XGLX7Fq7$ 
> > +
> > +title: MediaTek CAMSYS RAW Controller
> > +
> > +maintainers:
> > +  - Weiyi Lu <weiyi.lu@mediatek.com>
> > +
> > +description:
> > +  The Mediatek camsys raw controller provides various clocks to the system.
> > +
> 
> It only provides clocks or also provides configuration registers
> non-clock related?
> 

Thanks for reminding, it also provides other configuration registers.
I'll update the description in next version.

> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - mediatek,mt8192-camsys_rawa
> > +          - mediatek,mt8192-camsys_rawb
> > +          - mediatek,mt8192-camsys_rawc
> > +      - const: syscon
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  '#clock-cells':
> > +    const: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +
> > +examples:
> > +  - |
> > +    camsys_rawa: camsys_rawa@1a04f000 {
> 
> I think that this should be  "syscon@1a04f000", since node names are
> supposed to match the class of the device instead of the name of the
> device.
> 

Got it, I'll fix in next version.

> Just because I am curious, can you show me an example of
> "mediatek,mt8192-camsys_rawb" or "mediatek,mt8192-camsys_rawc"? It's a
> different address space?
> 
> > +        compatible = "mediatek,mt8192-camsys_rawa", "syscon";
> > +        reg = <0 0x1a04f000 0 0x1000>;
> > +        #clock-cells = <1>;
> > +    };
> 

OK, I'll add those in next version.

> [snip]


^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v2 5/5] clk: mediatek: Add MT8192 clock support
  2020-07-29  9:32   ` [PATCH v2 5/5] clk: mediatek: Add MT8192 clock support Enric Balletbo Serra
@ 2020-08-11  7:03     ` Weiyi Lu
  0 siblings, 0 replies; 17+ messages in thread
From: Weiyi Lu @ 2020-08-11  7:03 UTC (permalink / raw)
  To: Enric Balletbo Serra
  Cc: Rob Herring, Nicolas Boichat, srv_heupstream, James Liao,
	Stephen Boyd, linux-kernel,
	moderated list:ARM/Mediatek SoC support, Matthias Brugger,
	Wendell Lin, linux-clk, Linux ARM

On Wed, 2020-07-29 at 11:32 +0200, Enric Balletbo Serra wrote:
> Hi Weiyi,
> 
> Thank you for your patch. Some few comment below, I'll focus on
> clk-mt8192-mm file, but I think can apply to other files too.
> 
> [snip]
> 
> > diff --git a/drivers/clk/mediatek/clk-mt8192-mm.c b/drivers/clk/mediatek/clk-mt8192-mm.c
> > new file mode 100644
> > index 0000000..02eef24
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8192-mm.c
> > @@ -0,0 +1,108 @@
> > +// SPDX-License-Identifier: GPL-2.0
> 
> nit: Although is a valid license identifier for the kernel would be
> better to use the non-deprecated form by SPDX, GPL-2.0-only
> 
> > +//
> > +// Copyright (c) 2020 MediaTek Inc.
> > +// Author: Weiyi Lu <weiyi.lu@mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> > +
> > +#include <dt-bindings/clock/mt8192-clk.h>
> > +
> > +static const struct mtk_gate_regs mm0_cg_regs = {
> > +       .set_ofs = 0x104,
> > +       .clr_ofs = 0x108,
> > +       .sta_ofs = 0x100,
> > +};
> > +
> > +static const struct mtk_gate_regs mm1_cg_regs = {
> > +       .set_ofs = 0x114,
> > +       .clr_ofs = 0x118,
> > +       .sta_ofs = 0x110,
> > +};
> > +
> > +static const struct mtk_gate_regs mm2_cg_regs = {
> > +       .set_ofs = 0x1a4,
> > +       .clr_ofs = 0x1a8,
> > +       .sta_ofs = 0x1a0,
> > +};
> > +
> > +#define GATE_MM0(_id, _name, _parent, _shift)                  \
> > +       GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift,     \
> > +               &mtk_clk_gate_ops_setclr)
> 
> nit: You can take advantage of the new line length limit, which is now
> 100 characters.
> 

OK, thanks for reminding.

> > +
> > +#define GATE_MM1(_id, _name, _parent, _shift)                  \
> > +       GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift,     \
> > +               &mtk_clk_gate_ops_setclr)
> > +
> 
> ditto
> 

Got it.

> > +#define GATE_MM2(_id, _name, _parent, _shift)                  \
> > +       GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift,     \
> > +               &mtk_clk_gate_ops_setclr)
> > +
> 
> ditto
> 
> > +static const struct mtk_gate mm_clks[] = {
> > +       /* MM0 */
> > +       GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "disp_sel", 0),
> > +       GATE_MM0(CLK_MM_DISP_CONFIG, "mm_disp_config", "disp_sel", 1),
> > +       GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "disp_sel", 2),
> > +       GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "disp_sel", 3),
> > +       GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "disp_sel", 4),
> > +       GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp_sel", 5),
> > +       GATE_MM0(CLK_MM_DISP_UFBC_WDMA0, "mm_disp_ufbc_wdma0", "disp_sel", 6),
> > +       GATE_MM0(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "disp_sel", 7),
> > +       GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "disp_sel", 8),
> > +       GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "disp_sel", 9),
> > +       GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "disp_sel", 10),
> > +       GATE_MM0(CLK_MM_SMI_INFRA, "mm_smi_infra", "disp_sel", 11),
> > +       GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "disp_sel", 12),
> > +       GATE_MM0(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "disp_sel", 13),
> > +       GATE_MM0(CLK_MM_DISP_DSC_WRAP0, "mm_disp_dsc_wrap0", "disp_sel", 14),
> > +       GATE_MM0(CLK_MM_DSI0, "mm_dsi0", "disp_sel", 15),
> > +       GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "disp_sel", 16),
> > +       GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "disp_sel", 17),
> > +       GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "disp_sel", 18),
> > +       GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1", "disp_sel", 19),
> > +       GATE_MM0(CLK_MM_MDP_TDSHP4, "mm_mdp_tdshp4", "disp_sel", 20),
> > +       GATE_MM0(CLK_MM_MDP_RSZ4, "mm_mdp_rsz4", "disp_sel", 21),
> > +       GATE_MM0(CLK_MM_MDP_AAL4, "mm_mdp_aal4", "disp_sel", 22),
> > +       GATE_MM0(CLK_MM_MDP_HDR4, "mm_mdp_hdr4", "disp_sel", 23),
> > +       GATE_MM0(CLK_MM_MDP_RDMA4, "mm_mdp_rdma4", "disp_sel", 24),
> > +       GATE_MM0(CLK_MM_MDP_COLOR4, "mm_mdp_color4", "disp_sel", 25),
> > +       GATE_MM0(CLK_MM_DISP_Y2R0, "mm_disp_y2r0", "disp_sel", 26),
> > +       GATE_MM0(CLK_MM_SMI_GALS, "mm_smi_gals", "disp_sel", 27),
> > +       GATE_MM0(CLK_MM_DISP_OVL2_2L, "mm_disp_ovl2_2l", "disp_sel", 28),
> > +       GATE_MM0(CLK_MM_DISP_RDMA4, "mm_disp_rdma4", "disp_sel", 29),
> > +       GATE_MM0(CLK_MM_DISP_DPI0, "mm_disp_dpi0", "disp_sel", 30),
> > +       /* MM1 */
> > +       GATE_MM1(CLK_MM_SMI_IOMMU, "mm_smi_iommu", "disp_sel", 0),
> > +       /* MM2 */
> > +       GATE_MM2(CLK_MM_DSI_DSI0, "mm_dsi_dsi0", "disp_sel", 0),
> > +       GATE_MM2(CLK_MM_DPI_DPI0, "mm_dpi_dpi0", "dpi_sel", 8),
> > +       GATE_MM2(CLK_MM_26MHZ, "mm_26mhz", "clk26m", 24),
> > +       GATE_MM2(CLK_MM_32KHZ, "mm_32khz", "clk32k", 25),
> > +};
> > +
> > +static int clk_mt8192_mm_probe(struct platform_device *pdev)
> > +{
> > +       struct device *dev = &pdev->dev;
> > +       struct device_node *node = dev->parent->of_node;
> > +       struct clk_onecell_data *clk_data;
> > +
> > +       clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
> 
> mtk_alloc_clk_data can return NULL
> 
>            if (!clk_data)
>               return -ENOMEM;
> 
> > +
> > +       mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
> > +                       clk_data);
> > +
> 
> The above function can fail, better check for error
> 
>          if (ret)
>              return ret;
> 

OK, I'll fix in next version.

> > +       return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > +}
> > +
> > +
> 
> No need for double line spacing.
> 

Got it.

> > +static struct platform_driver clk_mt8192_mm_drv = {
> > +       .probe = clk_mt8192_mm_probe,
> > +       .driver = {
> > +               .name = "clk-mt8192-mm",
> > +       },
> > +};
> > +
> > +builtin_platform_driver(clk_mt8192_mm_drv);
> 
> [snip]
> 
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> https://urldefense.com/v3/__http://lists.infradead.org/mailman/listinfo/linux-mediatek__;!!CTRNKA9wMg0ARbw!3-tRGg8pYRBy0yJ4A9LkGuveXPD7gziSzHyQDExjoUi3iiLooDu5k2Sbx2kWQZtW$ 


^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v2 4/5] clk: mediatek: Add configurable enable control to mtk_pll_data
  2020-08-11  6:43     ` Weiyi Lu
@ 2020-08-11  7:28       ` Nicolas Boichat
  2020-08-11  9:31         ` Weiyi Lu
  0 siblings, 1 reply; 17+ messages in thread
From: Nicolas Boichat @ 2020-08-11  7:28 UTC (permalink / raw)
  To: Weiyi Lu
  Cc: Rob Herring, srv_heupstream, James Liao, Stephen Boyd, lkml,
	moderated list:ARM/Mediatek SoC support, Matthias Brugger,
	Wendell Lin, linux-clk, linux-arm Mailing List

On Tue, Aug 11, 2020 at 2:43 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
> [...]
> > > +       writel(r, pll->en_addr);
> > >
> > >         r = readl(pll->pwr_addr) | CON0_ISO_EN;
> > >         writel(r, pll->pwr_addr);
> > > @@ -327,6 +327,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
> > >                 pll->tuner_addr = base + data->tuner_reg;
> > >         if (data->tuner_en_reg)
> > >                 pll->tuner_en_addr = base + data->tuner_en_reg;
> > > +       if (data->en_reg)
> > > +               pll->en_addr = base + data->en_reg;
> > > +       else
> > > +               pll->en_addr = pll->base_addr + REG_CON0;
> >
> > Don't you need to set pll->data->pll_en_bit to CON0_BASE_EN here?
> > (which probably means that you need to add a pll->en_bit field to
> > struct mtk_clk_pll)
> >
>
> Because all mtk_clk_pll data are static variables, en_bit would be 0 if
> NO value assigned.

Wow, you're right, but this is a little bit subtle. I wonder if it's
worth adding a small comment? (either here or in struct mtk_pll_data)

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v2 4/5] clk: mediatek: Add configurable enable control to mtk_pll_data
  2020-08-11  7:28       ` Nicolas Boichat
@ 2020-08-11  9:31         ` Weiyi Lu
  0 siblings, 0 replies; 17+ messages in thread
From: Weiyi Lu @ 2020-08-11  9:31 UTC (permalink / raw)
  To: Nicolas Boichat
  Cc: Rob Herring, srv_heupstream, James Liao, Stephen Boyd, lkml,
	moderated list:ARM/Mediatek SoC support, Matthias Brugger,
	Wendell Lin, linux-clk, linux-arm Mailing List

On Tue, 2020-08-11 at 15:28 +0800, Nicolas Boichat wrote:
> On Tue, Aug 11, 2020 at 2:43 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
> > [...]
> > > > +       writel(r, pll->en_addr);
> > > >
> > > >         r = readl(pll->pwr_addr) | CON0_ISO_EN;
> > > >         writel(r, pll->pwr_addr);
> > > > @@ -327,6 +327,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
> > > >                 pll->tuner_addr = base + data->tuner_reg;
> > > >         if (data->tuner_en_reg)
> > > >                 pll->tuner_en_addr = base + data->tuner_en_reg;
> > > > +       if (data->en_reg)
> > > > +               pll->en_addr = base + data->en_reg;
> > > > +       else
> > > > +               pll->en_addr = pll->base_addr + REG_CON0;
> > >
> > > Don't you need to set pll->data->pll_en_bit to CON0_BASE_EN here?
> > > (which probably means that you need to add a pll->en_bit field to
> > > struct mtk_clk_pll)
> > >
> >
> > Because all mtk_clk_pll data are static variables, en_bit would be 0 if
> > NO value assigned.
> 
> Wow, you're right, but this is a little bit subtle. I wonder if it's
> worth adding a small comment? (either here or in struct mtk_pll_data)

OK, I'll add comment for en_bit


^ permalink raw reply	[flat|nested] 17+ messages in thread

end of thread, back to index

Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-29  8:44 [PATCH v2 0/5] Mediatek MT8192 clock support Weiyi Lu
2020-07-29  8:44 ` [PATCH v2 1/5] dt-bindings: ARM: Mediatek: Document bindings for MT8192 Weiyi Lu
2020-07-29  9:53   ` Enric Balletbo Serra
2020-08-11  7:01     ` Weiyi Lu
2020-07-29  8:44 ` [PATCH v2 2/5] clk: mediatek: Add dt-bindings for MT8192 clocks Weiyi Lu
2020-07-29  8:44 ` [PATCH v2 3/5] clk: mediatek: Fix asymmetrical PLL enable and disable control Weiyi Lu
2020-07-29 10:51   ` Nicolas Boichat
2020-07-29 11:02     ` Nicolas Boichat
2020-08-11  6:34       ` Weiyi Lu
2020-08-11  6:50     ` Weiyi Lu
2020-07-29  8:44 ` [PATCH v2 4/5] clk: mediatek: Add configurable enable control to mtk_pll_data Weiyi Lu
2020-07-29 10:58   ` Nicolas Boichat
2020-08-11  6:43     ` Weiyi Lu
2020-08-11  7:28       ` Nicolas Boichat
2020-08-11  9:31         ` Weiyi Lu
     [not found] ` <1596012277-8448-6-git-send-email-weiyi.lu@mediatek.com>
2020-07-29  9:32   ` [PATCH v2 5/5] clk: mediatek: Add MT8192 clock support Enric Balletbo Serra
2020-08-11  7:03     ` Weiyi Lu

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