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b5409c2b-e6d4-49be-68a3-08daa6b503c9 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Oct 2022 09:36:00.8856 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: dac28005-13e0-41b8-8280-7663835f2b1d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: XShQoyMZDhjBJ+OWh7XSkHroYG70j4XA7SrD2N6JoldjW5yPRnswMQOl40ezJ7gcWqB7IRcTgjxDAjvWAUm6HA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR19MB4416 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Language: en-US Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hi Stephen,=0A=0AOn 30/9/2022 9:01 am, Stephen Boyd wrote:=0A> This email w= as sent from outside of MaxLinear.=0A>=20=0A>=20=0A> Quoting Rahul Tanwar (= 2022-09-28 22:45:59)=0A>> On 29/9/2022 8:17 am, Stephen Boyd wrote:=0A>>> T= his email was sent from outside of MaxLinear.=0A>>>=0A>>>=0A>>> Quoting Rah= ul Tanwar (2022-09-21 23:24:26)=0A>>>> In MxL's LGM SoC, gate clocks are su= pposed to be enabled or disabled=0A>>>> from EPU (power management IP) in c= ertain power saving modes. If gate=0A>>>> clocks are allowed to be enabled/= disabled from CGU clk driver, then=0A>>>> there arises a conflict where in = case clk driver disables a gate clk,=0A>>>> and then EPU tries to disable t= he same gate clk, then it will hang=0A>>>> polling for the clk gated succes= sful status.=0A>>>=0A>>> Is there any point in registering these clks when = they're not supposed=0A>>> to be controlled from Linux?=0A>>=0A>>=0A>> As m= entioned in the full commit log, only reason to register these clks=0A>> is= to be backward compatible with older versions of similar SoC's which=0A>> = reuse the same clk CGU IP but do not use same power management IP. Such=0A>= > older SoCs also use the same clk driver and for them these clks are=0A>> = required to be controlled by clk ops from Linux.=0A>>=0A>=20=0A> Why is the= clk driver probing on the new SoCs? Is it providing=0A> something? Can we = detect that the power management IP exists and not=0A> register these clks?= =0A>=20=0A=0AWe discussed in the team about not registering gate clks at al= l as you=20=0Amentioned. But if we do that, all peripheral drivers that use= these clks=20=0Awould need modifications so their probe does not fail due = to failure=20=0Areturns of clk related standard calls for e.g devm_clk_get(= ),=20=0Aclk_prepare_enable(). These are standard calls in probe for all the= =20=0Adrivers and a lot of them use gate clks. So this would need a lot of= =20=0Achanges with possibility of breaking working functionalities.=0A=0AAl= so, i incorrectly mentioned about the reason being backward=20=0Acompatibil= ity with older SoCs. Main reason is to support different power=20=0Aprofile= s use cases as per end product requirements some of which might=20=0Acontro= l it from clk framework i.e. this driver. We keep a internal=20=0Adriver fl= ag just for this purpose to provide this flexibility depending=20=0Aon the = use case which is what we have used here.=0A=0AI am sending v3 with more cl= ear & correct description about it to=20=0Ajustify the need for these chang= es.=0A=0AThanks,=0ARahul=0A=0A=0A>=20=0A=0A