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8bb2ba66-49d9-414e-61f6-08daa1e143b2 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Sep 2022 06:10:10.1667 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: dac28005-13e0-41b8-8280-7663835f2b1d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: MG2ZlNRjjR8I9hqk/WprdricDCh4cQwhiyEkcN3ZniMvEeuULRLrjRqGFk+qR7bHgElVl2KH7Rd96O7cF2WhxQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR19MB4279 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Language: en-US Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 29/9/2022 8:20 am, Stephen Boyd wrote:=0A> This email was sent from outs= ide of MaxLinear.=0A>=20=0A>=20=0A> Quoting Rahul Tanwar (2022-09-21 23:24:= 27)=0A>> Some clocks support parent clock dividers but they do not=0A>> sup= port clock gating (clk enable/disable). Such types of=0A>> clocks might cal= l API's for get/set_reg_val routines with=0A>> width as 0 during clk_prepar= e_enable() call. Handle such=0A>> cases by first validating width during cl= k_prepare_enable()=0A>> while still supporting clk_set_rate() correctly.=0A= >>=0A>> Signed-off-by: Rahul Tanwar =0A>> ---=0A>> = drivers/clk/x86/clk-cgu.h | 30 ++++++++++++++++++++++++++----=0A>> 1 fil= e changed, 26 insertions(+), 4 deletions(-)=0A>>=0A>> diff --git a/drivers/= clk/x86/clk-cgu.h b/drivers/clk/x86/clk-cgu.h=0A>> index 73ce84345f81..46da= f9ebd6c9 100644=0A>> --- a/drivers/clk/x86/clk-cgu.h=0A>> +++ b/drivers/clk= /x86/clk-cgu.h=0A>> @@ -299,29 +299,51 @@ struct lgm_clk_branch {=0A>> st= atic inline void lgm_set_clk_val(struct regmap *membase, u32 reg,=0A>> = u8 shift, u8 width, u32 set_val)=0A>> {= =0A>> - u32 mask =3D (GENMASK(width - 1, 0) << shift);=0A>> + u= 32 mask;=0A>>=0A>> + /*=0A>> + * Some clocks support parent cl= ock dividers but they do not=0A>> + * support clock gating (clk enab= le/disable). Such types of=0A>> + * clocks might call this function = with width as 0 during=0A>> + * clk_prepare_enable() call. Handle su= ch cases by not doing=0A>> + * anything during clk_prepare_enable() = but handle clk_set_rate()=0A>> + * correctly=0A>> + */=0A>> += if (!width)=0A>> + return;=0A>=20=0A> Why are the clk_= ops assigned in a way that makes the code get here? Why=0A> can't we have d= ifferent clk_ops, or not register the clks at all, when=0A> the hardware ca= n't be written?=0A=0A=0AThe hardware can actually be written for such clks = but only for=20=0Aclk_set_rate() op for setting the clk rate. Just that har= dware does not=20=0Aprovide any way to enable/disable such clks.=0A=0AAlter= native way to handle such clks could be that the clk consumer does=0Anot in= voke clk_prepare_enable() before invoking clk_set_rate(). But we=0Awant to = avoid making changes in the clk consumer code to keep it=20=0Astandard. And= handle it here by just validating the width parameter.=0A=0AThanks,=0ARahu= l=0A=0A=0A>=20=0A>> +=0A>> + mask =3D (GENMASK(width - 1, 0) << shift= );=0A>> regmap_update_bits(membase, reg, mask, set_val << shift);= =0A>=20=0A>=20=0A=0A