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From: Biju Das <biju.das@bp.renesas.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	linux-clk <linux-clk@vger.kernel.org>,
	Simon Horman <horms@verge.net.au>,
	Chris Paterson <Chris.Paterson2@renesas.com>,
	Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Subject: RE: [PATCH 3/5] clk: renesas: r8a774c0: Add TMU clock
Date: Fri, 1 Feb 2019 14:02:40 +0000	[thread overview]
Message-ID: <OSBPR01MB21034B18C8F3C490511DF7E9B8920@OSBPR01MB2103.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <CAMuHMdXDuTTy5Ko2bgSBceN1QZ+uhVTFWFJksyWX4GpMomny8w@mail.gmail.com>

Hi Geert,

Thanks for the feedback.

Regards,
Biju

> Subject: Re: [PATCH 3/5] clk: renesas: r8a774c0: Add TMU clock
>
> Hi Biju,
>
> On Fri, Feb 1, 2019 at 11:16 AM Biju Das <biju.das@bp.renesas.com> wrote:
> > This patch adds TMU clock to the R8A774C0 SoC.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> > @@ -119,6 +119,11 @@ static const struct cpg_core_clk
> > r8a774c0_core_clks[] __initconst = {  };
> >
> >  static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
> > +       DEF_MOD("tmu4",                  121,   R8A774C0_CLK_S0D6),
>
> RZ/G2 Hardware User's Manual rev. 0.61 says S0D6C?
>
Yes you are correct, I missed  it.
> > +       DEF_MOD("tmu3",                  122,   R8A774C0_CLK_S3D2),
> > +       DEF_MOD("tmu2",                  123,   R8A774C0_CLK_S3D2),
> > +       DEF_MOD("tmu1",                  124,   R8A774C0_CLK_S3D2),
>
> S3D2C? (all three)

Yes you are correct. Will send v2.

> Since these are timers, it should be easy to verify the actual parent clock
> rates.

Will check.

> > +       DEF_MOD("tmu0",                  125,   R8A774C0_CLK_CP),
> >         DEF_MOD("scif5",                 202,   R8A774C0_CLK_S3D4C),
> >         DEF_MOD("scif4",                 203,   R8A774C0_CLK_S3D4C),
> >         DEF_MOD("scif3",                 204,   R8A774C0_CLK_S3D4C),

Regards,
Biju



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

      reply	other threads:[~2019-02-01 14:02 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1549015841-33536-1-git-send-email-biju.das@bp.renesas.com>
2019-02-01 10:10 ` [PATCH 3/5] clk: renesas: r8a774c0: Add TMU clock Biju Das
2019-02-01 13:52   ` Geert Uytterhoeven
2019-02-01 14:02     ` Biju Das [this message]

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