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Wed, 30 Jan 2019 18:43:15 +0000 From: Fabrizio Castro To: Simon Horman , Geert Uytterhoeven CC: Magnus Damm , "linux-renesas-soc@vger.kernel.org" , "linux-clk@vger.kernel.org" , Biju Das Subject: RE: [PATCH/RFT v2 6/6] clk: renesas: r8a7745: Implement Z2 as a variable clock Thread-Topic: [PATCH/RFT v2 6/6] clk: renesas: r8a7745: Implement Z2 as a variable clock Thread-Index: AQHUuH/mcSaS8mC4AEaiF994lYJ6IaXIFuwA Date: Wed, 30 Jan 2019 18:43:14 +0000 Message-ID: References: <20190130094029.9604-1-horms+renesas@verge.net.au> <20190130094029.9604-7-horms+renesas@verge.net.au> In-Reply-To: <20190130094029.9604-7-horms+renesas@verge.net.au> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=fabrizio.castro@bp.renesas.com; x-originating-ip: [193.141.220.21] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;TY1PR01MB1801;20:Nb+CLu+6YnfjlxfMQ2lKNd812R+kS1zSFs3nqRo7novodIdkbOteeF6lL/1gq2haF00xj7Pr7haIPPyEnkHBV85qBlEmFKG5DtOKHHIkXMc4bmUgdgCug0IME065ceR5il6zRLlpRNDL75mBUxH1as+X8hx3ZIRThIm/Mn3ztUo= x-ms-office365-filtering-correlation-id: ba8c1e5e-b669-4c14-974f-08d686e2cb5e x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600110)(711020)(4605077)(4618075)(2017052603328)(7153060)(7193020);SRVR:TY1PR01MB1801; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-Network-Message-Id: ba8c1e5e-b669-4c14-974f-08d686e2cb5e X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Jan 2019 18:43:14.9796 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY1PR01MB1801 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hello Simon, Thank you for your patch! > From: Simon Horman > Sent: 30 January 2019 09:40 > Subject: [PATCH/RFT v2 6/6] clk: renesas: r8a7745: Implement Z2 as a vari= able clock > > On the RZ/G2E (r8a7745) SoC the Z2 clock is not a fixed clock. Did you mean RZ/G1E here? > Rather it is a clock with: > > * A parent of CLK_PLL0 running at 4.8GHz > * A fixed divider of 4 > * A variable divider controlled by the Z2FC bits of the RFQCRC register My understanding is that those statements don't apply to the RZ/G1E, but th= ey do apply to the RZ/G2E > > This can be described using the DEF_GEN3_Z with a clock type of > CLK_TYPE_GEN3_Z2. > > This change is made with reference to the User's Manual v0.61. That's the version of the User's Manual for the RZ/G2E, but this patch is f= or the RZ/G1E > > Fixes: 9127d54bb894 ("clk: renesas: cpg-mssr: Add R8A7745 support") > Signed-off-by: Simon Horman > --- > drivers/clk/renesas/r8a7745-cpg-mssr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas= /r8a7745-cpg-mssr.c > index 493874e5ebee..f2ea72d9d663 100644 > --- a/drivers/clk/renesas/r8a7745-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c > @@ -53,7 +53,7 @@ static const struct cpg_core_clk r8a7745_core_clks[] __= initconst =3D { > DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI,CLK_PLL1_DIV2), > DEF_BASE("rcan", R8A7745_CLK_RCAN, CLK_TYPE_GEN2_RCAN,CLK_USB_EXTAL), > > -DEF_FIXED("z2", R8A7745_CLK_Z2,CLK_PLL0, 1, 1), > +DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL0, 4), Perhaps this change was made to the wrong file? Thanks, Fab > DEF_FIXED("zg", R8A7745_CLK_ZG,CLK_PLL1, 6, 1), > DEF_FIXED("zx", R8A7745_CLK_ZX,CLK_PLL1, 3, 1), > DEF_FIXED("zs", R8A7745_CLK_ZS,CLK_PLL1, 6, 1), > -- > 2.11.0 Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, B= uckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered= No. 04586709.