From: Leonard Crestez <leonard.crestez@nxp.com>
To: Abel Vesa <abel.vesa@nxp.com>, Shawn Guo <shawnguo@kernel.org>,
Stephen Boyd <sboyd@kernel.org>
Cc: Aisheng Dong <aisheng.dong@nxp.com>,
Sascha Hauer <kernel@pengutronix.de>,
Jacky Bai <ping.bai@nxp.com>, Peng Fan <peng.fan@nxp.com>,
dl-linux-imx <linux-imx@nxp.com>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 5/9] clk: imx: Rename sccg and frac pll register to suggest clk_hw
Date: Tue, 19 Nov 2019 16:32:27 +0000 [thread overview]
Message-ID: <VI1PR04MB702360DD60D297B19F346B7FEE4C0@VI1PR04MB7023.eurprd04.prod.outlook.com> (raw)
In-Reply-To: 1574172496-12987-6-git-send-email-abel.vesa@nxp.com
On 2019-11-19 4:08 PM, Abel Vesa wrote:
> Renaming the imx_clk_frac_pll and imx_clk_sccg_pll register functions to
> imx_clk_hw_frac_pll, respectively imx_clk_hw_sccg_pll to be more obvious
> that they are clk_hw based
On a somewake unrelated note there is no "SCCG", reference manual refers
to this as "SSCG": "Spread Sprectum Clock Generator"
These wrapping macros don't correctly forward null or error either.
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
> drivers/clk/imx/clk-frac-pll.c | 7 ++++---
> drivers/clk/imx/clk-sccg-pll.c | 4 ++--
> drivers/clk/imx/clk.h | 12 ++++++++++--
> 3 files changed, 16 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c
> index fece503..101e0a3 100644
> --- a/drivers/clk/imx/clk-frac-pll.c
> +++ b/drivers/clk/imx/clk-frac-pll.c
> @@ -201,8 +201,9 @@ static const struct clk_ops clk_frac_pll_ops = {
> .set_rate = clk_pll_set_rate,
> };
>
> -struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
> - void __iomem *base)
> +struct clk_hw *imx_clk_hw_frac_pll(const char *name,
> + const char *parent_name,
> + void __iomem *base)
> {
> struct clk_init_data init;
> struct clk_frac_pll *pll;
> @@ -230,5 +231,5 @@ struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
> return ERR_PTR(ret);
> }
>
> - return hw->clk;
> + return hw;
> }
> diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c
> index 5d65f65..2cf8748 100644
> --- a/drivers/clk/imx/clk-sccg-pll.c
> +++ b/drivers/clk/imx/clk-sccg-pll.c
> @@ -506,7 +506,7 @@ static const struct clk_ops clk_sccg_pll_ops = {
> .determine_rate = clk_sccg_pll_determine_rate,
> };
>
> -struct clk *imx_clk_sccg_pll(const char *name,
> +struct clk_hw *imx_clk_hw_sccg_pll(const char *name,
> const char * const *parent_names,
> u8 num_parents,
> u8 parent, u8 bypass1, u8 bypass2,
> @@ -545,5 +545,5 @@ struct clk *imx_clk_sccg_pll(const char *name,
> return ERR_PTR(ret);
> }
>
> - return hw->clk;
> + return hw;
> }
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
> index 71b21ab..15c6f54 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -115,6 +115,14 @@ extern struct imx_pll14xx_clk imx_1443x_pll;
> #define imx_clk_pllv2(name, parent, base) \
> imx_clk_hw_pllv2(name, parent, base)->clk
>
> +#define imx_clk_frac_pll(name, parent_name, base) \
> + imx_clk_hw_frac_pll(name, parent_name, base)->clk
> +
> +#define imx_clk_sccg_pll(name, parent_names, num_parents, parent,\
> + bypass1, bypass2, base, flags) \
> + imx_clk_hw_sccg_pll(name, parent_names, num_parents, parent,\
> + bypass1, bypass2, base, flags)->clk \
> +
> struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
> void __iomem *base, const struct imx_pll14xx_clk *pll_clk);
>
> @@ -124,10 +132,10 @@ struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,
> struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
> void __iomem *base);
>
> -struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
> +struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
> void __iomem *base);
>
> -struct clk *imx_clk_sccg_pll(const char *name,
> +struct clk_hw *imx_clk_hw_sccg_pll(const char *name,
> const char * const *parent_names,
> u8 num_parents,
> u8 parent, u8 bypass1, u8 bypass2,
>
next prev parent reply other threads:[~2019-11-19 16:32 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-19 14:08 [PATCH 0/9] clk: imx: Trivial cleanups for clk_hw based API Abel Vesa
2019-11-19 14:08 ` [PATCH 1/9] clk: imx: Replace all the clk based helpers with macros Abel Vesa
2019-11-19 16:28 ` Leonard Crestez
2019-11-19 14:08 ` [PATCH 2/9] clk: imx: pllv1: Switch to clk_hw based API Abel Vesa
2019-11-19 14:08 ` [PATCH 3/9] clk: imx: pllv2: " Abel Vesa
2019-11-19 14:08 ` [PATCH 4/9] clk: imx: imx7ulp composite: Rename to show is clk_hw based Abel Vesa
2019-11-19 14:08 ` [PATCH 5/9] clk: imx: Rename sccg and frac pll register to suggest clk_hw Abel Vesa
2019-11-19 16:32 ` Leonard Crestez [this message]
2019-11-19 14:08 ` [PATCH 6/9] clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw based Abel Vesa
2019-11-19 14:08 ` [PATCH 7/9] clk: imx: Rename the imx_clk_pfdv2 " Abel Vesa
2019-11-19 14:08 ` [PATCH 8/9] clk: imx: Rename the imx_clk_divider_gate " Abel Vesa
2019-11-19 14:08 ` [PATCH 9/9] clk: imx7up: Rename the clks to hws Abel Vesa
2019-11-22 7:56 ` [PATCH 0/9] clk: imx: Trivial cleanups for clk_hw based API Peng Fan
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